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From: nasm-bot f. H. P. A. <hp...@zy...> - 2013-11-24 19:54:27
|
Commit-ID: 8b0e5a34fcbc66e04cec3fc297c20a34e79c4dc0 Gitweb: http://repo.or.cz/w/nasm.git?a=commitdiff;h=8b0e5a34fcbc66e04cec3fc297c20a34e79c4dc0 Author: H. Peter Anvin <hp...@zy...> AuthorDate: Sun, 24 Nov 2013 11:49:24 -0800 Committer: H. Peter Anvin <hp...@zy...> CommitDate: Sun, 24 Nov 2013 11:49:24 -0800 iflag: remove C99 constructs, don't hardcode the number of words Avoid using C99 constructs when not necessary. Don't hardcode the number of words when we can autodiscover them. Signed-off-by: H. Peter Anvin <hp...@zy...> --- iflag.h | 4 ---- insns-iflags.pl | 53 +++++++++++++++++++++++++++-------------------------- 2 files changed, 27 insertions(+), 30 deletions(-) diff --git a/iflag.h b/iflag.h index d08249e..72929ee 100644 --- a/iflag.h +++ b/iflag.h @@ -37,10 +37,6 @@ int ilog2_32(uint32_t v); * * iflag_t is defined to store these flags. */ -typedef struct { - uint32_t field[4]; -} iflag_t; - #include "iflaggen.h" #define IF_GENBIT(bit) (UINT32_C(1) << (bit)) diff --git a/insns-iflags.pl b/insns-iflags.pl index 77eefee..632bba3 100644 --- a/insns-iflags.pl +++ b/insns-iflags.pl @@ -135,6 +135,19 @@ my %insns_flag_bit = ( my %insns_flag_hash = (); my @insns_flag_values = (); +my $iflag_words; + +sub get_flag_words() { + my $max = -1; + + foreach my $key (keys(%insns_flag_bit)) { + if (${$insns_flag_bit{$key}}[0] > $max) { + $max = ${$insns_flag_bit{$key}}[0]; + } + } + + return int($max/32)+1; +} sub insns_flag_index(@) { return undef if $_[0] eq "ignore"; @@ -143,34 +156,16 @@ sub insns_flag_index(@) { my $key = join("", @prekey); if (not defined($insns_flag_hash{$key})) { - my @newkey = ([], [], [], []); - my $str = ""; + my @newkey = (0) x $iflag_words; for my $i (@prekey) { die "No key for $i\n" if not defined($insns_flag_bit{$i}); - if ($insns_flag_bit{$i}[0] < 32) { - push @newkey[0], $insns_flag_bit{$i}[0] - 0; - } elsif ($insns_flag_bit{$i}[0] < 64) { - push @newkey[1], $insns_flag_bit{$i}[0] - 32; - } elsif ($insns_flag_bit{$i}[0] < 96) { - push @newkey[2], $insns_flag_bit{$i}[0] - 64; - } elsif ($insns_flag_bit{$i}[0] < 128) { - push @newkey[3], $insns_flag_bit{$i}[0] - 96; - } else { - die "Key value is too big ", $insns_flag_bit{$i}[0], "\n"; - } - } - - for my $j (0 .. $#newkey) { - my $v = ""; - if (scalar(@{$newkey[$j]})) { - $v = join(" | ", map { map { sprintf("(UINT32_C(1) << %d)", $_) } @$_; } $newkey[$j]); - } else { - $v = "0"; - } - $str .= sprintf(".field[%d] = %s, ", $j, $v); + $newkey[$insns_flag_bit{$i}[0]/32] |= + (1 << ($insns_flag_bit{$i}[0] % 32)); } + my $str = join(',', map { sprintf("UINT32_C(0x%08x)",$_) } @newkey); + push @insns_flag_values, $str; $insns_flag_hash{$key} = $#insns_flag_values; } @@ -193,8 +188,12 @@ sub write_iflaggen_h() { } print N "\n"; - print N sprintf("extern iflag_t insns_flags[%d];\n\n", - $#insns_flag_values + 1); + print N "typedef struct {\n"; + printf N " uint32_t field[%d];\n", $iflag_words; + print N "} iflag_t;\n"; + + print N "\n"; + printf N "extern iflag_t insns_flags[%d];\n\n", $#insns_flag_values + 1; print N "#endif /* NASM_IFLAGGEN_H */\n"; close N; @@ -210,10 +209,12 @@ sub write_iflag_c() { print N "/* Global flags referenced from instruction templates */\n"; print N sprintf("iflag_t insns_flags[%d] = {\n", $#insns_flag_values + 1); foreach my $i (0 .. $#insns_flag_values) { - print N sprintf(" [%8d] = { %s },\n", $i, $insns_flag_values[$i]); + print N sprintf(" /* %4d */ {{ %s }},\n", $i, $insns_flag_values[$i]); } print N "};\n\n"; close N; } +$iflag_words = get_flag_words(); + 1; |
|
From: nasm-bot f. H. P. A. <hp...@zy...> - 2013-11-24 19:54:25
|
Commit-ID: 9a1db4589596fd9f7421ef44dbd0f73490373f41 Gitweb: http://repo.or.cz/w/nasm.git?a=commitdiff;h=9a1db4589596fd9f7421ef44dbd0f73490373f41 Author: H. Peter Anvin <hp...@zy...> AuthorDate: Sun, 24 Nov 2013 11:52:32 -0800 Committer: H. Peter Anvin <hp...@zy...> CommitDate: Sun, 24 Nov 2013 11:53:38 -0800 iflag: Move instruction flag comment Move the instruction flag comment to the Perl file where they are defined. Signed-off-by: H. Peter Anvin <hp...@zy...> --- iflag.h | 28 ---------------------------- insns-iflags.pl | 34 ++++++++++++++++++++++++++++------ insns.dat | 2 +- 3 files changed, 29 insertions(+), 35 deletions(-) diff --git a/iflag.h b/iflag.h index 72929ee..066149a 100644 --- a/iflag.h +++ b/iflag.h @@ -9,34 +9,6 @@ int ilog2_32(uint32_t v); -/* - * Instruction template flags. These specify which processor - * targets the instruction is eligible for, whether it is - * privileged or undocumented, and also specify extra error - * checking on the matching of the instruction. - * - * IF_SM stands for Size Match: any operand whose size is not - * explicitly specified by the template is `really' intended to be - * the same size as the first size-specified operand. - * Non-specification is tolerated in the input instruction, but - * _wrong_ specification is not. - * - * IF_SM2 invokes Size Match on only the first _two_ operands, for - * three-operand instructions such as SHLD: it implies that the - * first two operands must match in size, but that the third is - * required to be _unspecified_. - * - * IF_SB invokes Size Byte: operands with unspecified size in the - * template are really bytes, and so no non-byte specification in - * the input instruction will be tolerated. IF_SW similarly invokes - * Size Word, and IF_SD invokes Size Doubleword. - * - * (The default state if neither IF_SM nor IF_SM2 is specified is - * that any operand with unspecified size in the template is - * required to have unspecified size in the instruction too...) - * - * iflag_t is defined to store these flags. - */ #include "iflaggen.h" #define IF_GENBIT(bit) (UINT32_C(1) << (bit)) diff --git a/insns-iflags.pl b/insns-iflags.pl index 632bba3..b954c73 100644 --- a/insns-iflags.pl +++ b/insns-iflags.pl @@ -33,15 +33,37 @@ ## -------------------------------------------------------------------------- # -# Here we generate instrcution template flags. Note we assume that at moment -# less than 128 bits are used for all flags. If needed it can be extended -# arbitrary, but it'll be needed to extend arrays (they are 4 32 bit elements -# by now). - +# Instruction template flags. These specify which processor +# targets the instruction is eligible for, whether it is +# privileged or undocumented, and also specify extra error +# checking on the matching of the instruction. +# +# IF_SM stands for Size Match: any operand whose size is not +# explicitly specified by the template is `really' intended to be +# the same size as the first size-specified operand. +# Non-specification is tolerated in the input instruction, but +# _wrong_ specification is not. +# +# IF_SM2 invokes Size Match on only the first _two_ operands, for +# three-operand instructions such as SHLD: it implies that the +# first two operands must match in size, but that the third is +# required to be _unspecified_. +# +# IF_SB invokes Size Byte: operands with unspecified size in the +# template are really bytes, and so no non-byte specification in +# the input instruction will be tolerated. IF_SW similarly invokes +# Size Word, and IF_SD invokes Size Doubleword. +# +# (The default state if neither IF_SM nor IF_SM2 is specified is +# that any operand with unspecified size in the template is +# required to have unspecified size in the instruction too...) +# +# iflag_t is defined to store these flags. # # The order does matter here. We use some predefined masks to quick test -# for a set of flags, so be carefull moving bits (and +# for a set of flags, so be careful moving bits (and # don't forget to update C code generation then). +# my %insns_flag_bit = ( # # dword bound, index 0 - specific flags diff --git a/insns.dat b/insns.dat index 9e6c059..1d15997 100644 --- a/insns.dat +++ b/insns.dat @@ -41,7 +41,7 @@ ; ; For a detailed description of the code string (third field), please ; see insns.pl and the comment at the top of assemble.c. For a detailed -; description of the flags (fourth field), please see insns.h. +; description of the flags (fourth field), please see insns-iflag.pl. ; ; Comments with a pound sign after the semicolon generate section ; subheaders in the NASM documentation. |
|
From: nasm-bot f. H. P. A. <hp...@zy...> - 2013-11-24 19:54:25
|
Commit-ID: cd4c89bbb9a59c76671f2fe8bdbe0de34e38ef1d Gitweb: http://repo.or.cz/w/nasm.git?a=commitdiff;h=cd4c89bbb9a59c76671f2fe8bdbe0de34e38ef1d Author: H. Peter Anvin <hp...@zy...> AuthorDate: Sun, 24 Nov 2013 11:18:50 -0800 Committer: H. Peter Anvin <hp...@zy...> CommitDate: Sun, 24 Nov 2013 11:18:50 -0800 "make alldeps" Signed-off-by: H. Peter Anvin <hp...@zy...> --- Makefile.in | 56 ++++++++++++++++++++++++++-------------------------- Mkfiles/msvc.mak | 56 ++++++++++++++++++++++++++++------------------------ Mkfiles/netware.mak | 54 +++++++++++++++++++++++++++----------------------- Mkfiles/openwcom.mak | 56 ++++++++++++++++++++++++++-------------------------- Mkfiles/owlinux.mak | 56 ++++++++++++++++++++++++++++------------------------ 5 files changed, 145 insertions(+), 133 deletions(-) diff --git a/Makefile.in b/Makefile.in index 310c79a..8c102ce 100644 --- a/Makefile.in +++ b/Makefile.in @@ -302,14 +302,14 @@ alldeps: perlreq # @path-separator: "/" #-- Everything below is generated by mkdep.pl - do not edit --# assemble.$(O): assemble.c assemble.h compiler.h config.h directiv.h disp8.h \ - iflag.h insns.h insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h \ - regs.h tables.h tokens.h + iflag.h iflaggen.h insns.h insnsi.h nasm.h nasmlib.h opflags.h pptok.h \ + preproc.h regs.h tables.h tokens.h crc64.$(O): crc64.c compiler.h config.h nasmlib.h directiv.$(O): directiv.c compiler.h config.h directiv.h hashtbl.h insnsi.h \ nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h disasm.$(O): disasm.c compiler.h config.h directiv.h disasm.h disp8.h \ - iflag.h insns.h insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h \ - regdis.h regs.h sync.h tables.h tokens.h + iflag.h iflaggen.h insns.h insnsi.h nasm.h nasmlib.h opflags.h pptok.h \ + preproc.h regdis.h regs.h sync.h tables.h tokens.h disp8.$(O): disp8.c compiler.h config.h directiv.h disp8.h insnsi.h nasm.h \ nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h eval.$(O): eval.c compiler.h config.h directiv.h eval.h float.h insnsi.h \ @@ -320,17 +320,17 @@ float.$(O): float.c compiler.h config.h directiv.h float.h insnsi.h nasm.h \ nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h hashtbl.$(O): hashtbl.c compiler.h config.h directiv.h hashtbl.h insnsi.h \ nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h -iflag.$(O): iflag.c compiler.h config.h iflag.h +iflag.$(O): iflag.c compiler.h config.h iflag.h iflaggen.h ilog2.$(O): ilog2.c compiler.h config.h nasmlib.h -insnsa.$(O): insnsa.c compiler.h config.h directiv.h iflag.h insns.h \ - insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h \ - tokens.h -insnsb.$(O): insnsb.c compiler.h config.h directiv.h iflag.h insns.h \ - insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h \ - tokens.h -insnsd.$(O): insnsd.c compiler.h config.h directiv.h iflag.h insns.h \ - insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h \ - tokens.h +insnsa.$(O): insnsa.c compiler.h config.h directiv.h iflag.h iflaggen.h \ + insns.h insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h \ + tables.h tokens.h +insnsb.$(O): insnsb.c compiler.h config.h directiv.h iflag.h iflaggen.h \ + insns.h insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h \ + tables.h tokens.h +insnsd.$(O): insnsd.c compiler.h config.h directiv.h iflag.h iflaggen.h \ + insns.h insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h \ + tables.h tokens.h insnsn.$(O): insnsn.c compiler.h config.h insnsi.h tables.h labels.$(O): labels.c compiler.h config.h directiv.h hashtbl.h insnsi.h \ nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h @@ -343,15 +343,15 @@ macros.$(O): macros.c compiler.h config.h directiv.h hashtbl.h insnsi.h \ nasm.h nasmlib.h opflags.h output/outform.h pptok.h preproc.h regs.h \ tables.h nasm.$(O): nasm.c assemble.h compiler.h config.h directiv.h eval.h float.h \ - iflag.h insns.h insnsi.h labels.h listing.h nasm.h nasmlib.h opflags.h \ - output/outform.h parser.h pptok.h preproc.h raa.h regs.h saa.h stdscan.h \ + iflag.h iflaggen.h insns.h insnsi.h labels.h listing.h nasm.h nasmlib.h \ + opflags.h output/outform.h parser.h pptok.h preproc.h raa.h regs.h saa.h \ + stdscan.h tables.h tokens.h +nasmlib.$(O): nasmlib.c compiler.h config.h directiv.h iflag.h iflaggen.h \ + insns.h insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h \ tables.h tokens.h -nasmlib.$(O): nasmlib.c compiler.h config.h directiv.h iflag.h insns.h \ - insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h \ - tokens.h ndisasm.$(O): ndisasm.c compiler.h config.h directiv.h disasm.h iflag.h \ - insns.h insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h sync.h \ - tables.h tokens.h + iflaggen.h insns.h insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h \ + regs.h sync.h tables.h tokens.h output/nulldbg.$(O): output/nulldbg.c compiler.h config.h directiv.h \ insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h output/nullout.$(O): output/nullout.c compiler.h config.h directiv.h \ @@ -409,8 +409,8 @@ output/outrdf2.$(O): output/outrdf2.c compiler.h config.h directiv.h \ insnsi.h nasm.h nasmlib.h opflags.h output/outform.h output/outlib.h \ pptok.h preproc.h rdoff/rdoff.h regs.h saa.h tables.h parser.$(O): parser.c compiler.h config.h directiv.h eval.h float.h iflag.h \ - insns.h insnsi.h nasm.h nasmlib.h opflags.h parser.h pptok.h preproc.h \ - regs.h stdscan.h tables.h tokens.h + iflaggen.h insns.h insnsi.h nasm.h nasmlib.h opflags.h parser.h pptok.h \ + preproc.h regs.h stdscan.h tables.h tokens.h pptok.$(O): pptok.c compiler.h config.h hashtbl.h nasmlib.h pptok.h \ preproc.h preproc-nop.$(O): preproc-nop.c compiler.h config.h directiv.h insnsi.h \ @@ -427,14 +427,14 @@ regflags.$(O): regflags.c compiler.h config.h directiv.h insnsi.h nasm.h \ regs.$(O): regs.c compiler.h config.h insnsi.h tables.h regvals.$(O): regvals.c compiler.h config.h insnsi.h tables.h saa.$(O): saa.c compiler.h config.h nasmlib.h saa.h -stdscan.$(O): stdscan.c compiler.h config.h directiv.h iflag.h insns.h \ - insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h quote.h regs.h \ - stdscan.h tables.h tokens.h +stdscan.$(O): stdscan.c compiler.h config.h directiv.h iflag.h iflaggen.h \ + insns.h insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h quote.h \ + regs.h stdscan.h tables.h tokens.h strfunc.$(O): strfunc.c compiler.h config.h directiv.h insnsi.h nasm.h \ nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h sync.$(O): sync.c compiler.h config.h nasmlib.h sync.h tokhash.$(O): tokhash.c compiler.h config.h directiv.h hashtbl.h iflag.h \ - insns.h insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h \ - tables.h tokens.h + iflaggen.h insns.h insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h \ + regs.h tables.h tokens.h ver.$(O): ver.c compiler.h config.h directiv.h insnsi.h nasm.h nasmlib.h \ opflags.h pptok.h preproc.h regs.h tables.h version.h diff --git a/Mkfiles/msvc.mak b/Mkfiles/msvc.mak index b213235..8154818 100644 --- a/Mkfiles/msvc.mak +++ b/Mkfiles/msvc.mak @@ -211,14 +211,14 @@ everything: all doc rdf # @exclude: "config.h" #-- Everything below is generated by mkdep.pl - do not edit --# assemble.$(O): assemble.c assemble.h compiler.h directiv.h disp8.h iflag.h \ - insns.h insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h \ - tables.h tokens.h + iflaggen.h insns.h insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h \ + regs.h tables.h tokens.h crc64.$(O): crc64.c compiler.h nasmlib.h directiv.$(O): directiv.c compiler.h directiv.h hashtbl.h insnsi.h nasm.h \ nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h -disasm.$(O): disasm.c compiler.h directiv.h disasm.h disp8.h iflag.h insns.h \ - insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h regdis.h regs.h \ - sync.h tables.h tokens.h +disasm.$(O): disasm.c compiler.h directiv.h disasm.h disp8.h iflag.h \ + iflaggen.h insns.h insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h \ + regdis.h regs.h sync.h tables.h tokens.h disp8.$(O): disp8.c compiler.h directiv.h disp8.h insnsi.h nasm.h nasmlib.h \ opflags.h pptok.h preproc.h regs.h tables.h eval.$(O): eval.c compiler.h directiv.h eval.h float.h insnsi.h labels.h \ @@ -229,14 +229,17 @@ float.$(O): float.c compiler.h directiv.h float.h insnsi.h nasm.h nasmlib.h \ opflags.h pptok.h preproc.h regs.h tables.h hashtbl.$(O): hashtbl.c compiler.h directiv.h hashtbl.h insnsi.h nasm.h \ nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h -iflag.$(O): iflag.c compiler.h iflag.h +iflag.$(O): iflag.c compiler.h iflag.h iflaggen.h ilog2.$(O): ilog2.c compiler.h nasmlib.h -insnsa.$(O): insnsa.c compiler.h directiv.h iflag.h insns.h insnsi.h nasm.h \ - nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h tokens.h -insnsb.$(O): insnsb.c compiler.h directiv.h iflag.h insns.h insnsi.h nasm.h \ - nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h tokens.h -insnsd.$(O): insnsd.c compiler.h directiv.h iflag.h insns.h insnsi.h nasm.h \ - nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h tokens.h +insnsa.$(O): insnsa.c compiler.h directiv.h iflag.h iflaggen.h insns.h \ + insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h \ + tokens.h +insnsb.$(O): insnsb.c compiler.h directiv.h iflag.h iflaggen.h insns.h \ + insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h \ + tokens.h +insnsd.$(O): insnsd.c compiler.h directiv.h iflag.h iflaggen.h insns.h \ + insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h \ + tokens.h insnsn.$(O): insnsn.c compiler.h insnsi.h tables.h labels.$(O): labels.c compiler.h directiv.h hashtbl.h insnsi.h nasm.h \ nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h @@ -248,13 +251,14 @@ listing.$(O): listing.c compiler.h directiv.h insnsi.h listing.h nasm.h \ macros.$(O): macros.c compiler.h directiv.h hashtbl.h insnsi.h nasm.h \ nasmlib.h opflags.h output/outform.h pptok.h preproc.h regs.h tables.h nasm.$(O): nasm.c assemble.h compiler.h directiv.h eval.h float.h iflag.h \ - insns.h insnsi.h labels.h listing.h nasm.h nasmlib.h opflags.h \ + iflaggen.h insns.h insnsi.h labels.h listing.h nasm.h nasmlib.h opflags.h \ output/outform.h parser.h pptok.h preproc.h raa.h regs.h saa.h stdscan.h \ tables.h tokens.h -nasmlib.$(O): nasmlib.c compiler.h directiv.h iflag.h insns.h insnsi.h \ - nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h tokens.h -ndisasm.$(O): ndisasm.c compiler.h directiv.h disasm.h iflag.h insns.h \ - insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h sync.h \ +nasmlib.$(O): nasmlib.c compiler.h directiv.h iflag.h iflaggen.h insns.h \ + insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h \ + tokens.h +ndisasm.$(O): ndisasm.c compiler.h directiv.h disasm.h iflag.h iflaggen.h \ + insns.h insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h sync.h \ tables.h tokens.h output/nulldbg.$(O): output/nulldbg.c compiler.h directiv.h insnsi.h nasm.h \ nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h @@ -308,9 +312,9 @@ output/outobj.$(O): output/outobj.c compiler.h directiv.h eval.h insnsi.h \ output/outrdf2.$(O): output/outrdf2.c compiler.h directiv.h insnsi.h nasm.h \ nasmlib.h opflags.h output/outform.h output/outlib.h pptok.h preproc.h \ rdoff/rdoff.h regs.h saa.h tables.h -parser.$(O): parser.c compiler.h directiv.h eval.h float.h iflag.h insns.h \ - insnsi.h nasm.h nasmlib.h opflags.h parser.h pptok.h preproc.h regs.h \ - stdscan.h tables.h tokens.h +parser.$(O): parser.c compiler.h directiv.h eval.h float.h iflag.h \ + iflaggen.h insns.h insnsi.h nasm.h nasmlib.h opflags.h parser.h pptok.h \ + preproc.h regs.h stdscan.h tables.h tokens.h pptok.$(O): pptok.c compiler.h hashtbl.h nasmlib.h pptok.h preproc.h preproc-nop.$(O): preproc-nop.c compiler.h directiv.h insnsi.h nasm.h \ nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h @@ -326,14 +330,14 @@ regflags.$(O): regflags.c compiler.h directiv.h insnsi.h nasm.h nasmlib.h \ regs.$(O): regs.c compiler.h insnsi.h tables.h regvals.$(O): regvals.c compiler.h insnsi.h tables.h saa.$(O): saa.c compiler.h nasmlib.h saa.h -stdscan.$(O): stdscan.c compiler.h directiv.h iflag.h insns.h insnsi.h \ - nasm.h nasmlib.h opflags.h pptok.h preproc.h quote.h regs.h stdscan.h \ - tables.h tokens.h +stdscan.$(O): stdscan.c compiler.h directiv.h iflag.h iflaggen.h insns.h \ + insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h quote.h regs.h \ + stdscan.h tables.h tokens.h strfunc.$(O): strfunc.c compiler.h directiv.h insnsi.h nasm.h nasmlib.h \ opflags.h pptok.h preproc.h regs.h tables.h sync.$(O): sync.c compiler.h nasmlib.h sync.h -tokhash.$(O): tokhash.c compiler.h directiv.h hashtbl.h iflag.h insns.h \ - insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h \ - tokens.h +tokhash.$(O): tokhash.c compiler.h directiv.h hashtbl.h iflag.h iflaggen.h \ + insns.h insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h \ + tables.h tokens.h ver.$(O): ver.c compiler.h directiv.h insnsi.h nasm.h nasmlib.h opflags.h \ pptok.h preproc.h regs.h tables.h version.h diff --git a/Mkfiles/netware.mak b/Mkfiles/netware.mak index fc0aadd..256dab4 100644 --- a/Mkfiles/netware.mak +++ b/Mkfiles/netware.mak @@ -132,14 +132,14 @@ $(OBJDIR)/version.mak: $(PROOT)/version $(PROOT)/version.pl $(OBJDIR) # @continuation: "\" #-- Everything below is generated by mkdep.pl - do not edit --# assemble.o: assemble.c assemble.h compiler.h config.h directiv.h disp8.h \ - iflag.h insns.h insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h \ - regs.h tables.h tokens.h + iflag.h iflaggen.h insns.h insnsi.h nasm.h nasmlib.h opflags.h pptok.h \ + preproc.h regs.h tables.h tokens.h crc64.o: crc64.c compiler.h config.h nasmlib.h directiv.o: directiv.c compiler.h config.h directiv.h hashtbl.h insnsi.h \ nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h disasm.o: disasm.c compiler.h config.h directiv.h disasm.h disp8.h iflag.h \ - insns.h insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h regdis.h \ - regs.h sync.h tables.h tokens.h + iflaggen.h insns.h insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h \ + regdis.h regs.h sync.h tables.h tokens.h disp8.o: disp8.c compiler.h config.h directiv.h disp8.h insnsi.h nasm.h \ nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h eval.o: eval.c compiler.h config.h directiv.h eval.h float.h insnsi.h \ @@ -150,14 +150,17 @@ float.o: float.c compiler.h config.h directiv.h float.h insnsi.h nasm.h \ nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h hashtbl.o: hashtbl.c compiler.h config.h directiv.h hashtbl.h insnsi.h \ nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h -iflag.o: iflag.c compiler.h config.h iflag.h +iflag.o: iflag.c compiler.h config.h iflag.h iflaggen.h ilog2.o: ilog2.c compiler.h config.h nasmlib.h -insnsa.o: insnsa.c compiler.h config.h directiv.h iflag.h insns.h insnsi.h \ - nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h tokens.h -insnsb.o: insnsb.c compiler.h config.h directiv.h iflag.h insns.h insnsi.h \ - nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h tokens.h -insnsd.o: insnsd.c compiler.h config.h directiv.h iflag.h insns.h insnsi.h \ - nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h tokens.h +insnsa.o: insnsa.c compiler.h config.h directiv.h iflag.h iflaggen.h insns.h \ + insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h \ + tokens.h +insnsb.o: insnsb.c compiler.h config.h directiv.h iflag.h iflaggen.h insns.h \ + insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h \ + tokens.h +insnsd.o: insnsd.c compiler.h config.h directiv.h iflag.h iflaggen.h insns.h \ + insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h \ + tokens.h insnsn.o: insnsn.c compiler.h config.h insnsi.h tables.h labels.o: labels.c compiler.h config.h directiv.h hashtbl.h insnsi.h nasm.h \ nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h @@ -169,14 +172,15 @@ listing.o: listing.c compiler.h config.h directiv.h insnsi.h listing.h \ macros.o: macros.c compiler.h config.h directiv.h hashtbl.h insnsi.h nasm.h \ nasmlib.h opflags.h outform.h pptok.h preproc.h regs.h tables.h nasm.o: nasm.c assemble.h compiler.h config.h directiv.h eval.h float.h \ - iflag.h insns.h insnsi.h labels.h listing.h nasm.h nasmlib.h opflags.h \ - outform.h parser.h pptok.h preproc.h raa.h regs.h saa.h stdscan.h tables.h \ - tokens.h -nasmlib.o: nasmlib.c compiler.h config.h directiv.h iflag.h insns.h insnsi.h \ - nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h tokens.h -ndisasm.o: ndisasm.c compiler.h config.h directiv.h disasm.h iflag.h insns.h \ - insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h sync.h \ + iflag.h iflaggen.h insns.h insnsi.h labels.h listing.h nasm.h nasmlib.h \ + opflags.h outform.h parser.h pptok.h preproc.h raa.h regs.h saa.h stdscan.h \ + tables.h tokens.h +nasmlib.o: nasmlib.c compiler.h config.h directiv.h iflag.h iflaggen.h \ + insns.h insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h \ tables.h tokens.h +ndisasm.o: ndisasm.c compiler.h config.h directiv.h disasm.h iflag.h \ + iflaggen.h insns.h insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h \ + regs.h sync.h tables.h tokens.h nulldbg.o: nulldbg.c compiler.h config.h directiv.h insnsi.h nasm.h \ nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h nullout.o: nullout.c compiler.h config.h directiv.h insnsi.h nasm.h \ @@ -226,8 +230,8 @@ outrdf2.o: outrdf2.c compiler.h config.h directiv.h insnsi.h nasm.h \ nasmlib.h opflags.h outform.h outlib.h pptok.h preproc.h rdoff.h regs.h \ saa.h tables.h parser.o: parser.c compiler.h config.h directiv.h eval.h float.h iflag.h \ - insns.h insnsi.h nasm.h nasmlib.h opflags.h parser.h pptok.h preproc.h \ - regs.h stdscan.h tables.h tokens.h + iflaggen.h insns.h insnsi.h nasm.h nasmlib.h opflags.h parser.h pptok.h \ + preproc.h regs.h stdscan.h tables.h tokens.h pptok.o: pptok.c compiler.h config.h hashtbl.h nasmlib.h pptok.h preproc.h preproc-nop.o: preproc-nop.c compiler.h config.h directiv.h insnsi.h nasm.h \ nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h @@ -243,14 +247,14 @@ regflags.o: regflags.c compiler.h config.h directiv.h insnsi.h nasm.h \ regs.o: regs.c compiler.h config.h insnsi.h tables.h regvals.o: regvals.c compiler.h config.h insnsi.h tables.h saa.o: saa.c compiler.h config.h nasmlib.h saa.h -stdscan.o: stdscan.c compiler.h config.h directiv.h iflag.h insns.h insnsi.h \ - nasm.h nasmlib.h opflags.h pptok.h preproc.h quote.h regs.h stdscan.h \ - tables.h tokens.h +stdscan.o: stdscan.c compiler.h config.h directiv.h iflag.h iflaggen.h \ + insns.h insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h quote.h \ + regs.h stdscan.h tables.h tokens.h strfunc.o: strfunc.c compiler.h config.h directiv.h insnsi.h nasm.h \ nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h sync.o: sync.c compiler.h config.h nasmlib.h sync.h tokhash.o: tokhash.c compiler.h config.h directiv.h hashtbl.h iflag.h \ - insns.h insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h \ - tables.h tokens.h + iflaggen.h insns.h insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h \ + regs.h tables.h tokens.h ver.o: ver.c compiler.h config.h directiv.h insnsi.h nasm.h nasmlib.h \ opflags.h pptok.h preproc.h regs.h tables.h version.h diff --git a/Mkfiles/openwcom.mak b/Mkfiles/openwcom.mak index f67e3a8..7732be0 100644 --- a/Mkfiles/openwcom.mak +++ b/Mkfiles/openwcom.mak @@ -269,14 +269,14 @@ alldeps: perlreq .SYMBOLIC # @continuation: "&" #-- Everything below is generated by mkdep.pl - do not edit --# assemble.$(O): assemble.c assemble.h compiler.h config.h directiv.h disp8.h & - iflag.h insns.h insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h & - regs.h tables.h tokens.h + iflag.h iflaggen.h insns.h insnsi.h nasm.h nasmlib.h opflags.h pptok.h & + preproc.h regs.h tables.h tokens.h crc64.$(O): crc64.c compiler.h config.h nasmlib.h directiv.$(O): directiv.c compiler.h config.h directiv.h hashtbl.h insnsi.h & nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h disasm.$(O): disasm.c compiler.h config.h directiv.h disasm.h disp8.h & - iflag.h insns.h insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h & - regdis.h regs.h sync.h tables.h tokens.h + iflag.h iflaggen.h insns.h insnsi.h nasm.h nasmlib.h opflags.h pptok.h & + preproc.h regdis.h regs.h sync.h tables.h tokens.h disp8.$(O): disp8.c compiler.h config.h directiv.h disp8.h insnsi.h nasm.h & nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h eval.$(O): eval.c compiler.h config.h directiv.h eval.h float.h insnsi.h & @@ -287,17 +287,17 @@ float.$(O): float.c compiler.h config.h directiv.h float.h insnsi.h nasm.h & nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h hashtbl.$(O): hashtbl.c compiler.h config.h directiv.h hashtbl.h insnsi.h & nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h -iflag.$(O): iflag.c compiler.h config.h iflag.h +iflag.$(O): iflag.c compiler.h config.h iflag.h iflaggen.h ilog2.$(O): ilog2.c compiler.h config.h nasmlib.h -insnsa.$(O): insnsa.c compiler.h config.h directiv.h iflag.h insns.h & - insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h & - tokens.h -insnsb.$(O): insnsb.c compiler.h config.h directiv.h iflag.h insns.h & - insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h & - tokens.h -insnsd.$(O): insnsd.c compiler.h config.h directiv.h iflag.h insns.h & - insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h & - tokens.h +insnsa.$(O): insnsa.c compiler.h config.h directiv.h iflag.h iflaggen.h & + insns.h insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h & + tables.h tokens.h +insnsb.$(O): insnsb.c compiler.h config.h directiv.h iflag.h iflaggen.h & + insns.h insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h & + tables.h tokens.h +insnsd.$(O): insnsd.c compiler.h config.h directiv.h iflag.h iflaggen.h & + insns.h insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h & + tables.h tokens.h insnsn.$(O): insnsn.c compiler.h config.h insnsi.h tables.h labels.$(O): labels.c compiler.h config.h directiv.h hashtbl.h insnsi.h & nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h @@ -310,15 +310,15 @@ macros.$(O): macros.c compiler.h config.h directiv.h hashtbl.h insnsi.h & nasm.h nasmlib.h opflags.h output/outform.h pptok.h preproc.h regs.h & tables.h nasm.$(O): nasm.c assemble.h compiler.h config.h directiv.h eval.h float.h & - iflag.h insns.h insnsi.h labels.h listing.h nasm.h nasmlib.h opflags.h & - output/outform.h parser.h pptok.h preproc.h raa.h regs.h saa.h stdscan.h & + iflag.h iflaggen.h insns.h insnsi.h labels.h listing.h nasm.h nasmlib.h & + opflags.h output/outform.h parser.h pptok.h preproc.h raa.h regs.h saa.h & + stdscan.h tables.h tokens.h +nasmlib.$(O): nasmlib.c compiler.h config.h directiv.h iflag.h iflaggen.h & + insns.h insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h & tables.h tokens.h -nasmlib.$(O): nasmlib.c compiler.h config.h directiv.h iflag.h insns.h & - insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h & - tokens.h ndisasm.$(O): ndisasm.c compiler.h config.h directiv.h disasm.h iflag.h & - insns.h insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h sync.h & - tables.h tokens.h + iflaggen.h insns.h insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h & + regs.h sync.h tables.h tokens.h output/nulldbg.$(O): output/nulldbg.c compiler.h config.h directiv.h & insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h output/nullout.$(O): output/nullout.c compiler.h config.h directiv.h & @@ -376,8 +376,8 @@ output/outrdf2.$(O): output/outrdf2.c compiler.h config.h directiv.h & insnsi.h nasm.h nasmlib.h opflags.h output/outform.h output/outlib.h & pptok.h preproc.h rdoff/rdoff.h regs.h saa.h tables.h parser.$(O): parser.c compiler.h config.h directiv.h eval.h float.h iflag.h & - insns.h insnsi.h nasm.h nasmlib.h opflags.h parser.h pptok.h preproc.h & - regs.h stdscan.h tables.h tokens.h + iflaggen.h insns.h insnsi.h nasm.h nasmlib.h opflags.h parser.h pptok.h & + preproc.h regs.h stdscan.h tables.h tokens.h pptok.$(O): pptok.c compiler.h config.h hashtbl.h nasmlib.h pptok.h & preproc.h preproc-nop.$(O): preproc-nop.c compiler.h config.h directiv.h insnsi.h & @@ -394,14 +394,14 @@ regflags.$(O): regflags.c compiler.h config.h directiv.h insnsi.h nasm.h & regs.$(O): regs.c compiler.h config.h insnsi.h tables.h regvals.$(O): regvals.c compiler.h config.h insnsi.h tables.h saa.$(O): saa.c compiler.h config.h nasmlib.h saa.h -stdscan.$(O): stdscan.c compiler.h config.h directiv.h iflag.h insns.h & - insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h quote.h regs.h & - stdscan.h tables.h tokens.h +stdscan.$(O): stdscan.c compiler.h config.h directiv.h iflag.h iflaggen.h & + insns.h insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h quote.h & + regs.h stdscan.h tables.h tokens.h strfunc.$(O): strfunc.c compiler.h config.h directiv.h insnsi.h nasm.h & nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h sync.$(O): sync.c compiler.h config.h nasmlib.h sync.h tokhash.$(O): tokhash.c compiler.h config.h directiv.h hashtbl.h iflag.h & - insns.h insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h & - tables.h tokens.h + iflaggen.h insns.h insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h & + regs.h tables.h tokens.h ver.$(O): ver.c compiler.h config.h directiv.h insnsi.h nasm.h nasmlib.h & opflags.h pptok.h preproc.h regs.h tables.h version.h diff --git a/Mkfiles/owlinux.mak b/Mkfiles/owlinux.mak index c1a892c..a9137c3 100644 --- a/Mkfiles/owlinux.mak +++ b/Mkfiles/owlinux.mak @@ -238,14 +238,14 @@ everything: all doc rdf # @continuation: "\" #-- Everything below is generated by mkdep.pl - do not edit --# assemble.$(O): assemble.c assemble.h compiler.h directiv.h disp8.h iflag.h \ - insns.h insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h \ - tables.h tokens.h + iflaggen.h insns.h insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h \ + regs.h tables.h tokens.h crc64.$(O): crc64.c compiler.h nasmlib.h directiv.$(O): directiv.c compiler.h directiv.h hashtbl.h insnsi.h nasm.h \ nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h -disasm.$(O): disasm.c compiler.h directiv.h disasm.h disp8.h iflag.h insns.h \ - insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h regdis.h regs.h \ - sync.h tables.h tokens.h +disasm.$(O): disasm.c compiler.h directiv.h disasm.h disp8.h iflag.h \ + iflaggen.h insns.h insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h \ + regdis.h regs.h sync.h tables.h tokens.h disp8.$(O): disp8.c compiler.h directiv.h disp8.h insnsi.h nasm.h nasmlib.h \ opflags.h pptok.h preproc.h regs.h tables.h eval.$(O): eval.c compiler.h directiv.h eval.h float.h insnsi.h labels.h \ @@ -256,14 +256,17 @@ float.$(O): float.c compiler.h directiv.h float.h insnsi.h nasm.h nasmlib.h \ opflags.h pptok.h preproc.h regs.h tables.h hashtbl.$(O): hashtbl.c compiler.h directiv.h hashtbl.h insnsi.h nasm.h \ nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h -iflag.$(O): iflag.c compiler.h iflag.h +iflag.$(O): iflag.c compiler.h iflag.h iflaggen.h ilog2.$(O): ilog2.c compiler.h nasmlib.h -insnsa.$(O): insnsa.c compiler.h directiv.h iflag.h insns.h insnsi.h nasm.h \ - nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h tokens.h -insnsb.$(O): insnsb.c compiler.h directiv.h iflag.h insns.h insnsi.h nasm.h \ - nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h tokens.h -insnsd.$(O): insnsd.c compiler.h directiv.h iflag.h insns.h insnsi.h nasm.h \ - nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h tokens.h +insnsa.$(O): insnsa.c compiler.h directiv.h iflag.h iflaggen.h insns.h \ + insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h \ + tokens.h +insnsb.$(O): insnsb.c compiler.h directiv.h iflag.h iflaggen.h insns.h \ + insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h \ + tokens.h +insnsd.$(O): insnsd.c compiler.h directiv.h iflag.h iflaggen.h insns.h \ + insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h \ + tokens.h insnsn.$(O): insnsn.c compiler.h insnsi.h tables.h labels.$(O): labels.c compiler.h directiv.h hashtbl.h insnsi.h nasm.h \ nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h @@ -275,13 +278,14 @@ listing.$(O): listing.c compiler.h directiv.h insnsi.h listing.h nasm.h \ macros.$(O): macros.c compiler.h directiv.h hashtbl.h insnsi.h nasm.h \ nasmlib.h opflags.h output/outform.h pptok.h preproc.h regs.h tables.h nasm.$(O): nasm.c assemble.h compiler.h directiv.h eval.h float.h iflag.h \ - insns.h insnsi.h labels.h listing.h nasm.h nasmlib.h opflags.h \ + iflaggen.h insns.h insnsi.h labels.h listing.h nasm.h nasmlib.h opflags.h \ output/outform.h parser.h pptok.h preproc.h raa.h regs.h saa.h stdscan.h \ tables.h tokens.h -nasmlib.$(O): nasmlib.c compiler.h directiv.h iflag.h insns.h insnsi.h \ - nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h tokens.h -ndisasm.$(O): ndisasm.c compiler.h directiv.h disasm.h iflag.h insns.h \ - insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h sync.h \ +nasmlib.$(O): nasmlib.c compiler.h directiv.h iflag.h iflaggen.h insns.h \ + insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h \ + tokens.h +ndisasm.$(O): ndisasm.c compiler.h directiv.h disasm.h iflag.h iflaggen.h \ + insns.h insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h sync.h \ tables.h tokens.h output/nulldbg.$(O): output/nulldbg.c compiler.h directiv.h insnsi.h nasm.h \ nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h @@ -335,9 +339,9 @@ output/outobj.$(O): output/outobj.c compiler.h directiv.h eval.h insnsi.h \ output/outrdf2.$(O): output/outrdf2.c compiler.h directiv.h insnsi.h nasm.h \ nasmlib.h opflags.h output/outform.h output/outlib.h pptok.h preproc.h \ rdoff/rdoff.h regs.h saa.h tables.h -parser.$(O): parser.c compiler.h directiv.h eval.h float.h iflag.h insns.h \ - insnsi.h nasm.h nasmlib.h opflags.h parser.h pptok.h preproc.h regs.h \ - stdscan.h tables.h tokens.h +parser.$(O): parser.c compiler.h directiv.h eval.h float.h iflag.h \ + iflaggen.h insns.h insnsi.h nasm.h nasmlib.h opflags.h parser.h pptok.h \ + preproc.h regs.h stdscan.h tables.h tokens.h pptok.$(O): pptok.c compiler.h hashtbl.h nasmlib.h pptok.h preproc.h preproc-nop.$(O): preproc-nop.c compiler.h directiv.h insnsi.h nasm.h \ nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h @@ -353,14 +357,14 @@ regflags.$(O): regflags.c compiler.h directiv.h insnsi.h nasm.h nasmlib.h \ regs.$(O): regs.c compiler.h insnsi.h tables.h regvals.$(O): regvals.c compiler.h insnsi.h tables.h saa.$(O): saa.c compiler.h nasmlib.h saa.h -stdscan.$(O): stdscan.c compiler.h directiv.h iflag.h insns.h insnsi.h \ - nasm.h nasmlib.h opflags.h pptok.h preproc.h quote.h regs.h stdscan.h \ - tables.h tokens.h +stdscan.$(O): stdscan.c compiler.h directiv.h iflag.h iflaggen.h insns.h \ + insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h quote.h regs.h \ + stdscan.h tables.h tokens.h strfunc.$(O): strfunc.c compiler.h directiv.h insnsi.h nasm.h nasmlib.h \ opflags.h pptok.h preproc.h regs.h tables.h sync.$(O): sync.c compiler.h nasmlib.h sync.h -tokhash.$(O): tokhash.c compiler.h directiv.h hashtbl.h iflag.h insns.h \ - insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h \ - tokens.h +tokhash.$(O): tokhash.c compiler.h directiv.h hashtbl.h iflag.h iflaggen.h \ + insns.h insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h \ + tables.h tokens.h ver.$(O): ver.c compiler.h directiv.h insnsi.h nasm.h nasmlib.h opflags.h \ pptok.h preproc.h regs.h tables.h version.h |
|
From: nasm-bot f. H. P. A. <hp...@zy...> - 2013-11-24 19:00:41
|
Commit-ID: 015774dc3fee2aa1a96718e5097fb8045ef020a3 Gitweb: http://repo.or.cz/w/nasm.git?a=commitdiff;h=015774dc3fee2aa1a96718e5097fb8045ef020a3 Author: H. Peter Anvin <hp...@zy...> AuthorDate: Sun, 24 Nov 2013 10:56:49 -0800 Committer: H. Peter Anvin <hp...@zy...> CommitDate: Sun, 24 Nov 2013 10:56:49 -0800 "make alldeps" Signed-off-by: H. Peter Anvin <hp...@zy...> --- Makefile.in | 14 ++++++++------ Mkfiles/msvc.mak | 14 +++++++++----- Mkfiles/netware.mak | 18 +++++++++++------- Mkfiles/openwcom.mak | 18 +++++++++++------- Mkfiles/owlinux.mak | 14 +++++++++----- 5 files changed, 48 insertions(+), 30 deletions(-) diff --git a/Makefile.in b/Makefile.in index 98f233e..2f46d3b 100644 --- a/Makefile.in +++ b/Makefile.in @@ -300,15 +300,17 @@ alldeps: perlreq # @object-ending: ".$(O)" # @path-separator: "/" #-- Everything below is generated by mkdep.pl - do not edit --# -assemble.$(O): assemble.c assemble.h compiler.h config.h directiv.h iflag.h \ - insns.h insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h \ - tables.h tokens.h +assemble.$(O): assemble.c assemble.h compiler.h config.h directiv.h disp8.h \ + iflag.h insns.h insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h \ + regs.h tables.h tokens.h crc64.$(O): crc64.c compiler.h config.h nasmlib.h directiv.$(O): directiv.c compiler.h config.h directiv.h hashtbl.h insnsi.h \ nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h -disasm.$(O): disasm.c compiler.h config.h directiv.h disasm.h iflag.h \ - insns.h insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h regdis.h \ - regs.h sync.h tables.h tokens.h +disasm.$(O): disasm.c compiler.h config.h directiv.h disasm.h disp8.h \ + iflag.h insns.h insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h \ + regdis.h regs.h sync.h tables.h tokens.h +disp8.$(O): disp8.c compiler.h config.h directiv.h disp8.h insnsi.h nasm.h \ + nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h eval.$(O): eval.c compiler.h config.h directiv.h eval.h float.h insnsi.h \ labels.h nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h exprlib.$(O): exprlib.c compiler.h config.h directiv.h insnsi.h nasm.h \ diff --git a/Mkfiles/msvc.mak b/Mkfiles/msvc.mak index 9548c9b..b213235 100644 --- a/Mkfiles/msvc.mak +++ b/Mkfiles/msvc.mak @@ -52,10 +52,12 @@ NASM = nasm.$(O) nasmlib.$(O) ver.$(O) \ ilog2.$(O) \ lib/strlcpy.$(O) \ preproc-nop.$(O) \ + disp8.$(O) \ iflag.$(O) NDISASM = ndisasm.$(O) disasm.$(O) sync.$(O) nasmlib.$(O) ver.$(O) \ - insnsd.$(O) insnsb.$(O) insnsn.$(O) regs.$(O) regdis.$(O) iflag.$(O) + insnsd.$(O) insnsb.$(O) insnsn.$(O) regs.$(O) regdis.$(O) \ + disp8.$(O) iflag.$(O) #-- End File Lists --# all: nasm$(X) ndisasm$(X) @@ -208,15 +210,17 @@ everything: all doc rdf # @path-separator: "/" # @exclude: "config.h" #-- Everything below is generated by mkdep.pl - do not edit --# -assemble.$(O): assemble.c assemble.h compiler.h directiv.h iflag.h insns.h \ - insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h \ - tokens.h +assemble.$(O): assemble.c assemble.h compiler.h directiv.h disp8.h iflag.h \ + insns.h insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h \ + tables.h tokens.h crc64.$(O): crc64.c compiler.h nasmlib.h directiv.$(O): directiv.c compiler.h directiv.h hashtbl.h insnsi.h nasm.h \ nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h -disasm.$(O): disasm.c compiler.h directiv.h disasm.h iflag.h insns.h \ +disasm.$(O): disasm.c compiler.h directiv.h disasm.h disp8.h iflag.h insns.h \ insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h regdis.h regs.h \ sync.h tables.h tokens.h +disp8.$(O): disp8.c compiler.h directiv.h disp8.h insnsi.h nasm.h nasmlib.h \ + opflags.h pptok.h preproc.h regs.h tables.h eval.$(O): eval.c compiler.h directiv.h eval.h float.h insnsi.h labels.h \ nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h exprlib.$(O): exprlib.c compiler.h directiv.h insnsi.h nasm.h nasmlib.h \ diff --git a/Mkfiles/netware.mak b/Mkfiles/netware.mak index 1a888c9..fc0aadd 100644 --- a/Mkfiles/netware.mak +++ b/Mkfiles/netware.mak @@ -48,10 +48,12 @@ NASM = nasm.o nasmlib.o ver.o \ ilog2.o \ strlcpy.o \ preproc-nop.o \ + disp8.o \ iflag.o NDISASM = ndisasm.o disasm.o sync.o nasmlib.o ver.o \ - insnsd.o insnsb.o insnsn.o regs.o regdis.o iflag.o + insnsd.o insnsb.o insnsn.o regs.o regdis.o \ + disp8.o iflag.o #-- End File Lists --# NASM_OBJ = $(addprefix $(OBJDIR)/,$(notdir $(NASM))) $(EOLIST) @@ -129,15 +131,17 @@ $(OBJDIR)/version.mak: $(PROOT)/version $(PROOT)/version.pl $(OBJDIR) # @path-separator: "" # @continuation: "\" #-- Everything below is generated by mkdep.pl - do not edit --# -assemble.o: assemble.c assemble.h compiler.h config.h directiv.h iflag.h \ - insns.h insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h \ - tables.h tokens.h +assemble.o: assemble.c assemble.h compiler.h config.h directiv.h disp8.h \ + iflag.h insns.h insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h \ + regs.h tables.h tokens.h crc64.o: crc64.c compiler.h config.h nasmlib.h directiv.o: directiv.c compiler.h config.h directiv.h hashtbl.h insnsi.h \ nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h -disasm.o: disasm.c compiler.h config.h directiv.h disasm.h iflag.h insns.h \ - insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h regdis.h regs.h \ - sync.h tables.h tokens.h +disasm.o: disasm.c compiler.h config.h directiv.h disasm.h disp8.h iflag.h \ + insns.h insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h regdis.h \ + regs.h sync.h tables.h tokens.h +disp8.o: disp8.c compiler.h config.h directiv.h disp8.h insnsi.h nasm.h \ + nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h eval.o: eval.c compiler.h config.h directiv.h eval.h float.h insnsi.h \ labels.h nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h exprlib.o: exprlib.c compiler.h config.h directiv.h insnsi.h nasm.h \ diff --git a/Mkfiles/openwcom.mak b/Mkfiles/openwcom.mak index 9287d61..f67e3a8 100644 --- a/Mkfiles/openwcom.mak +++ b/Mkfiles/openwcom.mak @@ -64,10 +64,12 @@ NASM = nasm.$(O) nasmlib.$(O) ver.$(O) & ilog2.$(O) & lib/strlcpy.$(O) & preproc-nop.$(O) & + disp8.$(O) & iflag.$(O) NDISASM = ndisasm.$(O) disasm.$(O) sync.$(O) nasmlib.$(O) ver.$(O) & - insnsd.$(O) insnsb.$(O) insnsn.$(O) regs.$(O) regdis.$(O) iflag.$(O) + insnsd.$(O) insnsb.$(O) insnsn.$(O) regs.$(O) regdis.$(O) & + disp8.$(O) iflag.$(O) #-- End File Lists --# what: .SYMBOLIC @@ -266,15 +268,17 @@ alldeps: perlreq .SYMBOLIC # @exclude: "" # @continuation: "&" #-- Everything below is generated by mkdep.pl - do not edit --# -assemble.$(O): assemble.c assemble.h compiler.h config.h directiv.h iflag.h & - insns.h insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h & - tables.h tokens.h +assemble.$(O): assemble.c assemble.h compiler.h config.h directiv.h disp8.h & + iflag.h insns.h insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h & + regs.h tables.h tokens.h crc64.$(O): crc64.c compiler.h config.h nasmlib.h directiv.$(O): directiv.c compiler.h config.h directiv.h hashtbl.h insnsi.h & nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h -disasm.$(O): disasm.c compiler.h config.h directiv.h disasm.h iflag.h & - insns.h insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h regdis.h & - regs.h sync.h tables.h tokens.h +disasm.$(O): disasm.c compiler.h config.h directiv.h disasm.h disp8.h & + iflag.h insns.h insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h & + regdis.h regs.h sync.h tables.h tokens.h +disp8.$(O): disp8.c compiler.h config.h directiv.h disp8.h insnsi.h nasm.h & + nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h eval.$(O): eval.c compiler.h config.h directiv.h eval.h float.h insnsi.h & labels.h nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h exprlib.$(O): exprlib.c compiler.h config.h directiv.h insnsi.h nasm.h & diff --git a/Mkfiles/owlinux.mak b/Mkfiles/owlinux.mak index d5c84be..c1a892c 100644 --- a/Mkfiles/owlinux.mak +++ b/Mkfiles/owlinux.mak @@ -75,10 +75,12 @@ NASM = nasm.$(O) nasmlib.$(O) ver.$(O) \ ilog2.$(O) \ lib/strlcpy.$(O) \ preproc-nop.$(O) \ + disp8.$(O) \ iflag.$(O) NDISASM = ndisasm.$(O) disasm.$(O) sync.$(O) nasmlib.$(O) ver.$(O) \ - insnsd.$(O) insnsb.$(O) insnsn.$(O) regs.$(O) regdis.$(O) iflag.$(O) + insnsd.$(O) insnsb.$(O) insnsn.$(O) regs.$(O) regdis.$(O) \ + disp8.$(O) iflag.$(O) #-- End File Lists --# what: @@ -235,15 +237,17 @@ everything: all doc rdf # @exclude: "config.h" # @continuation: "\" #-- Everything below is generated by mkdep.pl - do not edit --# -assemble.$(O): assemble.c assemble.h compiler.h directiv.h iflag.h insns.h \ - insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h \ - tokens.h +assemble.$(O): assemble.c assemble.h compiler.h directiv.h disp8.h iflag.h \ + insns.h insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h \ + tables.h tokens.h crc64.$(O): crc64.c compiler.h nasmlib.h directiv.$(O): directiv.c compiler.h directiv.h hashtbl.h insnsi.h nasm.h \ nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h -disasm.$(O): disasm.c compiler.h directiv.h disasm.h iflag.h insns.h \ +disasm.$(O): disasm.c compiler.h directiv.h disasm.h disp8.h iflag.h insns.h \ insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h regdis.h regs.h \ sync.h tables.h tokens.h +disp8.$(O): disp8.c compiler.h directiv.h disp8.h insnsi.h nasm.h nasmlib.h \ + opflags.h pptok.h preproc.h regs.h tables.h eval.$(O): eval.c compiler.h directiv.h eval.h float.h insnsi.h labels.h \ nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h exprlib.$(O): exprlib.c compiler.h directiv.h insnsi.h nasm.h nasmlib.h \ |
|
From: nasm-bot f. C. G. <gor...@gm...> - 2013-11-24 09:30:40
|
Commit-ID: 0835915c1dba4e96e91dcb62672720d963b7a8c7 Gitweb: http://repo.or.cz/w/nasm.git?a=commitdiff;h=0835915c1dba4e96e91dcb62672720d963b7a8c7 Author: Cyrill Gorcunov <gor...@gm...> AuthorDate: Sat, 9 Nov 2013 22:16:11 +0400 Committer: Cyrill Gorcunov <gor...@gm...> CommitDate: Sun, 24 Nov 2013 13:20:59 +0400 iflag: Start using new instruction flags engine Here we start using instruction flags generator. Signed-off-by: Cyrill Gorcunov <gor...@gm...> --- Makefile.in | 14 ++++-- Mkfiles/msvc.mak | 11 +++-- Mkfiles/netware.mak | 5 ++- Mkfiles/openwcom.mak | 12 ++++-- Mkfiles/owlinux.mak | 11 +++-- assemble.c | 55 ++++++++++++------------ assemble.h | 11 ++--- disasm.c | 28 ++++++------ disasm.h | 4 +- insns.h | 118 +-------------------------------------------------- insns.pl | 25 ++++++++--- nasm.c | 99 ++++++++++++++++++++++++------------------ ndisasm.c | 23 ++++++---- 13 files changed, 182 insertions(+), 234 deletions(-) diff --git a/Makefile.in b/Makefile.in index e4c56b5..c3dbc0f 100644 --- a/Makefile.in +++ b/Makefile.in @@ -89,10 +89,13 @@ NASM = nasm.$(O) nasmlib.$(O) ver.$(O) \ strfunc.$(O) tokhash.$(O) regvals.$(O) regflags.$(O) \ ilog2.$(O) \ lib/strlcpy.$(O) \ - preproc-nop.$(O) disp8.$(O) + preproc-nop.$(O) \ + disp8.$(O) \ + iflag.$(O) NDISASM = ndisasm.$(O) disasm.$(O) sync.$(O) nasmlib.$(O) ver.$(O) \ - insnsd.$(O) insnsb.$(O) insnsn.$(O) regs.$(O) regdis.$(O) disp8.$(O) + insnsd.$(O) insnsb.$(O) insnsn.$(O) regs.$(O) regdis.$(O) \ + disp8.$(O) iflag.$(O) #-- End File Lists --# all: nasm$(X) ndisasm$(X) manpages rdf @@ -108,6 +111,10 @@ ndisasm$(X): $(NDISASM) $(XOBJS) # though, so it isn't necessary to have Perl just to recompile NASM # from the distribution. +insns.pl: insns-iflags.pl + +iflag.c iflag.h: insns.dat insns.pl + $(PERL) $(srcdir)/insns.pl -t $(srcdir)/insns.dat insnsb.c: insns.dat insns.pl $(PERL) $(srcdir)/insns.pl -b $(srcdir)/insns.dat insnsa.c: insns.dat insns.pl @@ -185,7 +192,8 @@ PERLREQ = macros.c insnsb.c insnsa.c insnsd.c insnsi.h insnsn.c \ regs.c regs.h regflags.c regdis.c regdis.h regvals.c \ tokhash.c tokens.h pptok.h pptok.c pptok.ph \ directiv.c directiv.h \ - version.h version.mac version.mak version.nsh + version.h version.mac version.mak version.nsh \ + iflag.c iflag.h perlreq: $(PERLREQ) # Generated manpages, also pregenerated for distribution diff --git a/Mkfiles/msvc.mak b/Mkfiles/msvc.mak index a96bd15..e93219f 100644 --- a/Mkfiles/msvc.mak +++ b/Mkfiles/msvc.mak @@ -51,10 +51,11 @@ NASM = nasm.$(O) nasmlib.$(O) ver.$(O) \ strfunc.$(O) tokhash.$(O) regvals.$(O) regflags.$(O) \ ilog2.$(O) \ lib/strlcpy.$(O) \ - preproc-nop.$(O) + preproc-nop.$(O) \ + iflag.$(O) NDISASM = ndisasm.$(O) disasm.$(O) sync.$(O) nasmlib.$(O) ver.$(O) \ - insnsd.$(O) insnsb.$(O) insnsn.$(O) regs.$(O) regdis.$(O) + insnsd.$(O) insnsb.$(O) insnsn.$(O) regs.$(O) regdis.$(O) iflag.$(O) #-- End File Lists --# all: nasm$(X) ndisasm$(X) @@ -71,6 +72,10 @@ ndisasm$(X): $(NDISASM) # though, so it isn't necessary to have Perl just to recompile NASM # from the distribution. +insns.pl: insns-iflags.pl + +iflag.c iflag.h: insns.dat insns.pl + $(PERL) $(srcdir)/insns.pl -t $(srcdir)/insns.dat insnsb.c: insns.dat insns.pl $(PERL) $(srcdir)/insns.pl -b $(srcdir)/insns.dat insnsa.c: insns.dat insns.pl @@ -142,7 +147,7 @@ directiv.c: directiv.dat directiv.pl perllib/phash.ph # This allows easier generation of distribution (see dist target). PERLREQ = macros.c insnsb.c insnsa.c insnsd.c insnsi.h insnsn.c \ regs.c regs.h regflags.c regdis.c regvals.c tokhash.c tokens.h \ - version.h version.mac pptok.h pptok.c + version.h version.mac pptok.h pptok.c iflag.c iflag.h perlreq: $(PERLREQ) clean: diff --git a/Mkfiles/netware.mak b/Mkfiles/netware.mak index 178dbdc..8615431 100644 --- a/Mkfiles/netware.mak +++ b/Mkfiles/netware.mak @@ -47,10 +47,11 @@ NASM = nasm.o nasmlib.o ver.o \ strfunc.o tokhash.o regvals.o regflags.o \ ilog2.o \ strlcpy.o \ - preproc-nop.o + preproc-nop.o \ + iflag.o NDISASM = ndisasm.o disasm.o sync.o nasmlib.o ver.o \ - insnsd.o insnsb.o insnsn.o regs.o regdis.o + insnsd.o insnsb.o insnsn.o regs.o regdis.o iflag.o #-- End File Lists --# NASM_OBJ = $(addprefix $(OBJDIR)/,$(notdir $(NASM))) $(EOLIST) diff --git a/Mkfiles/openwcom.mak b/Mkfiles/openwcom.mak index 8a0ffef..222163d 100644 --- a/Mkfiles/openwcom.mak +++ b/Mkfiles/openwcom.mak @@ -63,10 +63,11 @@ NASM = nasm.$(O) nasmlib.$(O) ver.$(O) & strfunc.$(O) tokhash.$(O) regvals.$(O) regflags.$(O) & ilog2.$(O) & lib/strlcpy.$(O) & - preproc-nop.$(O) + preproc-nop.$(O) & + iflag.$(O) NDISASM = ndisasm.$(O) disasm.$(O) sync.$(O) nasmlib.$(O) ver.$(O) & - insnsd.$(O) insnsb.$(O) insnsn.$(O) regs.$(O) regdis.$(O) + insnsd.$(O) insnsb.$(O) insnsn.$(O) regs.$(O) regdis.$(O) iflag.$(O) #-- End File Lists --# what: .SYMBOLIC @@ -106,6 +107,10 @@ ndisasm$(X): $(NDISASM) # though, so it isn't necessary to have Perl just to recompile NASM # from the distribution. +insns.pl: insns-iflags.pl + +iflag.c iflag.h: insns.dat insns.pl + $(PERL) $(srcdir)/insns.pl -t $(srcdir)/insns.dat insnsb.c: insns.dat insns.pl $(PERL) $(srcdir)/insns.pl -b $(srcdir)/insns.dat insnsa.c: insns.dat insns.pl @@ -177,7 +182,8 @@ PERLREQ = pptok.ph macros.c insnsb.c insnsa.c insnsd.c insnsi.h insnsn.c & regs.c regs.h regflags.c regdis.c regdis.h regvals.c & tokhash.c tokens.h pptok.h pptok.c & directiv.c directiv.h & - version.h version.mac + version.h version.mac & + iflag.c iflag.h perlreq: $(PERLREQ) .SYMBOLIC clean: .SYMBOLIC diff --git a/Mkfiles/owlinux.mak b/Mkfiles/owlinux.mak index d04c80d..04fb90a 100644 --- a/Mkfiles/owlinux.mak +++ b/Mkfiles/owlinux.mak @@ -74,10 +74,11 @@ NASM = nasm.$(O) nasmlib.$(O) ver.$(O) \ strfunc.$(O) tokhash.$(O) regvals.$(O) regflags.$(O) \ ilog2.$(O) \ lib/strlcpy.$(O) \ - preproc-nop.$(O) + preproc-nop.$(O) \ + iflag.$(O) NDISASM = ndisasm.$(O) disasm.$(O) sync.$(O) nasmlib.$(O) ver.$(O) \ - insnsd.$(O) insnsb.$(O) insnsn.$(O) regs.$(O) regdis.$(O) + insnsd.$(O) insnsb.$(O) insnsn.$(O) regs.$(O) regdis.$(O) iflag.$(O) #-- End File Lists --# what: @@ -105,6 +106,10 @@ ndisasm$(X): $(NDISASM) # though, so it isn't necessary to have Perl just to recompile NASM # from the distribution. +insns.pl: insns-iflags.pl + +iflag.c iflag.h: insns.dat insns.pl + $(PERL) $(srcdir)/insns.pl -t $(srcdir)/insns.dat insnsb.c: insns.dat insns.pl $(PERL) $(srcdir)/insns.pl -b $(srcdir)/insns.dat insnsa.c: insns.dat insns.pl @@ -167,7 +172,7 @@ pptok.c: pptok.dat pptok.pl perllib/phash.ph PERLREQ = macros.c insnsb.c insnsa.c insnsd.c insnsi.h insnsn.c \ regs.c regs.h regflags.c regdis.c regdis.h regvals.c \ tokhash.c tokens.h pptok.h pptok.c \ - version.h version.mac + version.h version.mac iflag.c iflag.h perlreq: $(PERLREQ) clean: diff --git a/assemble.c b/assemble.c index 0667ef7..193c487 100644 --- a/assemble.c +++ b/assemble.c @@ -218,7 +218,7 @@ typedef struct { #define GEN_MODRM(mod, reg, rm) \ (((mod) << 6) | (((reg) & 7) << 3) | ((rm) & 7)) -static iflags_t cpu; /* cpu level received from nasm.c */ +static iflag_t cpu; /* cpu level received from nasm.c */ static efunc errfunc; static struct ofmt *outfmt; static ListGen *list; @@ -390,7 +390,7 @@ static bool jmp_match(int32_t segment, int64_t offset, int bits, return is_byte; } -int64_t assemble(int32_t segment, int64_t offset, int bits, iflags_t cp, +int64_t assemble(int32_t segment, int64_t offset, int bits, iflag_t cp, insn * instruction, struct ofmt *output, efunc error, ListGen * listgen) { @@ -704,7 +704,7 @@ int64_t assemble(int32_t segment, int64_t offset, int bits, iflags_t cp, return 0; } -int64_t insn_size(int32_t segment, int64_t offset, int bits, iflags_t cp, +int64_t insn_size(int32_t segment, int64_t offset, int bits, iflag_t cp, insn * instruction, efunc error) { const struct itemplate *temp; @@ -1231,7 +1231,7 @@ static int64_t calcsize(int32_t segment, int64_t offset, int bits, * only for mib operands, make a single reg index [reg*1]. * gas uses this form to explicitly denote index register. */ - if ((temp->flags & IF_MIB) && + if (itemp_has(temp, IF_MIB) && (opy->indexreg == -1 && opy->hintbase == opy->basereg && opy->hinttype == EAH_NOTBASE)) { opy->indexreg = opy->basereg; @@ -1310,7 +1310,7 @@ static int64_t calcsize(int32_t segment, int64_t offset, int bits, length++; } else if ((ins->rex & REX_L) && !(ins->rex & (REX_P|REX_W|REX_X|REX_B)) && - cpu >= IF_X86_64) { + iflag_ffs(&cpu) >= IF_X86_64) { /* LOCK-as-REX.R */ assert_no_prefix(ins, PPS_LOCK); lockcheck = false; /* Already errored, no need for warning */ @@ -1322,7 +1322,7 @@ static int64_t calcsize(int32_t segment, int64_t offset, int bits, } if (has_prefix(ins, PPS_LOCK, P_LOCK) && lockcheck && - (!(temp->flags & IF_LOCK) || !is_class(MEMORY, ins->oprs[0].type))) { + (!itemp_has(temp,IF_LOCK) || !is_class(MEMORY, ins->oprs[0].type))) { errfunc(ERR_WARNING | ERR_WARN_LOCK | ERR_PASS2 , "instruction is not lockable"); } @@ -2003,8 +2003,7 @@ static enum match_result find_match(const struct itemplate **tempp, m = MOK_GOOD; else m = MERR_INVALOP; - } else if (m == MERR_OPSIZEMISSING && - (temp->flags & IF_SMASK) != IF_SX) { + } else if (m == MERR_OPSIZEMISSING && !itemp_has(temp, IF_SX)) { /* * Missing operand size and a candidate for fuzzy matching... */ @@ -2090,7 +2089,7 @@ static enum match_result matches(const struct itemplate *itemp, /* * Is it legal? */ - if (!(optimizing > 0) && (itemp->flags & IF_OPT)) + if (!(optimizing > 0) && itemp_has(itemp, IF_OPT)) return MERR_INVALOP; /* @@ -2103,29 +2102,29 @@ static enum match_result matches(const struct itemplate *itemp, /* * Process size flags */ - switch (itemp->flags & IF_SMASK) { - case IF_SB: + switch (itemp_smask(itemp)) { + case IF_GENBIT(IF_SB): asize = BITS8; break; - case IF_SW: + case IF_GENBIT(IF_SW): asize = BITS16; break; - case IF_SD: + case IF_GENBIT(IF_SD): asize = BITS32; break; - case IF_SQ: + case IF_GENBIT(IF_SQ): asize = BITS64; break; - case IF_SO: + case IF_GENBIT(IF_SO): asize = BITS128; break; - case IF_SY: + case IF_GENBIT(IF_SY): asize = BITS256; break; - case IF_SZ: + case IF_GENBIT(IF_SZ): asize = BITS512; break; - case IF_SIZE: + case IF_GENBIT(IF_SIZE): switch (bits) { case 16: asize = BITS16; @@ -2146,9 +2145,9 @@ static enum match_result matches(const struct itemplate *itemp, break; } - if (itemp->flags & IF_ARMASK) { + if (itemp_armask(itemp)) { /* S- flags only apply to a specific operand */ - i = ((itemp->flags & IF_ARMASK) >> IF_ARSHFT) - 1; + i = itemp_arg(itemp); memset(size, 0, sizeof size); size[i] = asize; } else { @@ -2235,10 +2234,10 @@ static enum match_result matches(const struct itemplate *itemp, } } else if (is_register(instruction->oprs[i].basereg) && nasm_regvals[instruction->oprs[i].basereg] >= 16 && - !(itemp->flags & IF_AVX512)) { + !itemp_has(itemp, IF_AVX512)) { return MERR_ENCMISMATCH; } else if (instruction->prefixes[PPS_EVEX] && - !(itemp->flags & IF_AVX512)) { + !itemp_has(itemp, IF_AVX512)) { return MERR_ENCMISMATCH; } } @@ -2249,8 +2248,8 @@ static enum match_result matches(const struct itemplate *itemp, /* * Check operand sizes */ - if (itemp->flags & (IF_SM | IF_SM2)) { - oprs = (itemp->flags & IF_SM2 ? 2 : itemp->operands); + if (itemp_has(itemp, IF_SM) || itemp_has(itemp, IF_SM2)) { + oprs = (itemp_has(itemp, IF_SM2) ? 2 : itemp->operands); for (i = 0; i < oprs; i++) { asize = itemp->opd[i] & SIZE_MASK; if (asize) { @@ -2272,19 +2271,19 @@ static enum match_result matches(const struct itemplate *itemp, /* * Check template is okay at the set cpu level */ - if (((itemp->flags & IF_PLEVEL) > cpu)) + if (iflag_cmp_cpu_level(&insns_flags[itemp->iflag_idx], &cpu) > 0) return MERR_BADCPU; /* * Verify the appropriate long mode flag. */ - if ((itemp->flags & (bits == 64 ? IF_NOLONG : IF_LONG))) + if (itemp_has(itemp, (bits == 64 ? IF_NOLONG : IF_LONG))) return MERR_BADMODE; /* * If we have a HLE prefix, look for the NOHLE flag */ - if ((itemp->flags & IF_NOHLE) && + if (itemp_has(itemp, IF_NOHLE) && (has_prefix(instruction, PPS_REP, P_XACQUIRE) || has_prefix(instruction, PPS_REP, P_XRELEASE))) return MERR_BADHLE; @@ -2298,7 +2297,7 @@ static enum match_result matches(const struct itemplate *itemp, /* * Check if BND prefix is allowed */ - if ((IF_BND & ~itemp->flags) && + if (!itemp_has(itemp, IF_BND) && has_prefix(instruction, PPS_REP, P_BND)) return MERR_BADBND; diff --git a/assemble.h b/assemble.h index 1197d59..381e3ab 100644 --- a/assemble.h +++ b/assemble.h @@ -38,10 +38,11 @@ #ifndef NASM_ASSEMBLE_H #define NASM_ASSEMBLE_H -int64_t insn_size(int32_t segment, int64_t offset, int bits, iflags_t cp, - insn * instruction, efunc error); -int64_t assemble(int32_t segment, int64_t offset, int bits, iflags_t cp, - insn * instruction, struct ofmt *output, efunc error, - ListGen * listgen); +#include "iflag.h" +int64_t insn_size(int32_t segment, int64_t offset, int bits, iflag_t cp, + insn * instruction, efunc error); +int64_t assemble(int32_t segment, int64_t offset, int bits, iflag_t cp, + insn * instruction, struct ofmt *output, efunc error, + ListGen * listgen); #endif diff --git a/disasm.c b/disasm.c index 9064b65..b7c5027 100644 --- a/disasm.c +++ b/disasm.c @@ -501,11 +501,11 @@ static int matches(const struct itemplate *t, uint8_t *data, ins->rex = prefix->rex; memset(ins->prefixes, 0, sizeof ins->prefixes); - if (t->flags & (segsize == 64 ? IF_NOLONG : IF_LONG)) + if (itemp_has(t, (segsize == 64 ? IF_NOLONG : IF_LONG))) return false; if (prefix->rep == 0xF2) - drep = (t->flags & IF_BND ? P_BND : P_REPNE); + drep = (itemp_has(t, IF_BND) ? P_BND : P_REPNE); else if (prefix->rep == 0xF3) drep = P_REP; @@ -1099,7 +1099,7 @@ static const char * const condition_name[16] = { }; int32_t disasm(uint8_t *data, char *output, int outbufsize, int segsize, - int32_t offset, int autosync, iflags_t prefer) + int32_t offset, int autosync, iflag_t *prefer) { const struct itemplate * const *p, * const *best_p; const struct disasm_index *ix; @@ -1110,7 +1110,7 @@ int32_t disasm(uint8_t *data, char *output, int outbufsize, int segsize, uint8_t *origdata; int works; insn tmp_ins, ins; - iflags_t goodness, best, flags; + iflag_t goodness, best; int best_pref; struct prefix_info prefix; bool end_prefix; @@ -1277,7 +1277,7 @@ int32_t disasm(uint8_t *data, char *output, int outbufsize, int segsize, } } - best = -1; /* Worst possible */ + iflag_set_all(&best); /* Worst possible */ best_p = NULL; best_pref = INT_MAX; @@ -1331,13 +1331,14 @@ int32_t disasm(uint8_t *data, char *output, int outbufsize, int segsize, */ if (works) { int i, nprefix; - goodness = ((*p)->flags & IF_PFMASK) ^ prefer; - nprefix = 0; - for (i = 0; i < MAXPREFIX; i++) - if (tmp_ins.prefixes[i]) - nprefix++; + goodness = iflag_pfmask(*p); + goodness = iflag_xor(&goodness, prefer); + nprefix = 0; + for (i = 0; i < MAXPREFIX; i++) + if (tmp_ins.prefixes[i]) + nprefix++; if (nprefix < best_pref || - (nprefix == best_pref && goodness < best)) { + (nprefix == best_pref && iflag_cmp(&goodness, &best) == -1)) { /* This is the best one found so far */ best = goodness; best_p = p; @@ -1355,7 +1356,6 @@ int32_t disasm(uint8_t *data, char *output, int outbufsize, int segsize, /* Pick the best match */ p = best_p; length = best_length; - flags = (*p)->flags; slen = 0; @@ -1528,7 +1528,7 @@ int32_t disasm(uint8_t *data, char *output, int outbufsize, int segsize, nasm_reg_names[(o->basereg-EXPR_REG_START)]); started = true; } - if (o->indexreg != -1 && !(flags & IF_MIB)) { + if (o->indexreg != -1 && !itemp_has(*best_p, IF_MIB)) { if (started) output[slen++] = '+'; slen += snprintf(output + slen, outbufsize - slen, "%s", @@ -1607,7 +1607,7 @@ int32_t disasm(uint8_t *data, char *output, int outbufsize, int segsize, } } - if (o->indexreg != -1 && (flags & IF_MIB)) { + if (o->indexreg != -1 && itemp_has(*best_p, IF_MIB)) { output[slen++] = ','; slen += snprintf(output + slen, outbufsize - slen, "%s", nasm_reg_names[(o->indexreg-EXPR_REG_START)]); diff --git a/disasm.h b/disasm.h index 70a9a7b..fa6e2e2 100644 --- a/disasm.h +++ b/disasm.h @@ -38,10 +38,12 @@ #ifndef NASM_DISASM_H #define NASM_DISASM_H +#include "iflag.h" + #define INSN_MAX 32 /* one instruction can't be longer than this */ int32_t disasm(uint8_t *data, char *output, int outbufsize, int segsize, - int32_t offset, int autosync, iflags_t prefer); + int32_t offset, int autosync, iflag_t *prefer); int32_t eatbyte(uint8_t *data, char *output, int outbufsize, int segsize); #endif diff --git a/insns.h b/insns.h index dd447c5..8f04d13 100644 --- a/insns.h +++ b/insns.h @@ -11,6 +11,7 @@ #include "nasm.h" #include "tokens.h" +#include "iflag.h" /* if changed, ITEMPLATE_END should be also changed accordingly */ struct itemplate { @@ -19,7 +20,7 @@ struct itemplate { opflags_t opd[MAX_OPERANDS]; /* bit flags for operand types */ decoflags_t deco[MAX_OPERANDS]; /* bit flags for operand decorators */ const uint8_t *code; /* the code it assembles to */ - iflags_t flags; /* some flags */ + uint32_t iflag_idx; /* some flags referenced by index */ }; /* Disassembler table structure */ @@ -47,119 +48,4 @@ extern const uint8_t nasm_bytecodes[]; */ #define ITEMPLATE_END {-1,-1,{-1,-1,-1,-1,-1},{-1,-1,-1,-1,-1},NULL,0} -/* - * Instruction template flags. These specify which processor - * targets the instruction is eligible for, whether it is - * privileged or undocumented, and also specify extra error - * checking on the matching of the instruction. - * - * IF_SM stands for Size Match: any operand whose size is not - * explicitly specified by the template is `really' intended to be - * the same size as the first size-specified operand. - * Non-specification is tolerated in the input instruction, but - * _wrong_ specification is not. - * - * IF_SM2 invokes Size Match on only the first _two_ operands, for - * three-operand instructions such as SHLD: it implies that the - * first two operands must match in size, but that the third is - * required to be _unspecified_. - * - * IF_SB invokes Size Byte: operands with unspecified size in the - * template are really bytes, and so no non-byte specification in - * the input instruction will be tolerated. IF_SW similarly invokes - * Size Word, and IF_SD invokes Size Doubleword. - * - * (The default state if neither IF_SM nor IF_SM2 is specified is - * that any operand with unspecified size in the template is - * required to have unspecified size in the instruction too...) - * - * iflags_t is defined to store these flags. - */ - -#define IF_SM UINT64_C(0x00000001) /* size match */ -#define IF_SM2 UINT64_C(0x00000002) /* size match first two operands */ -#define IF_SB UINT64_C(0x00000004) /* unsized operands can't be non-byte */ -#define IF_SW UINT64_C(0x00000008) /* unsized operands can't be non-word */ -#define IF_SD UINT64_C(0x0000000C) /* unsized operands can't be non-dword */ -#define IF_SQ UINT64_C(0x00000010) /* unsized operands can't be non-qword */ -#define IF_SO UINT64_C(0x00000014) /* unsized operands can't be non-oword */ -#define IF_SY UINT64_C(0x00000018) /* unsized operands can't be non-yword */ -#define IF_SZ UINT64_C(0x0000001C) /* unsized operands can't be non-zword */ -#define IF_SIZE UINT64_C(0x00000038) /* unsized operands must match the bitsize */ -#define IF_SX UINT64_C(0x0000003C) /* unsized operands not allowed */ -#define IF_SMASK UINT64_C(0x0000003C) /* mask for unsized argument size */ -#define IF_AR0 UINT64_C(0x00000040) /* SB, SW, SD applies to argument 0 */ -#define IF_AR1 UINT64_C(0x00000080) /* SB, SW, SD applies to argument 1 */ -#define IF_AR2 UINT64_C(0x000000C0) /* SB, SW, SD applies to argument 2 */ -#define IF_AR3 UINT64_C(0x00000100) /* SB, SW, SD applies to argument 3 */ -#define IF_AR4 UINT64_C(0x00000140) /* SB, SW, SD applies to argument 4 */ -#define IF_ARMASK UINT64_C(0x000001C0) /* mask for unsized argument spec */ -#define IF_ARSHFT 6 /* LSB in IF_ARMASK */ -#define IF_OPT UINT64_C(0x00000200) /* optimizing assembly only */ -/* The next 3 bits aren't actually used for anything */ -#define IF_PRIV UINT64_C(0x00000000) /* it's a privileged instruction */ -#define IF_SMM UINT64_C(0x00000000) /* it's only valid in SMM */ -#define IF_PROT UINT64_C(0x00000000) /* it's protected mode only */ -#define IF_LOCK UINT64_C(0x00000400) /* lockable if operand 0 is memory */ -#define IF_NOLONG UINT64_C(0x00000800) /* it's not available in long mode */ -#define IF_LONG UINT64_C(0x00001000) /* long mode instruction */ -#define IF_NOHLE UINT64_C(0x00002000) /* HLE prefixes forbidden */ -#define IF_MIB UINT64_C(0x00004000) /* Disassemble with split EA */ -#define IF_BND UINT64_C(0x00008000) /* BND (0xF2) prefix available */ -/* These flags are currently not used for anything - intended for insn set */ -#define IF_UNDOC UINT64_C(0x8000000000) /* it's an undocumented instruction */ -#define IF_HLE UINT64_C(0x4000000000) /* HACK NEED TO REORGANIZE THESE BITS */ -#define IF_AVX512 UINT64_C(0x2000000000) /* it's an AVX-512F (512b) instruction */ -#define IF_FPU UINT64_C(0x0100000000) /* it's an FPU instruction */ -#define IF_MMX UINT64_C(0x0200000000) /* it's an MMX instruction */ -#define IF_3DNOW UINT64_C(0x0300000000) /* it's a 3DNow! instruction */ -#define IF_SSE UINT64_C(0x0400000000) /* it's a SSE (KNI, MMX2) instruction */ -#define IF_SSE2 UINT64_C(0x0500000000) /* it's a SSE2 instruction */ -#define IF_SSE3 UINT64_C(0x0600000000) /* it's a SSE3 (PNI) instruction */ -#define IF_VMX UINT64_C(0x0700000000) /* it's a VMX instruction */ -#define IF_SSSE3 UINT64_C(0x0800000000) /* it's an SSSE3 instruction */ -#define IF_SSE4A UINT64_C(0x0900000000) /* AMD SSE4a */ -#define IF_SSE41 UINT64_C(0x0A00000000) /* it's an SSE4.1 instruction */ -#define IF_SSE42 UINT64_C(0x0B00000000) /* HACK NEED TO REORGANIZE THESE BITS */ -#define IF_SSE5 UINT64_C(0x0C00000000) /* HACK NEED TO REORGANIZE THESE BITS */ -#define IF_AVX UINT64_C(0x0D00000000) /* it's an AVX (128b) instruction */ -#define IF_AVX2 UINT64_C(0x0E00000000) /* it's an AVX2 (256b) instruction */ -#define IF_FMA UINT64_C(0x1000000000) /* HACK NEED TO REORGANIZE THESE BITS */ -#define IF_BMI1 UINT64_C(0x1100000000) /* HACK NEED TO REORGANIZE THESE BITS */ -#define IF_BMI2 UINT64_C(0x1200000000) /* HACK NEED TO REORGANIZE THESE BITS */ -#define IF_TBM UINT64_C(0x1300000000) /* HACK NEED TO REORGANIZE THESE BITS */ -#define IF_RTM UINT64_C(0x1400000000) /* HACK NEED TO REORGANIZE THESE BITS */ -#define IF_INVPCID UINT64_C(0x1500000000) /* HACK NEED TO REORGANIZE THESE BITS */ -#define IF_AVX512CD (UINT64_C(0x1600000000)|IF_AVX512) /* AVX-512 Conflict Detection insns */ -#define IF_AVX512ER (UINT64_C(0x1700000000)|IF_AVX512) /* AVX-512 Exponential and Reciprocal */ -#define IF_AVX512PF (UINT64_C(0x1800000000)|IF_AVX512) /* AVX-512 Prefetch instructions */ -#define IF_MPX UINT64_C(0x1900000000) /* MPX instructions */ -#define IF_SHA UINT64_C(0x1A00000000) /* SHA instructions */ -#define IF_PREFETCHWT1 UINT64_C(0x1F00000000) /* PREFETCHWT1 instructions */ -#define IF_INSMASK UINT64_C(0xFF00000000) /* the mask for instruction set types */ -#define IF_PMASK UINT64_C(0xFF000000) /* the mask for processor types */ -#define IF_PLEVEL UINT64_C(0x0F000000) /* the mask for processor instr. level */ - /* also the highest possible processor */ -#define IF_8086 UINT64_C(0x00000000) /* 8086 instruction */ -#define IF_186 UINT64_C(0x01000000) /* 186+ instruction */ -#define IF_286 UINT64_C(0x02000000) /* 286+ instruction */ -#define IF_386 UINT64_C(0x03000000) /* 386+ instruction */ -#define IF_486 UINT64_C(0x04000000) /* 486+ instruction */ -#define IF_PENT UINT64_C(0x05000000) /* Pentium instruction */ -#define IF_P6 UINT64_C(0x06000000) /* P6 instruction */ -#define IF_KATMAI UINT64_C(0x07000000) /* Katmai instructions */ -#define IF_WILLAMETTE UINT64_C(0x08000000) /* Willamette instructions */ -#define IF_PRESCOTT UINT64_C(0x09000000) /* Prescott instructions */ -#define IF_X86_64 UINT64_C(0x0A000000) /* x86-64 instruction (long or legacy mode) */ -#define IF_NEHALEM UINT64_C(0x0B000000) /* Nehalem instruction */ -#define IF_WESTMERE UINT64_C(0x0C000000) /* Westmere instruction */ -#define IF_SANDYBRIDGE UINT64_C(0x0D000000) /* Sandy Bridge instruction */ -#define IF_FUTURE UINT64_C(0x0E000000) /* Future processor (not yet disclosed) */ -#define IF_X64 (IF_LONG|IF_X86_64) -#define IF_IA64 UINT64_C(0x0F000000) /* IA64 instructions (in x86 mode) */ -#define IF_CYRIX UINT64_C(0x10000000) /* Cyrix-specific instruction */ -#define IF_AMD UINT64_C(0x20000000) /* AMD-specific instruction */ -#define IF_SPMASK UINT64_C(0x30000000) /* specific processor types mask */ -#define IF_PFMASK (IF_INSMASK|IF_SPMASK) /* disassembly "prefer" mask */ - #endif /* NASM_INSNS_H */ diff --git a/insns.pl b/insns.pl index 8bd76ab..bf91469 100755 --- a/insns.pl +++ b/insns.pl @@ -37,6 +37,8 @@ # # Parse insns.dat and produce generated source code files +require 'insns-iflags.pl'; + # Opcode prefixes which need their own opcode tables # LONGER PREFIXES FIRST! @disasm_prefixes = qw(0F24 0F25 0F38 0F3A 0F7A 0FA6 0FA7 0F); @@ -67,7 +69,7 @@ print STDERR "Reading insns.dat...\n"; undef $output; foreach $arg ( @ARGV ) { if ( $arg =~ /^\-/ ) { - if ( $arg =~ /^\-([abdin])$/ ) { + if ( $arg =~ /^\-([abdint])$/ ) { $output = $1; } else { die "$0: Unknown option: ${arg}\n"; @@ -393,6 +395,10 @@ if ( !defined($output) || $output eq 'n' ) { close N; } +if ( !defined($output) || $output eq 't') { + write_iflags(); +} + printf STDERR "Done: %d instructions\n", $insns; # Count primary bytecodes, for statistics @@ -424,7 +430,7 @@ sub count_bytecodes(@) { sub format_insn($$$$$) { my ($opcode, $operands, $codes, $flags, $relax) = @_; - my $num, $nd = 0; + my $num, $nd = 0, $rawflags, $flagsindex; my @bytecode; my $op, @ops, $opp, @opx, @oppx, @decos, @opevex; my @iflags = ( "FPU", "MMX", "3DNOW", "SSE", "SSE2", @@ -492,16 +498,23 @@ sub format_insn($$$$$) { } # format the flags - $flags =~ s/,/|IF_/g; - $flags =~ s/(\|IF_ND|IF_ND\|)//, $nd = 1 if $flags =~ /IF_ND/; - $flags = "IF_" . $flags; + $nd = 1 if $flags =~ /(^|\,)ND($|\,)/; + $flags =~ s/(^|\,)ND($|\,)/\1/g; + $flags =~ s/(^|\,)X64($|\,)/\1LONG,X86_64\2/g; + $flags =~ s/(^|\,)AVX512CD($|\,)/\1AVX512CD,AVX512\2/g; + $flags =~ s/(^|\,)AVX512ER($|\,)/\1AVX512ER,AVX512\2/g; + $flags =~ s/(^|\,)AVX512PF($|\,)/\1AVX512PF,AVX512\2/g; + $rawflags = $flags; + $flagsindex = insns_flag_index(split(',',$flags)); + + die "Error in flags $rawflags" if not defined($flagsindex); @bytecode = (decodify($codes, $relax), 0); push(@bytecode_list, [@bytecode]); $codes = hexstr(@bytecode); count_bytecodes(@bytecode); - ("{I_$opcode, $num, {$operands}, $decorators, \@\@CODES-$codes\@\@, $flags},", $nd); + ("{I_$opcode, $num, {$operands}, $decorators, \@\@CODES-$codes\@\@, $flagsindex},", $nd); } # diff --git a/nasm.c b/nasm.c index 3a0c050..b83810d 100644 --- a/nasm.c +++ b/nasm.c @@ -60,6 +60,7 @@ #include "labels.h" #include "output/outform.h" #include "listing.h" +#include "iflag.h" /* * This is the maximum number of optimization passes to do. If we ever @@ -74,7 +75,7 @@ struct forwrefinfo { /* info held on forward refs. */ }; static int get_bits(char *value); -static iflags_t get_cpu(char *cpu_str); +static iflag_t get_cpu(char *cpu_str); static void parse_cmdline(int, char **); static void assemble_file(char *, StrList **); static void nasm_verror_gnu(int severity, const char *fmt, va_list args); @@ -106,8 +107,10 @@ static FILE *error_file; /* Where to write error messages */ FILE *ofile = NULL; int optimizing = MAX_OPTIMIZE; /* number of optimization passes to take */ static int sb, cmd_sb = 16; /* by default */ -static iflags_t cmd_cpu = IF_PLEVEL; /* highest level by default */ -static iflags_t cpu = IF_PLEVEL; /* passed to insn_size & assemble.c */ + +static iflag_t cpu; +static iflag_t cmd_cpu; + int64_t global_offset_changed; /* referenced in labels.c */ int64_t prev_offset_changed; int32_t stall_count; @@ -321,6 +324,9 @@ int main(int argc, char **argv) time(&official_compile_time); + iflag_set(&cpu, IF_PLEVEL); + iflag_set(&cmd_cpu, IF_PLEVEL); + pass0 = 0; want_usage = terminate_after_phase = false; nasm_set_verror(nasm_verror_gnu); @@ -1187,7 +1193,7 @@ static void assemble_file(char *fname, StrList **depend_ptr) expr *e; int pass_max; - if (cmd_sb == 32 && cmd_cpu < IF_386) + if (cmd_sb == 32 && iflag_ffs(&cmd_cpu) < IF_386) nasm_error(ERR_FATAL, "command line: " "32-bit segment size requires a higher cpu"); @@ -2006,44 +2012,53 @@ static void usage(void) fputs("type `nasm -h' for help\n", error_file); } -static iflags_t get_cpu(char *value) +static iflag_t get_cpu(char *value) { + iflag_t r; + + iflag_clear_all(&r); + if (!strcmp(value, "8086")) - return IF_8086; - if (!strcmp(value, "186")) - return IF_186; - if (!strcmp(value, "286")) - return IF_286; - if (!strcmp(value, "386")) - return IF_386; - if (!strcmp(value, "486")) - return IF_486; - if (!strcmp(value, "586") || !nasm_stricmp(value, "pentium")) - return IF_PENT; - if (!strcmp(value, "686") || - !nasm_stricmp(value, "ppro") || - !nasm_stricmp(value, "pentiumpro") || !nasm_stricmp(value, "p2")) - return IF_P6; - if (!nasm_stricmp(value, "p3") || !nasm_stricmp(value, "katmai")) - return IF_KATMAI; - if (!nasm_stricmp(value, "p4") || /* is this right? -- jrc */ - !nasm_stricmp(value, "willamette")) - return IF_WILLAMETTE; - if (!nasm_stricmp(value, "prescott")) - return IF_PRESCOTT; - if (!nasm_stricmp(value, "x64") || - !nasm_stricmp(value, "x86-64")) - return IF_X86_64; - if (!nasm_stricmp(value, "ia64") || - !nasm_stricmp(value, "ia-64") || - !nasm_stricmp(value, "itanium") || - !nasm_stricmp(value, "itanic") || !nasm_stricmp(value, "merced")) - return IF_IA64; - - nasm_error(pass0 < 2 ? ERR_NONFATAL : ERR_FATAL, - "unknown 'cpu' type"); - - return IF_PLEVEL; /* the maximum level */ + iflag_set(&r, IF_8086); + else if (!strcmp(value, "186")) + iflag_set(&r, IF_186); + else if (!strcmp(value, "286")) + iflag_set(&r, IF_286); + else if (!strcmp(value, "386")) + iflag_set(&r, IF_386); + else if (!strcmp(value, "486")) + iflag_set(&r, IF_486); + else if (!strcmp(value, "586") || + !nasm_stricmp(value, "pentium")) + iflag_set(&r, IF_PENT); + else if (!strcmp(value, "686") || + !nasm_stricmp(value, "ppro") || + !nasm_stricmp(value, "pentiumpro") || + !nasm_stricmp(value, "p2")) + iflag_set(&r, IF_P6); + else if (!nasm_stricmp(value, "p3") || + !nasm_stricmp(value, "katmai")) + iflag_set(&r, IF_KATMAI); + else if (!nasm_stricmp(value, "p4") || /* is this right? -- jrc */ + !nasm_stricmp(value, "willamette")) + iflag_set(&r, IF_WILLAMETTE); + else if (!nasm_stricmp(value, "prescott")) + iflag_set(&r, IF_PRESCOTT); + else if (!nasm_stricmp(value, "x64") || + !nasm_stricmp(value, "x86-64")) + iflag_set(&r, IF_X86_64); + else if (!nasm_stricmp(value, "ia64") || + !nasm_stricmp(value, "ia-64") || + !nasm_stricmp(value, "itanium")|| + !nasm_stricmp(value, "itanic") || + !nasm_stricmp(value, "merced")) + iflag_set(&r, IF_IA64); + else { + iflag_set(&r, IF_PLEVEL); + nasm_error(pass0 < 2 ? ERR_NONFATAL : ERR_FATAL, + "unknown 'cpu' type"); + } + return r; } static int get_bits(char *value) @@ -2053,13 +2068,13 @@ static int get_bits(char *value) if ((i = atoi(value)) == 16) return i; /* set for a 16-bit segment */ else if (i == 32) { - if (cpu < IF_386) { + if (iflag_ffs(&cpu) < IF_386) { nasm_error(ERR_NONFATAL, "cannot specify 32-bit segment on processor below a 386"); i = 16; } } else if (i == 64) { - if (cpu < IF_X86_64) { + if (iflag_ffs(&cpu) < IF_X86_64) { nasm_error(ERR_NONFATAL, "cannot specify 64-bit segment on processor below an x86-64"); i = 16; diff --git a/ndisasm.c b/ndisasm.c index 638299f..3212629 100644 --- a/ndisasm.c +++ b/ndisasm.c @@ -88,7 +88,7 @@ int main(int argc, char **argv) bool autosync = false; int bits = 16, b; bool eof = false; - iflags_t prefer = 0; + iflag_t prefer; bool rn_error; int32_t offset; FILE *fp; @@ -96,6 +96,7 @@ int main(int argc, char **argv) tolower_init(); nasm_set_verror(ndisasm_verror); nasm_init_malloc_error(); + iflag_clear_all(&prefer); offset = 0; init_sync(); @@ -229,14 +230,20 @@ int main(int argc, char **argv) return 1; } if (!strcmp(v, "intel")) { - prefer = 0; /* Default */ + iflag_clear_all(&prefer); /* default */ } else if (!strcmp(v, "amd")) { - prefer = IF_AMD | IF_3DNOW; + iflag_clear_all(&prefer); + iflag_set(&prefer, IF_AMD); + iflag_set(&prefer, IF_3DNOW); } else if (!strcmp(v, "cyrix")) { - prefer = IF_CYRIX | IF_3DNOW; - } else if (!strcmp(v, "idt") || !strcmp(v, "centaur") - || !strcmp(v, "winchip")) { - prefer = IF_3DNOW; + iflag_clear_all(&prefer); + iflag_set(&prefer, IF_CYRIX); + iflag_set(&prefer, IF_3DNOW); + } else if (!strcmp(v, "idt") || + !strcmp(v, "centaur") || + !strcmp(v, "winchip")) { + iflag_clear_all(&prefer); + iflag_set(&prefer, IF_3DNOW); } else { fprintf(stderr, "%s: unknown vendor `%s' specified with `-p'\n", @@ -311,7 +318,7 @@ int main(int argc, char **argv) while (p > q && (p - q >= INSN_MAX || lenread == 0)) { lendis = disasm((uint8_t *) q, outbuf, sizeof(outbuf), bits, - offset, autosync, prefer); + offset, autosync, &prefer); if (!lendis || lendis > (p - q) || ((nextsync || synclen) && (uint32_t)lendis > nextsync - offset)) |
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From: nasm-bot f. C. G. <gor...@gm...> - 2013-11-24 09:30:39
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Commit-ID: ea882d0b595be687d34db59cd32a174970e56456 Gitweb: http://repo.or.cz/w/nasm.git?a=commitdiff;h=ea882d0b595be687d34db59cd32a174970e56456 Author: Cyrill Gorcunov <gor...@gm...> AuthorDate: Sun, 10 Nov 2013 11:45:24 +0400 Committer: Cyrill Gorcunov <gor...@gm...> CommitDate: Sun, 24 Nov 2013 13:21:04 +0400 insns: Restore back MMX,FPU flags In commit 9bb987d8e0330429afba42015b1fc7c7ca0d1b16 we had to drop some flags due to flags type used in nasm code. Since now flags internal structure is reworked, we can restore them back. Signed-off-by: Cyrill Gorcunov <gor...@gm...> --- insns.dat | 46 +++++++++++++++++++++++----------------------- insns.pl | 15 --------------- 2 files changed, 23 insertions(+), 38 deletions(-) diff --git a/insns.dat b/insns.dat index 5464f93..9e6c059 100644 --- a/insns.dat +++ b/insns.dat @@ -1520,8 +1520,8 @@ CMPPS xmmreg,xmmreg,imm [rmi: np 0f c2 /r ib,u] KATMAI,SSE,SB,AR2 CMPSS xmmreg,mem,imm [rmi: f3 0f c2 /r ib,u] KATMAI,SSE,SB,AR2 CMPSS xmmreg,xmmreg,imm [rmi: f3 0f c2 /r ib,u] KATMAI,SSE,SB,AR2 COMISS xmmreg,xmmrm32 [rm: np 0f 2f /r] KATMAI,SSE -CVTPI2PS xmmreg,mmxrm64 [rm: np 0f 2a /r] KATMAI,SSE -CVTPS2PI mmxreg,xmmrm64 [rm: np 0f 2d /r] KATMAI,SSE +CVTPI2PS xmmreg,mmxrm64 [rm: np 0f 2a /r] KATMAI,SSE,MMX +CVTPS2PI mmxreg,xmmrm64 [rm: np 0f 2d /r] KATMAI,SSE,MMX CVTSI2SS xmmreg,mem [rm: f3 0f 2a /r] KATMAI,SSE,SD,AR1,ND CVTSI2SS xmmreg,rm32 [rm: f3 0f 2a /r] KATMAI,SSE,SD,AR1 CVTSI2SS xmmreg,rm64 [rm: o64 f3 0f 2a /r] X64,SSE,SQ,AR1 @@ -1529,7 +1529,7 @@ CVTSS2SI reg32,xmmreg [rm: f3 0f 2d /r] KATMAI,SSE,SD,AR1 CVTSS2SI reg32,mem [rm: f3 0f 2d /r] KATMAI,SSE,SD,AR1 CVTSS2SI reg64,xmmreg [rm: o64 f3 0f 2d /r] X64,SSE,SD,AR1 CVTSS2SI reg64,mem [rm: o64 f3 0f 2d /r] X64,SSE,SD,AR1 -CVTTPS2PI mmxreg,xmmrm [rm: np 0f 2c /r] KATMAI,SSE,SQ +CVTTPS2PI mmxreg,xmmrm [rm: np 0f 2c /r] KATMAI,SSE,MMX,SQ CVTTSS2SI reg32,xmmrm [rm: f3 0f 2c /r] KATMAI,SSE,SD,AR1 CVTTSS2SI reg64,xmmrm [rm: o64 f3 0f 2c /r] X64,SSE,SD,AR1 DIVPS xmmreg,xmmrm128 [rm: np 0f 5e /r] KATMAI,SSE @@ -1574,10 +1574,10 @@ UNPCKLPS xmmreg,xmmrm128 [rm: np 0f 14 /r] KATMAI,SSE XORPS xmmreg,xmmrm128 [rm: np 0f 57 /r] KATMAI,SSE ;# Introduced in Deschutes but necessary for SSE support -FXRSTOR mem [m: np 0f ae /1] P6,SSE -FXRSTOR64 mem [m: o64 np 0f ae /1] X64,SSE -FXSAVE mem [m: np 0f ae /0] P6,SSE -FXSAVE64 mem [m: o64 np 0f ae /0] X64,SSE +FXRSTOR mem [m: np 0f ae /1] P6,SSE,FPU +FXRSTOR64 mem [m: o64 np 0f ae /1] X64,SSE,FPU +FXSAVE mem [m: np 0f ae /0] P6,SSE,FPU +FXSAVE64 mem [m: o64 np 0f ae /0] X64,SSE,FPU ;# XSAVE group (AVX and extended state) ; Introduced in late Penryn ... we really need to clean up the handling @@ -1869,37 +1869,37 @@ INVVPID reg32,mem [rm: 66 0f 38 81 /r] VMX,SO,NOLONG INVVPID reg64,mem [rm: o64nw 66 0f 38 81 /r] VMX,SO,LONG ;# Tejas New Instructions (SSSE3) -PABSB mmxreg,mmxrm [rm: np 0f 38 1c /r] SSSE3,SQ +PABSB mmxreg,mmxrm [rm: np 0f 38 1c /r] SSSE3,MMX,SQ PABSB xmmreg,xmmrm [rm: 66 0f 38 1c /r] SSSE3 -PABSW mmxreg,mmxrm [rm: np 0f 38 1d /r] SSSE3,SQ +PABSW mmxreg,mmxrm [rm: np 0f 38 1d /r] SSSE3,MMX,SQ PABSW xmmreg,xmmrm [rm: 66 0f 38 1d /r] SSSE3 -PABSD mmxreg,mmxrm [rm: np 0f 38 1e /r] SSSE3,SQ +PABSD mmxreg,mmxrm [rm: np 0f 38 1e /r] SSSE3,MMX,SQ PABSD xmmreg,xmmrm [rm: 66 0f 38 1e /r] SSSE3 -PALIGNR mmxreg,mmxrm,imm [rmi: np 0f 3a 0f /r ib,u] SSSE3,SQ +PALIGNR mmxreg,mmxrm,imm [rmi: np 0f 3a 0f /r ib,u] SSSE3,MMX,SQ PALIGNR xmmreg,xmmrm,imm [rmi: 66 0f 3a 0f /r ib,u] SSSE3 -PHADDW mmxreg,mmxrm [rm: np 0f 38 01 /r] SSSE3,SQ +PHADDW mmxreg,mmxrm [rm: np 0f 38 01 /r] SSSE3,MMX,SQ PHADDW xmmreg,xmmrm [rm: 66 0f 38 01 /r] SSSE3 -PHADDD mmxreg,mmxrm [rm: np 0f 38 02 /r] SSSE3,SQ +PHADDD mmxreg,mmxrm [rm: np 0f 38 02 /r] SSSE3,MMX,SQ PHADDD xmmreg,xmmrm [rm: 66 0f 38 02 /r] SSSE3 -PHADDSW mmxreg,mmxrm [rm: np 0f 38 03 /r] SSSE3,SQ +PHADDSW mmxreg,mmxrm [rm: np 0f 38 03 /r] SSSE3,MMX,SQ PHADDSW xmmreg,xmmrm [rm: 66 0f 38 03 /r] SSSE3 -PHSUBW mmxreg,mmxrm [rm: np 0f 38 05 /r] SSSE3,SQ +PHSUBW mmxreg,mmxrm [rm: np 0f 38 05 /r] SSSE3,MMX,SQ PHSUBW xmmreg,xmmrm [rm: 66 0f 38 05 /r] SSSE3 -PHSUBD mmxreg,mmxrm [rm: np 0f 38 06 /r] SSSE3,SQ +PHSUBD mmxreg,mmxrm [rm: np 0f 38 06 /r] SSSE3,MMX,SQ PHSUBD xmmreg,xmmrm [rm: 66 0f 38 06 /r] SSSE3 -PHSUBSW mmxreg,mmxrm [rm: np 0f 38 07 /r] SSSE3,SQ +PHSUBSW mmxreg,mmxrm [rm: np 0f 38 07 /r] SSSE3,MMX,SQ PHSUBSW xmmreg,xmmrm [rm: 66 0f 38 07 /r] SSSE3 -PMADDUBSW mmxreg,mmxrm [rm: np 0f 38 04 /r] SSSE3,SQ +PMADDUBSW mmxreg,mmxrm [rm: np 0f 38 04 /r] SSSE3,MMX,SQ PMADDUBSW xmmreg,xmmrm [rm: 66 0f 38 04 /r] SSSE3 -PMULHRSW mmxreg,mmxrm [rm: np 0f 38 0b /r] SSSE3,SQ +PMULHRSW mmxreg,mmxrm [rm: np 0f 38 0b /r] SSSE3,MMX,SQ PMULHRSW xmmreg,xmmrm [rm: 66 0f 38 0b /r] SSSE3 -PSHUFB mmxreg,mmxrm [rm: np 0f 38 00 /r] SSSE3,SQ +PSHUFB mmxreg,mmxrm [rm: np 0f 38 00 /r] SSSE3,MMX,SQ PSHUFB xmmreg,xmmrm [rm: 66 0f 38 00 /r] SSSE3 -PSIGNB mmxreg,mmxrm [rm: np 0f 38 08 /r] SSSE3,SQ +PSIGNB mmxreg,mmxrm [rm: np 0f 38 08 /r] SSSE3,MMX,SQ PSIGNB xmmreg,xmmrm [rm: 66 0f 38 08 /r] SSSE3 -PSIGNW mmxreg,mmxrm [rm: np 0f 38 09 /r] SSSE3,SQ +PSIGNW mmxreg,mmxrm [rm: np 0f 38 09 /r] SSSE3,MMX,SQ PSIGNW xmmreg,xmmrm [rm: 66 0f 38 09 /r] SSSE3 -PSIGND mmxreg,mmxrm [rm: np 0f 38 0a /r] SSSE3,SQ +PSIGND mmxreg,mmxrm [rm: np 0f 38 0a /r] SSSE3,MMX,SQ PSIGND xmmreg,xmmrm [rm: 66 0f 38 0a /r] SSSE3 ;# AMD SSE4A diff --git a/insns.pl b/insns.pl index bf91469..c9d7b7f 100755 --- a/insns.pl +++ b/insns.pl @@ -433,10 +433,6 @@ sub format_insn($$$$$) { my $num, $nd = 0, $rawflags, $flagsindex; my @bytecode; my $op, @ops, $opp, @opx, @oppx, @decos, @opevex; - my @iflags = ( "FPU", "MMX", "3DNOW", "SSE", "SSE2", - "SSE3", "VMX", "SSSE3", "SSE4A", "SSE41", - "SSE42", "SSE5", "AVX", "AVX2", "AVX512", - "FMA", "BMI1", "BMI2", "TBM", "RTM", "INVPCID"); return (undef, undef) if $operands eq "ignore"; @@ -486,17 +482,6 @@ sub format_insn($$$$$) { } $decorators =~ tr/a-z/A-Z/; - # check if two different insn set types are set - $cnt = 0; - foreach $fla (split(/,/, $flags)) { - if (grep(/$fla/, @iflags)) { - $cnt++; - if ($cnt >= 2) { - die "Too many insn set flags in $flags\n"; - } - } - } - # format the flags $nd = 1 if $flags =~ /(^|\,)ND($|\,)/; $flags =~ s/(^|\,)ND($|\,)/\1/g; |
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From: nasm-bot f. C. G. <gor...@gm...> - 2013-11-24 09:30:38
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Commit-ID: acfb97d3db0b91742465540c4558890e3c80fc8a Gitweb: http://repo.or.cz/w/nasm.git?a=commitdiff;h=acfb97d3db0b91742465540c4558890e3c80fc8a Author: Cyrill Gorcunov <gor...@gm...> AuthorDate: Sun, 24 Nov 2013 12:26:35 +0400 Committer: Cyrill Gorcunov <gor...@gm...> CommitDate: Sun, 24 Nov 2013 12:26:35 +0400 make: Add 'golden' target We've 'test' target in toplevel Makefile, lets be complete and allow to generate "golden" tests from toplevel as well. Signed-off-by: Cyrill Gorcunov <gor...@gm...> --- Makefile.in | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Makefile.in b/Makefile.in index bd807f2..e4c56b5 100644 --- a/Makefile.in +++ b/Makefile.in @@ -275,6 +275,9 @@ splint: test: nasm$(X) cd test && $(PERL) performtest.pl --nasm=../nasm *.asm +golden: nasm$(X) + cd test && $(PERL) performtest.pl --golden --nasm=../nasm *.asm + # # This build dependencies in *ALL* makefiles. Partially for that reason, # it's expected to be invoked manually. |
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From: nasm-bot f. C. G. <gor...@gm...> - 2013-11-24 09:30:36
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Commit-ID: ddf803b498826146a058cc98a008a471d592b631 Gitweb: http://repo.or.cz/w/nasm.git?a=commitdiff;h=ddf803b498826146a058cc98a008a471d592b631 Author: Cyrill Gorcunov <gor...@gm...> AuthorDate: Sat, 9 Nov 2013 22:28:05 +0400 Committer: Cyrill Gorcunov <gor...@gm...> CommitDate: Sun, 24 Nov 2013 13:21:04 +0400 make: Update deps Signed-off-by: Cyrill Gorcunov <gor...@gm...> --- Makefile.in | 57 ++++++++++++++++++++++++++++------------------------ Mkfiles/msvc.mak | 52 +++++++++++++++++++++++++---------------------- Mkfiles/netware.mak | 54 +++++++++++++++++++++++++------------------------ Mkfiles/openwcom.mak | 57 ++++++++++++++++++++++++++++------------------------ Mkfiles/owlinux.mak | 52 +++++++++++++++++++++++++---------------------- 5 files changed, 146 insertions(+), 126 deletions(-) diff --git a/Makefile.in b/Makefile.in index c3dbc0f..98f233e 100644 --- a/Makefile.in +++ b/Makefile.in @@ -300,15 +300,15 @@ alldeps: perlreq # @object-ending: ".$(O)" # @path-separator: "/" #-- Everything below is generated by mkdep.pl - do not edit --# -assemble.$(O): assemble.c assemble.h compiler.h config.h directiv.h insns.h \ - insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h \ - tokens.h +assemble.$(O): assemble.c assemble.h compiler.h config.h directiv.h iflag.h \ + insns.h insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h \ + tables.h tokens.h crc64.$(O): crc64.c compiler.h config.h nasmlib.h directiv.$(O): directiv.c compiler.h config.h directiv.h hashtbl.h insnsi.h \ nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h -disasm.$(O): disasm.c compiler.h config.h directiv.h disasm.h insns.h \ - insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h regdis.h regs.h \ - sync.h tables.h tokens.h +disasm.$(O): disasm.c compiler.h config.h directiv.h disasm.h iflag.h \ + insns.h insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h regdis.h \ + regs.h sync.h tables.h tokens.h eval.$(O): eval.c compiler.h config.h directiv.h eval.h float.h insnsi.h \ labels.h nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h exprlib.$(O): exprlib.c compiler.h config.h directiv.h insnsi.h nasm.h \ @@ -317,13 +317,17 @@ float.$(O): float.c compiler.h config.h directiv.h float.h insnsi.h nasm.h \ nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h hashtbl.$(O): hashtbl.c compiler.h config.h directiv.h hashtbl.h insnsi.h \ nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h +iflag.$(O): iflag.c compiler.h config.h iflag.h ilog2.$(O): ilog2.c compiler.h config.h nasmlib.h -insnsa.$(O): insnsa.c compiler.h config.h directiv.h insns.h insnsi.h nasm.h \ - nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h tokens.h -insnsb.$(O): insnsb.c compiler.h config.h directiv.h insns.h insnsi.h nasm.h \ - nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h tokens.h -insnsd.$(O): insnsd.c compiler.h config.h directiv.h insns.h insnsi.h nasm.h \ - nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h tokens.h +insnsa.$(O): insnsa.c compiler.h config.h directiv.h iflag.h insns.h \ + insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h \ + tokens.h +insnsb.$(O): insnsb.c compiler.h config.h directiv.h iflag.h insns.h \ + insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h \ + tokens.h +insnsd.$(O): insnsd.c compiler.h config.h directiv.h iflag.h insns.h \ + insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h \ + tokens.h insnsn.$(O): insnsn.c compiler.h config.h insnsi.h tables.h labels.$(O): labels.c compiler.h config.h directiv.h hashtbl.h insnsi.h \ nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h @@ -336,13 +340,14 @@ macros.$(O): macros.c compiler.h config.h directiv.h hashtbl.h insnsi.h \ nasm.h nasmlib.h opflags.h output/outform.h pptok.h preproc.h regs.h \ tables.h nasm.$(O): nasm.c assemble.h compiler.h config.h directiv.h eval.h float.h \ - insns.h insnsi.h labels.h listing.h nasm.h nasmlib.h opflags.h \ + iflag.h insns.h insnsi.h labels.h listing.h nasm.h nasmlib.h opflags.h \ output/outform.h parser.h pptok.h preproc.h raa.h regs.h saa.h stdscan.h \ tables.h tokens.h -nasmlib.$(O): nasmlib.c compiler.h config.h directiv.h insns.h insnsi.h \ - nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h tokens.h -ndisasm.$(O): ndisasm.c compiler.h config.h directiv.h disasm.h insns.h \ - insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h sync.h \ +nasmlib.$(O): nasmlib.c compiler.h config.h directiv.h iflag.h insns.h \ + insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h \ + tokens.h +ndisasm.$(O): ndisasm.c compiler.h config.h directiv.h disasm.h iflag.h \ + insns.h insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h sync.h \ tables.h tokens.h output/nulldbg.$(O): output/nulldbg.c compiler.h config.h directiv.h \ insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h @@ -400,9 +405,9 @@ output/outobj.$(O): output/outobj.c compiler.h config.h directiv.h eval.h \ output/outrdf2.$(O): output/outrdf2.c compiler.h config.h directiv.h \ insnsi.h nasm.h nasmlib.h opflags.h output/outform.h output/outlib.h \ pptok.h preproc.h rdoff/rdoff.h regs.h saa.h tables.h -parser.$(O): parser.c compiler.h config.h directiv.h eval.h float.h insns.h \ - insnsi.h nasm.h nasmlib.h opflags.h parser.h pptok.h preproc.h regs.h \ - stdscan.h tables.h tokens.h +parser.$(O): parser.c compiler.h config.h directiv.h eval.h float.h iflag.h \ + insns.h insnsi.h nasm.h nasmlib.h opflags.h parser.h pptok.h preproc.h \ + regs.h stdscan.h tables.h tokens.h pptok.$(O): pptok.c compiler.h config.h hashtbl.h nasmlib.h pptok.h \ preproc.h preproc-nop.$(O): preproc-nop.c compiler.h config.h directiv.h insnsi.h \ @@ -419,14 +424,14 @@ regflags.$(O): regflags.c compiler.h config.h directiv.h insnsi.h nasm.h \ regs.$(O): regs.c compiler.h config.h insnsi.h tables.h regvals.$(O): regvals.c compiler.h config.h insnsi.h tables.h saa.$(O): saa.c compiler.h config.h nasmlib.h saa.h -stdscan.$(O): stdscan.c compiler.h config.h directiv.h insns.h insnsi.h \ - nasm.h nasmlib.h opflags.h pptok.h preproc.h quote.h regs.h stdscan.h \ - tables.h tokens.h +stdscan.$(O): stdscan.c compiler.h config.h directiv.h iflag.h insns.h \ + insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h quote.h regs.h \ + stdscan.h tables.h tokens.h strfunc.$(O): strfunc.c compiler.h config.h directiv.h insnsi.h nasm.h \ nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h sync.$(O): sync.c compiler.h config.h nasmlib.h sync.h -tokhash.$(O): tokhash.c compiler.h config.h directiv.h hashtbl.h insns.h \ - insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h \ - tokens.h +tokhash.$(O): tokhash.c compiler.h config.h directiv.h hashtbl.h iflag.h \ + insns.h insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h \ + tables.h tokens.h ver.$(O): ver.c compiler.h config.h directiv.h insnsi.h nasm.h nasmlib.h \ opflags.h pptok.h preproc.h regs.h tables.h version.h diff --git a/Mkfiles/msvc.mak b/Mkfiles/msvc.mak index e93219f..9548c9b 100644 --- a/Mkfiles/msvc.mak +++ b/Mkfiles/msvc.mak @@ -208,14 +208,15 @@ everything: all doc rdf # @path-separator: "/" # @exclude: "config.h" #-- Everything below is generated by mkdep.pl - do not edit --# -assemble.$(O): assemble.c assemble.h compiler.h directiv.h insns.h insnsi.h \ - nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h tokens.h +assemble.$(O): assemble.c assemble.h compiler.h directiv.h iflag.h insns.h \ + insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h \ + tokens.h crc64.$(O): crc64.c compiler.h nasmlib.h directiv.$(O): directiv.c compiler.h directiv.h hashtbl.h insnsi.h nasm.h \ nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h -disasm.$(O): disasm.c compiler.h directiv.h disasm.h insns.h insnsi.h nasm.h \ - nasmlib.h opflags.h pptok.h preproc.h regdis.h regs.h sync.h tables.h \ - tokens.h +disasm.$(O): disasm.c compiler.h directiv.h disasm.h iflag.h insns.h \ + insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h regdis.h regs.h \ + sync.h tables.h tokens.h eval.$(O): eval.c compiler.h directiv.h eval.h float.h insnsi.h labels.h \ nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h exprlib.$(O): exprlib.c compiler.h directiv.h insnsi.h nasm.h nasmlib.h \ @@ -224,12 +225,13 @@ float.$(O): float.c compiler.h directiv.h float.h insnsi.h nasm.h nasmlib.h \ opflags.h pptok.h preproc.h regs.h tables.h hashtbl.$(O): hashtbl.c compiler.h directiv.h hashtbl.h insnsi.h nasm.h \ nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h +iflag.$(O): iflag.c compiler.h iflag.h ilog2.$(O): ilog2.c compiler.h nasmlib.h -insnsa.$(O): insnsa.c compiler.h directiv.h insns.h insnsi.h nasm.h \ +insnsa.$(O): insnsa.c compiler.h directiv.h iflag.h insns.h insnsi.h nasm.h \ nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h tokens.h -insnsb.$(O): insnsb.c compiler.h directiv.h insns.h insnsi.h nasm.h \ +insnsb.$(O): insnsb.c compiler.h directiv.h iflag.h insns.h insnsi.h nasm.h \ nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h tokens.h -insnsd.$(O): insnsd.c compiler.h directiv.h insns.h insnsi.h nasm.h \ +insnsd.$(O): insnsd.c compiler.h directiv.h iflag.h insns.h insnsi.h nasm.h \ nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h tokens.h insnsn.$(O): insnsn.c compiler.h insnsi.h tables.h labels.$(O): labels.c compiler.h directiv.h hashtbl.h insnsi.h nasm.h \ @@ -241,14 +243,15 @@ listing.$(O): listing.c compiler.h directiv.h insnsi.h listing.h nasm.h \ nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h macros.$(O): macros.c compiler.h directiv.h hashtbl.h insnsi.h nasm.h \ nasmlib.h opflags.h output/outform.h pptok.h preproc.h regs.h tables.h -nasm.$(O): nasm.c assemble.h compiler.h directiv.h eval.h float.h insns.h \ - insnsi.h labels.h listing.h nasm.h nasmlib.h opflags.h output/outform.h \ - parser.h pptok.h preproc.h raa.h regs.h saa.h stdscan.h tables.h tokens.h -nasmlib.$(O): nasmlib.c compiler.h directiv.h insns.h insnsi.h nasm.h \ - nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h tokens.h -ndisasm.$(O): ndisasm.c compiler.h directiv.h disasm.h insns.h insnsi.h \ - nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h sync.h tables.h \ - tokens.h +nasm.$(O): nasm.c assemble.h compiler.h directiv.h eval.h float.h iflag.h \ + insns.h insnsi.h labels.h listing.h nasm.h nasmlib.h opflags.h \ + output/outform.h parser.h pptok.h preproc.h raa.h regs.h saa.h stdscan.h \ + tables.h tokens.h +nasmlib.$(O): nasmlib.c compiler.h directiv.h iflag.h insns.h insnsi.h \ + nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h tokens.h +ndisasm.$(O): ndisasm.c compiler.h directiv.h disasm.h iflag.h insns.h \ + insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h sync.h \ + tables.h tokens.h output/nulldbg.$(O): output/nulldbg.c compiler.h directiv.h insnsi.h nasm.h \ nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h output/nullout.$(O): output/nullout.c compiler.h directiv.h insnsi.h nasm.h \ @@ -301,9 +304,9 @@ output/outobj.$(O): output/outobj.c compiler.h directiv.h eval.h insnsi.h \ output/outrdf2.$(O): output/outrdf2.c compiler.h directiv.h insnsi.h nasm.h \ nasmlib.h opflags.h output/outform.h output/outlib.h pptok.h preproc.h \ rdoff/rdoff.h regs.h saa.h tables.h -parser.$(O): parser.c compiler.h directiv.h eval.h float.h insns.h insnsi.h \ - nasm.h nasmlib.h opflags.h parser.h pptok.h preproc.h regs.h stdscan.h \ - tables.h tokens.h +parser.$(O): parser.c compiler.h directiv.h eval.h float.h iflag.h insns.h \ + insnsi.h nasm.h nasmlib.h opflags.h parser.h pptok.h preproc.h regs.h \ + stdscan.h tables.h tokens.h pptok.$(O): pptok.c compiler.h hashtbl.h nasmlib.h pptok.h preproc.h preproc-nop.$(O): preproc-nop.c compiler.h directiv.h insnsi.h nasm.h \ nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h @@ -319,13 +322,14 @@ regflags.$(O): regflags.c compiler.h directiv.h insnsi.h nasm.h nasmlib.h \ regs.$(O): regs.c compiler.h insnsi.h tables.h regvals.$(O): regvals.c compiler.h insnsi.h tables.h saa.$(O): saa.c compiler.h nasmlib.h saa.h -stdscan.$(O): stdscan.c compiler.h directiv.h insns.h insnsi.h nasm.h \ - nasmlib.h opflags.h pptok.h preproc.h quote.h regs.h stdscan.h tables.h \ - tokens.h +stdscan.$(O): stdscan.c compiler.h directiv.h iflag.h insns.h insnsi.h \ + nasm.h nasmlib.h opflags.h pptok.h preproc.h quote.h regs.h stdscan.h \ + tables.h tokens.h strfunc.$(O): strfunc.c compiler.h directiv.h insnsi.h nasm.h nasmlib.h \ opflags.h pptok.h preproc.h regs.h tables.h sync.$(O): sync.c compiler.h nasmlib.h sync.h -tokhash.$(O): tokhash.c compiler.h directiv.h hashtbl.h insns.h insnsi.h \ - nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h tokens.h +tokhash.$(O): tokhash.c compiler.h directiv.h hashtbl.h iflag.h insns.h \ + insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h \ + tokens.h ver.$(O): ver.c compiler.h directiv.h insnsi.h nasm.h nasmlib.h opflags.h \ pptok.h preproc.h regs.h tables.h version.h diff --git a/Mkfiles/netware.mak b/Mkfiles/netware.mak index 8615431..1a888c9 100644 --- a/Mkfiles/netware.mak +++ b/Mkfiles/netware.mak @@ -129,15 +129,15 @@ $(OBJDIR)/version.mak: $(PROOT)/version $(PROOT)/version.pl $(OBJDIR) # @path-separator: "" # @continuation: "\" #-- Everything below is generated by mkdep.pl - do not edit --# -assemble.o: assemble.c assemble.h compiler.h config.h directiv.h insns.h \ - insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h \ - tokens.h +assemble.o: assemble.c assemble.h compiler.h config.h directiv.h iflag.h \ + insns.h insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h \ + tables.h tokens.h crc64.o: crc64.c compiler.h config.h nasmlib.h directiv.o: directiv.c compiler.h config.h directiv.h hashtbl.h insnsi.h \ nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h -disasm.o: disasm.c compiler.h config.h directiv.h disasm.h insns.h insnsi.h \ - nasm.h nasmlib.h opflags.h pptok.h preproc.h regdis.h regs.h sync.h \ - tables.h tokens.h +disasm.o: disasm.c compiler.h config.h directiv.h disasm.h iflag.h insns.h \ + insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h regdis.h regs.h \ + sync.h tables.h tokens.h eval.o: eval.c compiler.h config.h directiv.h eval.h float.h insnsi.h \ labels.h nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h exprlib.o: exprlib.c compiler.h config.h directiv.h insnsi.h nasm.h \ @@ -146,13 +146,14 @@ float.o: float.c compiler.h config.h directiv.h float.h insnsi.h nasm.h \ nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h hashtbl.o: hashtbl.c compiler.h config.h directiv.h hashtbl.h insnsi.h \ nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h +iflag.o: iflag.c compiler.h config.h iflag.h ilog2.o: ilog2.c compiler.h config.h nasmlib.h -insnsa.o: insnsa.c compiler.h config.h directiv.h insns.h insnsi.h nasm.h \ - nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h tokens.h -insnsb.o: insnsb.c compiler.h config.h directiv.h insns.h insnsi.h nasm.h \ - nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h tokens.h -insnsd.o: insnsd.c compiler.h config.h directiv.h insns.h insnsi.h nasm.h \ - nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h tokens.h +insnsa.o: insnsa.c compiler.h config.h directiv.h iflag.h insns.h insnsi.h \ + nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h tokens.h +insnsb.o: insnsb.c compiler.h config.h directiv.h iflag.h insns.h insnsi.h \ + nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h tokens.h +insnsd.o: insnsd.c compiler.h config.h directiv.h iflag.h insns.h insnsi.h \ + nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h tokens.h insnsn.o: insnsn.c compiler.h config.h insnsi.h tables.h labels.o: labels.c compiler.h config.h directiv.h hashtbl.h insnsi.h nasm.h \ nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h @@ -164,11 +165,12 @@ listing.o: listing.c compiler.h config.h directiv.h insnsi.h listing.h \ macros.o: macros.c compiler.h config.h directiv.h hashtbl.h insnsi.h nasm.h \ nasmlib.h opflags.h outform.h pptok.h preproc.h regs.h tables.h nasm.o: nasm.c assemble.h compiler.h config.h directiv.h eval.h float.h \ - insns.h insnsi.h labels.h listing.h nasm.h nasmlib.h opflags.h outform.h \ - parser.h pptok.h preproc.h raa.h regs.h saa.h stdscan.h tables.h tokens.h -nasmlib.o: nasmlib.c compiler.h config.h directiv.h insns.h insnsi.h nasm.h \ - nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h tokens.h -ndisasm.o: ndisasm.c compiler.h config.h directiv.h disasm.h insns.h \ + iflag.h insns.h insnsi.h labels.h listing.h nasm.h nasmlib.h opflags.h \ + outform.h parser.h pptok.h preproc.h raa.h regs.h saa.h stdscan.h tables.h \ + tokens.h +nasmlib.o: nasmlib.c compiler.h config.h directiv.h iflag.h insns.h insnsi.h \ + nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h tokens.h +ndisasm.o: ndisasm.c compiler.h config.h directiv.h disasm.h iflag.h insns.h \ insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h sync.h \ tables.h tokens.h nulldbg.o: nulldbg.c compiler.h config.h directiv.h insnsi.h nasm.h \ @@ -219,9 +221,9 @@ outobj.o: outobj.c compiler.h config.h directiv.h eval.h insnsi.h nasm.h \ outrdf2.o: outrdf2.c compiler.h config.h directiv.h insnsi.h nasm.h \ nasmlib.h opflags.h outform.h outlib.h pptok.h preproc.h rdoff.h regs.h \ saa.h tables.h -parser.o: parser.c compiler.h config.h directiv.h eval.h float.h insns.h \ - insnsi.h nasm.h nasmlib.h opflags.h parser.h pptok.h preproc.h regs.h \ - stdscan.h tables.h tokens.h +parser.o: parser.c compiler.h config.h directiv.h eval.h float.h iflag.h \ + insns.h insnsi.h nasm.h nasmlib.h opflags.h parser.h pptok.h preproc.h \ + regs.h stdscan.h tables.h tokens.h pptok.o: pptok.c compiler.h config.h hashtbl.h nasmlib.h pptok.h preproc.h preproc-nop.o: preproc-nop.c compiler.h config.h directiv.h insnsi.h nasm.h \ nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h @@ -237,14 +239,14 @@ regflags.o: regflags.c compiler.h config.h directiv.h insnsi.h nasm.h \ regs.o: regs.c compiler.h config.h insnsi.h tables.h regvals.o: regvals.c compiler.h config.h insnsi.h tables.h saa.o: saa.c compiler.h config.h nasmlib.h saa.h -stdscan.o: stdscan.c compiler.h config.h directiv.h insns.h insnsi.h nasm.h \ - nasmlib.h opflags.h pptok.h preproc.h quote.h regs.h stdscan.h tables.h \ - tokens.h +stdscan.o: stdscan.c compiler.h config.h directiv.h iflag.h insns.h insnsi.h \ + nasm.h nasmlib.h opflags.h pptok.h preproc.h quote.h regs.h stdscan.h \ + tables.h tokens.h strfunc.o: strfunc.c compiler.h config.h directiv.h insnsi.h nasm.h \ nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h sync.o: sync.c compiler.h config.h nasmlib.h sync.h -tokhash.o: tokhash.c compiler.h config.h directiv.h hashtbl.h insns.h \ - insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h \ - tokens.h +tokhash.o: tokhash.c compiler.h config.h directiv.h hashtbl.h iflag.h \ + insns.h insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h \ + tables.h tokens.h ver.o: ver.c compiler.h config.h directiv.h insnsi.h nasm.h nasmlib.h \ opflags.h pptok.h preproc.h regs.h tables.h version.h diff --git a/Mkfiles/openwcom.mak b/Mkfiles/openwcom.mak index 222163d..9287d61 100644 --- a/Mkfiles/openwcom.mak +++ b/Mkfiles/openwcom.mak @@ -266,15 +266,15 @@ alldeps: perlreq .SYMBOLIC # @exclude: "" # @continuation: "&" #-- Everything below is generated by mkdep.pl - do not edit --# -assemble.$(O): assemble.c assemble.h compiler.h config.h directiv.h insns.h & - insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h & - tokens.h +assemble.$(O): assemble.c assemble.h compiler.h config.h directiv.h iflag.h & + insns.h insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h & + tables.h tokens.h crc64.$(O): crc64.c compiler.h config.h nasmlib.h directiv.$(O): directiv.c compiler.h config.h directiv.h hashtbl.h insnsi.h & nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h -disasm.$(O): disasm.c compiler.h config.h directiv.h disasm.h insns.h & - insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h regdis.h regs.h & - sync.h tables.h tokens.h +disasm.$(O): disasm.c compiler.h config.h directiv.h disasm.h iflag.h & + insns.h insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h regdis.h & + regs.h sync.h tables.h tokens.h eval.$(O): eval.c compiler.h config.h directiv.h eval.h float.h insnsi.h & labels.h nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h exprlib.$(O): exprlib.c compiler.h config.h directiv.h insnsi.h nasm.h & @@ -283,13 +283,17 @@ float.$(O): float.c compiler.h config.h directiv.h float.h insnsi.h nasm.h & nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h hashtbl.$(O): hashtbl.c compiler.h config.h directiv.h hashtbl.h insnsi.h & nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h +iflag.$(O): iflag.c compiler.h config.h iflag.h ilog2.$(O): ilog2.c compiler.h config.h nasmlib.h -insnsa.$(O): insnsa.c compiler.h config.h directiv.h insns.h insnsi.h nasm.h & - nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h tokens.h -insnsb.$(O): insnsb.c compiler.h config.h directiv.h insns.h insnsi.h nasm.h & - nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h tokens.h -insnsd.$(O): insnsd.c compiler.h config.h directiv.h insns.h insnsi.h nasm.h & - nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h tokens.h +insnsa.$(O): insnsa.c compiler.h config.h directiv.h iflag.h insns.h & + insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h & + tokens.h +insnsb.$(O): insnsb.c compiler.h config.h directiv.h iflag.h insns.h & + insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h & + tokens.h +insnsd.$(O): insnsd.c compiler.h config.h directiv.h iflag.h insns.h & + insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h & + tokens.h insnsn.$(O): insnsn.c compiler.h config.h insnsi.h tables.h labels.$(O): labels.c compiler.h config.h directiv.h hashtbl.h insnsi.h & nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h @@ -302,13 +306,14 @@ macros.$(O): macros.c compiler.h config.h directiv.h hashtbl.h insnsi.h & nasm.h nasmlib.h opflags.h output/outform.h pptok.h preproc.h regs.h & tables.h nasm.$(O): nasm.c assemble.h compiler.h config.h directiv.h eval.h float.h & - insns.h insnsi.h labels.h listing.h nasm.h nasmlib.h opflags.h & + iflag.h insns.h insnsi.h labels.h listing.h nasm.h nasmlib.h opflags.h & output/outform.h parser.h pptok.h preproc.h raa.h regs.h saa.h stdscan.h & tables.h tokens.h -nasmlib.$(O): nasmlib.c compiler.h config.h directiv.h insns.h insnsi.h & - nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h tokens.h -ndisasm.$(O): ndisasm.c compiler.h config.h directiv.h disasm.h insns.h & - insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h sync.h & +nasmlib.$(O): nasmlib.c compiler.h config.h directiv.h iflag.h insns.h & + insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h & + tokens.h +ndisasm.$(O): ndisasm.c compiler.h config.h directiv.h disasm.h iflag.h & + insns.h insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h sync.h & tables.h tokens.h output/nulldbg.$(O): output/nulldbg.c compiler.h config.h directiv.h & insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h @@ -366,9 +371,9 @@ output/outobj.$(O): output/outobj.c compiler.h config.h directiv.h eval.h & output/outrdf2.$(O): output/outrdf2.c compiler.h config.h directiv.h & insnsi.h nasm.h nasmlib.h opflags.h output/outform.h output/outlib.h & pptok.h preproc.h rdoff/rdoff.h regs.h saa.h tables.h -parser.$(O): parser.c compiler.h config.h directiv.h eval.h float.h insns.h & - insnsi.h nasm.h nasmlib.h opflags.h parser.h pptok.h preproc.h regs.h & - stdscan.h tables.h tokens.h +parser.$(O): parser.c compiler.h config.h directiv.h eval.h float.h iflag.h & + insns.h insnsi.h nasm.h nasmlib.h opflags.h parser.h pptok.h preproc.h & + regs.h stdscan.h tables.h tokens.h pptok.$(O): pptok.c compiler.h config.h hashtbl.h nasmlib.h pptok.h & preproc.h preproc-nop.$(O): preproc-nop.c compiler.h config.h directiv.h insnsi.h & @@ -385,14 +390,14 @@ regflags.$(O): regflags.c compiler.h config.h directiv.h insnsi.h nasm.h & regs.$(O): regs.c compiler.h config.h insnsi.h tables.h regvals.$(O): regvals.c compiler.h config.h insnsi.h tables.h saa.$(O): saa.c compiler.h config.h nasmlib.h saa.h -stdscan.$(O): stdscan.c compiler.h config.h directiv.h insns.h insnsi.h & - nasm.h nasmlib.h opflags.h pptok.h preproc.h quote.h regs.h stdscan.h & - tables.h tokens.h +stdscan.$(O): stdscan.c compiler.h config.h directiv.h iflag.h insns.h & + insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h quote.h regs.h & + stdscan.h tables.h tokens.h strfunc.$(O): strfunc.c compiler.h config.h directiv.h insnsi.h nasm.h & nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h sync.$(O): sync.c compiler.h config.h nasmlib.h sync.h -tokhash.$(O): tokhash.c compiler.h config.h directiv.h hashtbl.h insns.h & - insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h & - tokens.h +tokhash.$(O): tokhash.c compiler.h config.h directiv.h hashtbl.h iflag.h & + insns.h insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h & + tables.h tokens.h ver.$(O): ver.c compiler.h config.h directiv.h insnsi.h nasm.h nasmlib.h & opflags.h pptok.h preproc.h regs.h tables.h version.h diff --git a/Mkfiles/owlinux.mak b/Mkfiles/owlinux.mak index 04fb90a..d5c84be 100644 --- a/Mkfiles/owlinux.mak +++ b/Mkfiles/owlinux.mak @@ -235,14 +235,15 @@ everything: all doc rdf # @exclude: "config.h" # @continuation: "\" #-- Everything below is generated by mkdep.pl - do not edit --# -assemble.$(O): assemble.c assemble.h compiler.h directiv.h insns.h insnsi.h \ - nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h tokens.h +assemble.$(O): assemble.c assemble.h compiler.h directiv.h iflag.h insns.h \ + insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h \ + tokens.h crc64.$(O): crc64.c compiler.h nasmlib.h directiv.$(O): directiv.c compiler.h directiv.h hashtbl.h insnsi.h nasm.h \ nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h -disasm.$(O): disasm.c compiler.h directiv.h disasm.h insns.h insnsi.h nasm.h \ - nasmlib.h opflags.h pptok.h preproc.h regdis.h regs.h sync.h tables.h \ - tokens.h +disasm.$(O): disasm.c compiler.h directiv.h disasm.h iflag.h insns.h \ + insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h regdis.h regs.h \ + sync.h tables.h tokens.h eval.$(O): eval.c compiler.h directiv.h eval.h float.h insnsi.h labels.h \ nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h exprlib.$(O): exprlib.c compiler.h directiv.h insnsi.h nasm.h nasmlib.h \ @@ -251,12 +252,13 @@ float.$(O): float.c compiler.h directiv.h float.h insnsi.h nasm.h nasmlib.h \ opflags.h pptok.h preproc.h regs.h tables.h hashtbl.$(O): hashtbl.c compiler.h directiv.h hashtbl.h insnsi.h nasm.h \ nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h +iflag.$(O): iflag.c compiler.h iflag.h ilog2.$(O): ilog2.c compiler.h nasmlib.h -insnsa.$(O): insnsa.c compiler.h directiv.h insns.h insnsi.h nasm.h \ +insnsa.$(O): insnsa.c compiler.h directiv.h iflag.h insns.h insnsi.h nasm.h \ nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h tokens.h -insnsb.$(O): insnsb.c compiler.h directiv.h insns.h insnsi.h nasm.h \ +insnsb.$(O): insnsb.c compiler.h directiv.h iflag.h insns.h insnsi.h nasm.h \ nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h tokens.h -insnsd.$(O): insnsd.c compiler.h directiv.h insns.h insnsi.h nasm.h \ +insnsd.$(O): insnsd.c compiler.h directiv.h iflag.h insns.h insnsi.h nasm.h \ nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h tokens.h insnsn.$(O): insnsn.c compiler.h insnsi.h tables.h labels.$(O): labels.c compiler.h directiv.h hashtbl.h insnsi.h nasm.h \ @@ -268,14 +270,15 @@ listing.$(O): listing.c compiler.h directiv.h insnsi.h listing.h nasm.h \ nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h macros.$(O): macros.c compiler.h directiv.h hashtbl.h insnsi.h nasm.h \ nasmlib.h opflags.h output/outform.h pptok.h preproc.h regs.h tables.h -nasm.$(O): nasm.c assemble.h compiler.h directiv.h eval.h float.h insns.h \ - insnsi.h labels.h listing.h nasm.h nasmlib.h opflags.h output/outform.h \ - parser.h pptok.h preproc.h raa.h regs.h saa.h stdscan.h tables.h tokens.h -nasmlib.$(O): nasmlib.c compiler.h directiv.h insns.h insnsi.h nasm.h \ - nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h tokens.h -ndisasm.$(O): ndisasm.c compiler.h directiv.h disasm.h insns.h insnsi.h \ - nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h sync.h tables.h \ - tokens.h +nasm.$(O): nasm.c assemble.h compiler.h directiv.h eval.h float.h iflag.h \ + insns.h insnsi.h labels.h listing.h nasm.h nasmlib.h opflags.h \ + output/outform.h parser.h pptok.h preproc.h raa.h regs.h saa.h stdscan.h \ + tables.h tokens.h +nasmlib.$(O): nasmlib.c compiler.h directiv.h iflag.h insns.h insnsi.h \ + nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h tokens.h +ndisasm.$(O): ndisasm.c compiler.h directiv.h disasm.h iflag.h insns.h \ + insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h sync.h \ + tables.h tokens.h output/nulldbg.$(O): output/nulldbg.c compiler.h directiv.h insnsi.h nasm.h \ nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h output/nullout.$(O): output/nullout.c compiler.h directiv.h insnsi.h nasm.h \ @@ -328,9 +331,9 @@ output/outobj.$(O): output/outobj.c compiler.h directiv.h eval.h insnsi.h \ output/outrdf2.$(O): output/outrdf2.c compiler.h directiv.h insnsi.h nasm.h \ nasmlib.h opflags.h output/outform.h output/outlib.h pptok.h preproc.h \ rdoff/rdoff.h regs.h saa.h tables.h -parser.$(O): parser.c compiler.h directiv.h eval.h float.h insns.h insnsi.h \ - nasm.h nasmlib.h opflags.h parser.h pptok.h preproc.h regs.h stdscan.h \ - tables.h tokens.h +parser.$(O): parser.c compiler.h directiv.h eval.h float.h iflag.h insns.h \ + insnsi.h nasm.h nasmlib.h opflags.h parser.h pptok.h preproc.h regs.h \ + stdscan.h tables.h tokens.h pptok.$(O): pptok.c compiler.h hashtbl.h nasmlib.h pptok.h preproc.h preproc-nop.$(O): preproc-nop.c compiler.h directiv.h insnsi.h nasm.h \ nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h @@ -346,13 +349,14 @@ regflags.$(O): regflags.c compiler.h directiv.h insnsi.h nasm.h nasmlib.h \ regs.$(O): regs.c compiler.h insnsi.h tables.h regvals.$(O): regvals.c compiler.h insnsi.h tables.h saa.$(O): saa.c compiler.h nasmlib.h saa.h -stdscan.$(O): stdscan.c compiler.h directiv.h insns.h insnsi.h nasm.h \ - nasmlib.h opflags.h pptok.h preproc.h quote.h regs.h stdscan.h tables.h \ - tokens.h +stdscan.$(O): stdscan.c compiler.h directiv.h iflag.h insns.h insnsi.h \ + nasm.h nasmlib.h opflags.h pptok.h preproc.h quote.h regs.h stdscan.h \ + tables.h tokens.h strfunc.$(O): strfunc.c compiler.h directiv.h insnsi.h nasm.h nasmlib.h \ opflags.h pptok.h preproc.h regs.h tables.h sync.$(O): sync.c compiler.h nasmlib.h sync.h -tokhash.$(O): tokhash.c compiler.h directiv.h hashtbl.h insns.h insnsi.h \ - nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h tokens.h +tokhash.$(O): tokhash.c compiler.h directiv.h hashtbl.h iflag.h insns.h \ + insnsi.h nasm.h nasmlib.h opflags.h pptok.h preproc.h regs.h tables.h \ + tokens.h ver.$(O): ver.c compiler.h directiv.h insnsi.h nasm.h nasmlib.h opflags.h \ pptok.h preproc.h regs.h tables.h version.h |
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From: nasm-bot f. C. G. <gor...@gm...> - 2013-11-24 09:30:35
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Commit-ID: 970df6f47f3437996e98f581e53cde1f66518a0c Gitweb: http://repo.or.cz/w/nasm.git?a=commitdiff;h=970df6f47f3437996e98f581e53cde1f66518a0c Author: Cyrill Gorcunov <gor...@gm...> AuthorDate: Sat, 9 Nov 2013 22:28:52 +0400 Committer: Cyrill Gorcunov <gor...@gm...> CommitDate: Sun, 24 Nov 2013 13:21:04 +0400 Update .gitignore Signed-off-by: Cyrill Gorcunov <gor...@gm...> --- .gitignore | 2 ++ 1 file changed, 2 insertions(+) diff --git a/.gitignore b/.gitignore index 7762914..82d926f 100644 --- a/.gitignore +++ b/.gitignore @@ -78,3 +78,5 @@ TAGS /version.mak /version.nsh /version.sed +/iflag.c +/iflag.h |
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From: nasm-bot f. C. G. <gor...@gm...> - 2013-11-24 09:30:35
|
Commit-ID: d4e51d3e718a6bcf19151ed90caec1754ea94dec Gitweb: http://repo.or.cz/w/nasm.git?a=commitdiff;h=d4e51d3e718a6bcf19151ed90caec1754ea94dec Author: Cyrill Gorcunov <gor...@gm...> AuthorDate: Sun, 27 Oct 2013 01:20:42 +0400 Committer: Cyrill Gorcunov <gor...@gm...> CommitDate: Sun, 24 Nov 2013 13:20:52 +0400 insns: Introduce insns-flags.pl It been found that 64 bits for instruction flags is too small, so instead we start using indirect addressing scheme to keep instruction flags in bitvectors instead. Using one bitvector per instruction template entry is wastefull (especially if vector grow in future, at moment it's 128 bit length), so we use indirect addressing, which is generated as follow - read instruction flags from insns.dat - flag sequence sorted and joined into one key string - this key string become a hash index - all hash entries are compacted into one array - every instruction template uses array offset instead of flags bitfield Just for info, at moment we have 195 unique flags combination, but since instruction template will use index as unsigned integer, we can use a way more wider combination of flags in future. Signed-off-by: Cyrill Gorcunov <gor...@gm...> --- insns-iflags.pl | 410 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 410 insertions(+) diff --git a/insns-iflags.pl b/insns-iflags.pl new file mode 100644 index 0000000..56da134 --- /dev/null +++ b/insns-iflags.pl @@ -0,0 +1,410 @@ +#!/usr/bin/perl +## -------------------------------------------------------------------------- +## +## Copyright 1996-2013 The NASM Authors - All Rights Reserved +## See the file AUTHORS included with the NASM distribution for +## the specific copyright holders. +## +## Redistribution and use in source and binary forms, with or without +## modification, are permitted provided that the following +## conditions are met: +## +## * Redistributions of source code must retain the above copyright +## notice, this list of conditions and the following disclaimer. +## * Redistributions in binary form must reproduce the above +## copyright notice, this list of conditions and the following +## disclaimer in the documentation and/or other materials provided +## with the distribution. +## +## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND +## CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +## INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +## MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +## DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR +## CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +## SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +## NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +## LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +## HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR +## OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +## EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +## +## -------------------------------------------------------------------------- + +# +# Here we generate instrcution template flags. Note we assume that at moment +# less than 128 bits are used for all flags. If needed it can be extended +# arbitrary, but it'll be needed to extend arrays (they are 4 32 bit elements +# by now). + +# +# The order does matter here. We use some predefined masks to quick test +# for a set of flags, so be carefull moving bits (and +# don't forget to update C code generation then). +my %insns_flag_bit = ( + # + # dword bound, index 0 - specific flags + # + "SM" => [ 0, "Size match"], + "SM2" => [ 1, "Size match first two operands"], + "SB" => [ 2, "Unsized operands can't be non-byte"], + "SW" => [ 3, "Unsized operands can't be non-word"], + "SD" => [ 4, "Unsized operands can't be non-dword"], + "SQ" => [ 5, "Unsized operands can't be non-qword"], + "SO" => [ 6, "Unsized operands can't be non-oword"], + "SY" => [ 7, "Unsized operands can't be non-yword"], + "SZ" => [ 8, "Unsized operands can't be non-zword"], + "SIZE" => [ 9, "Unsized operands must match the bitsize"], + "SX" => [ 10, "Unsized operands not allowed"], + "AR0" => [ 11, "SB, SW, SD applies to argument 0"], + "AR1" => [ 12, "SB, SW, SD applies to argument 1"], + "AR2" => [ 13, "SB, SW, SD applies to argument 2"], + "AR3" => [ 14, "SB, SW, SD applies to argument 3"], + "AR4" => [ 15, "SB, SW, SD applies to argument 4"], + "OPT" => [ 16, "Optimizing assembly only"], + + # + # dword bound, index 1 - instruction filtering flags + # + "PRIV" => [ 32, "Privileged instruction"], + "SMM" => [ 33, "Only valid in SMM"], + "PROT" => [ 34, "Protected mode only"], + "LOCK" => [ 35, "Lockable if operand 0 is memory"], + "NOLONG" => [ 36, "Not available in long mode"], + "LONG" => [ 37, "Long mode"], + "NOHLE" => [ 38, "HLE prefixes forbidden"], + "MIB" => [ 39, "disassemble with split EA"], + "BND" => [ 40, "BND (0xF2) prefix available"], + "UNDOC" => [ 41, "Undocumented"], + "HLE" => [ 42, "HLE prefixed"], + "FPU" => [ 43, "FPU"], + "MMX" => [ 44, "MMX"], + "3DNOW" => [ 45, "3DNow!"], + "SSE" => [ 46, "SSE (KNI, MMX2)"], + "SSE2" => [ 47, "SSE2"], + "SSE3" => [ 48, "SSE3 (PNI)"], + "VMX" => [ 49, "VMX"], + "SSSE3" => [ 50, "SSSE3"], + "SSE4A" => [ 51, "AMD SSE4a"], + "SSE41" => [ 52, "SSE4.1"], + "SSE42" => [ 53, "SSE4.2"], + "SSE5" => [ 54, "SSE5"], + "AVX" => [ 55, "AVX (128b)"], + "AVX2" => [ 56, "AVX2 (256b)"], + "FMA" => [ 57, ""], + "BMI1" => [ 58, ""], + "BMI2" => [ 59, ""], + "TBM" => [ 60, ""], + "RTM" => [ 61, ""], + "INVPCID" => [ 62, ""], + + # + # dword bound, index 2 - instruction filtering flags + # + "AVX512" => [ 64, "AVX-512F (512b)"], + "AVX512CD" => [ 65, "AVX-512 Conflict Detection"], + "AVX512ER" => [ 66, "AVX-512 Exponential and Reciprocal"], + "AVX512PF" => [ 67, "AVX-512 Prefetch"], + "MPX" => [ 68 ,"MPX"], + "SHA" => [ 69 ,"SHA"], + "PREFETCHWT1" => [ 70 ,"PREFETCHWT1"], + + # + # dword bound, index 3 - cpu type flags + # + "8086" => [ 96, "8086"], + "186" => [ 97, "186+"], + "286" => [ 98, "286+"], + "386" => [ 99, "386+"], + "486" => [100, "486+"], + "PENT" => [101, "Pentium"], + "P6" => [102, "P6"], + "KATMAI" => [103, "Katmai"], + "WILLAMETTE" => [104, "Willamette"], + "PRESCOTT" => [105, "Prescott"], + "X86_64" => [106, "x86-64 (long or legacy mode)"], + "NEHALEM" => [107, "Nehalem"], + "WESTMERE" => [108, "Westmere"], + "SANDYBRIDGE" => [109, "Sandy Bridge"], + "FUTURE" => [110, "Future processor (not yet disclosed)"], + "IA64" => [111, "IA64 (in x86 mode)"], + "CYRIX" => [112, "Cyrix-specific"], + "AMD" => [113, "AMD-specific"], +); + +my %insns_flag_hash = (); +my @insns_flag_values = (); + +sub insns_flag_index(@) { + return undef if $_[0] eq "ignore"; + + my @prekey = sort(@_); + my $key = join("", @prekey); + + if (not defined($insns_flag_hash{$key})) { + my @newkey = ([], [], [], []); + my $str = ""; + + for my $i (@prekey) { + die "No key for $i\n" if not defined($insns_flag_bit{$i}); + if ($insns_flag_bit{$i}[0] < 32) { + push @newkey[0], $insns_flag_bit{$i}[0] - 0; + } elsif ($insns_flag_bit{$i}[0] < 64) { + push @newkey[1], $insns_flag_bit{$i}[0] - 32; + } elsif ($insns_flag_bit{$i}[0] < 96) { + push @newkey[2], $insns_flag_bit{$i}[0] - 64; + } elsif ($insns_flag_bit{$i}[0] < 128) { + push @newkey[3], $insns_flag_bit{$i}[0] - 96; + } else { + die "Key value is too big ", $insns_flag_bit{$i}[0], "\n"; + } + } + + for my $j (0 .. $#newkey) { + my $v = ""; + if (scalar(@{$newkey[$j]})) { + $v = join(" | ", map { map { sprintf("(UINT32_C(1) << %d)", $_) } @$_; } $newkey[$j]); + } else { + $v = "0"; + } + $str .= sprintf(".field[%d] = %s, ", $j, $v); + } + + push @insns_flag_values, $str; + $insns_flag_hash{$key} = $#insns_flag_values; + } + + return $insns_flag_hash{$key}; +} + +sub write_iflags() { + print STDERR "Writing iflag.h ...\n"; + + open N, ">iflag.h"; + + print N "/* This file is auto-generated. Don't edit. */\n"; + print N "#ifndef NASM_IFLAG_H__\n"; + print N "#define NASM_IFLAG_H__\n\n"; + + print N "#include <inttypes.h>\n\n"; + print N "#include <string.h>\n\n"; + + print N "#include \"compiler.h\"\n"; + + print N "extern int ilog2_32(uint32_t v);\n\n"; + + print N "/*\n"; + print N " * Instruction template flags. These specify which processor\n"; + print N " * targets the instruction is eligible for, whether it is\n"; + print N " * privileged or undocumented, and also specify extra error\n"; + print N " * checking on the matching of the instruction.\n"; + print N " *\n"; + print N " * IF_SM stands for Size Match: any operand whose size is not\n"; + print N " * explicitly specified by the template is `really' intended to be\n"; + print N " * the same size as the first size-specified operand.\n"; + print N " * Non-specification is tolerated in the input instruction, but\n"; + print N " * _wrong_ specification is not.\n"; + print N " *\n"; + print N " * IF_SM2 invokes Size Match on only the first _two_ operands, for\n"; + print N " * three-operand instructions such as SHLD: it implies that the\n"; + print N " * first two operands must match in size, but that the third is\n"; + print N " * required to be _unspecified_.\n"; + print N " *\n"; + print N " * IF_SB invokes Size Byte: operands with unspecified size in the\n"; + print N " * template are really bytes, and so no non-byte specification in\n"; + print N " * the input instruction will be tolerated. IF_SW similarly invokes\n"; + print N " * Size Word, and IF_SD invokes Size Doubleword.\n"; + print N " *\n"; + print N " * (The default state if neither IF_SM nor IF_SM2 is specified is\n"; + print N " * that any operand with unspecified size in the template is\n"; + print N " * required to have unspecified size in the instruction too...)\n"; + print N " *\n"; + print N " * iflag_t is defined to store these flags.\n"; + print N " */\n"; + foreach my $key (sort { $insns_flag_bit{$a}[0] <=> $insns_flag_bit{$b}[0] } keys(%insns_flag_bit)) { + print N sprintf("#define IF_%-16s (%3d) /* %-64s */\n", + $key, $insns_flag_bit{$key}[0], $insns_flag_bit{$key}[1]); + } + + print N "\n"; + print N "typedef struct {\n"; + print N " uint32_t field[4];\n"; + print N "} iflag_t;\n\n"; + + print N "\n"; + print N sprintf("extern iflag_t insns_flags[%d];\n\n", $#insns_flag_values + 1); + + print N "#define IF_GENBIT(bit) (UINT32_C(1) << (bit))\n\n"; + + print N "static inline unsigned int iflag_test(iflag_t *f,unsigned int bit)\n"; + print N "{\n"; + print N " unsigned int index = bit / 32;\n"; + print N " return f->field[index] & (UINT32_C(1) << (bit - (index * 32)));\n"; + print N "}\n\n"; + + print N "static inline void iflag_set(iflag_t *f, unsigned int bit)\n"; + print N "{\n"; + print N " unsigned int index = bit / 32;\n"; + print N " f->field[index] |= (UINT32_C(1) << (bit - (index * 32)));\n"; + print N "}\n\n"; + + print N "static inline void iflag_clear(iflag_t *f, unsigned int bit)\n"; + print N "{\n"; + print N " unsigned int index = bit / 32;\n"; + print N " f->field[index] &= ~(UINT32_C(1) << (bit - (index * 32)));\n"; + print N "}\n\n"; + + print N "static inline void iflag_clear_all(iflag_t *f)\n"; + print N "{\n"; + print N " memset(f, 0, sizeof(*f));\n"; + print N "}\n\n"; + + print N "static inline void iflag_set_all(iflag_t *f)\n"; + print N "{\n"; + print N " memset(f, 0xff, sizeof(*f));\n"; + print N "}\n\n"; + + print N "static inline int iflag_cmp(iflag_t *a, iflag_t *b)\n"; + print N "{\n"; + print N " unsigned int i;\n"; + print N "\n"; + print N " for (i = 0; i < sizeof(a->field) / sizeof(a->field[0]); i++) {\n"; + print N " if (a->field[i] < b->field[i])\n"; + print N " return -1;\n"; + print N " else if (a->field[i] > b->field[i])\n"; + print N " return 1;\n"; + print N " }\n"; + print N "\n"; + print N " return 0;\n"; + print N "}\n\n"; + + print N "static inline int iflag_cmp_cpu(iflag_t *a, iflag_t *b)\n"; + print N "{\n"; + print N " if (a->field[3] < b->field[3])\n"; + print N " return -1;\n"; + print N " else if (a->field[3] > b->field[3])\n"; + print N " return 1;\n"; + print N " return 0;\n"; + print N "}\n\n"; + + print N "static inline unsigned int iflag_ffs(iflag_t *a)\n"; + print N "{\n"; + print N " unsigned int i;\n"; + print N "\n"; + print N " for (i = 0; i < sizeof(a->field) / sizeof(a->field[0]); i++) {\n"; + print N " if (a->field[i])\n"; + print N " return ilog2_32(a->field[i]) + (i * 32);\n"; + print N " }\n"; + print N "\n"; + print N " return 0;\n"; + print N "}\n\n"; + + print N "#define IF_GEN_HELPER(name, op) \\\n"; + print N " static inline iflag_t iflag_##name(iflag_t *a, iflag_t *b) \\\n"; + print N " { \\\n"; + print N " unsigned int i; \\\n"; + print N " iflag_t res; \\\n"; + print N " \\\n"; + print N " for (i = 0; i < sizeof(a->field) / sizeof(a->field[0]); i++) \\\n"; + print N " res.field[i] = a->field[i] op b->field[i]; \\\n"; + print N " \\\n"; + print N " return res; \\\n"; + print N " }\n"; + print N "\n"; + print N "IF_GEN_HELPER(xor, ^)\n"; + print N "\n\n"; + + print N "/* Use this helper to test instruction template flags */\n"; + print N "#define itemp_has(itemp, bit) iflag_test(&insns_flags[(itemp)->iflag_idx], bit)\n\n"; + + print N "\n"; + print N "/* Maximum processor level at moment */\n"; + print N "#define IF_PLEVEL IF_IA64\n"; + + print N "/* Some helpers which are to work with predefined masks */\n"; + print N "#define IF_SMASK \\\n"; + print N " (IF_GENBIT(IF_SB) |\\\n"; + print N " IF_GENBIT(IF_SW) |\\\n"; + print N " IF_GENBIT(IF_SD) |\\\n"; + print N " IF_GENBIT(IF_SQ) |\\\n"; + print N " IF_GENBIT(IF_SO) |\\\n"; + print N " IF_GENBIT(IF_SY) |\\\n"; + print N " IF_GENBIT(IF_SZ) |\\\n"; + print N " IF_GENBIT(IF_SIZE))\n"; + print N "#define IF_ARMASK \\\n"; + print N " (IF_GENBIT(IF_AR0) |\\\n"; + print N " IF_GENBIT(IF_AR1) |\\\n"; + print N " IF_GENBIT(IF_AR2) |\\\n"; + print N " IF_GENBIT(IF_AR3) |\\\n"; + print N " IF_GENBIT(IF_AR4))\n"; + + print N "\n"; + print N "#define __itemp_smask(idx) (insns_flags[(idx)].field[0] & IF_SMASK)\n"; + print N "#define __itemp_armask(idx) (insns_flags[(idx)].field[0] & IF_ARMASK)\n"; + print N "#define __itemp_arg(idx) ((__itemp_armask(idx) >> IF_AR0) - 1)\n"; + print N "\n"; + print N "#define itemp_smask(itemp) __itemp_smask((itemp)->iflag_idx)\n"; + print N "#define itemp_arg(itemp) __itemp_arg((itemp)->iflag_idx)\n"; + print N "#define itemp_armask(itemp) __itemp_armask((itemp)->iflag_idx)\n"; + + print N "\n"; + print N "static inline int iflag_cmp_cpu_level(iflag_t *a, iflag_t *b)\n"; + print N "{\n"; + print N " iflag_t v1 = *a;\n"; + print N " iflag_t v2 = *b;\n"; + print N "\n"; + print N " iflag_clear(&v1, IF_CYRIX);\n"; + print N " iflag_clear(&v1, IF_AMD);\n"; + print N "\n"; + print N " iflag_clear(&v2, IF_CYRIX);\n"; + print N " iflag_clear(&v2, IF_AMD);\n"; + print N "\n"; + print N " if (v1.field[3] < v2.field[3])\n"; + print N " return -1;\n"; + print N " else if (v1.field[3] > v2.field[3])\n"; + print N " return 1;\n"; + print N "\n"; + print N " return 0;\n"; + print N "}\n"; + + + print N "\n"; + print N "static inline iflag_t __iflag_pfmask(iflag_t *a)\n"; + print N "{\n"; + print N " iflag_t r = (iflag_t) {\n"; + print N " .field[1] = a->field[1],\n"; + print N " .field[2] = a->field[2],\n"; + print N " };\n"; + print N "\n"; + print N " if (iflag_test(a, IF_CYRIX))\n"; + print N " iflag_set(&r, IF_CYRIX);\n"; + print N " if (iflag_test(a, IF_AMD))\n"; + print N " iflag_set(&r, IF_AMD);\n"; + print N "\n"; + print N " return r;\n"; + print N "}\n"; + + print N "\n"; + print N "#define iflag_pfmask(itemp) __iflag_pfmask(&insns_flags[(itemp)->iflag_idx])\n"; + + print N "\n"; + print N "#endif /* NASM_IFLAG_H__ */\n"; + close N; + + print STDERR "Writing iflag.c ...\n"; + + open N, ">iflag.c"; + + print N "/* This file is auto-generated. Don't edit. */\n"; + print N "#include \"iflag.h\"\n\n"; + print N "/* Global flags referenced from instruction templates */\n"; + print N sprintf("iflag_t insns_flags[%d] = {\n", $#insns_flag_values + 1); + foreach my $i (0 .. $#insns_flag_values) { + print N sprintf(" [%8d] = { %s },\n", $i, $insns_flag_values[$i]); + } + print N "};\n\n"; + close N; +} + +1; |
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From: nasm-bot f. J. K. S. <jin...@in...> - 2013-11-22 20:21:29
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Commit-ID: 305f3cee04d1adf3f4e335c5645814f2b67e8a69 Gitweb: http://repo.or.cz/w/nasm.git?a=commitdiff;h=305f3cee04d1adf3f4e335c5645814f2b67e8a69 Author: Jin Kyu Song <jin...@in...> AuthorDate: Thu, 21 Nov 2013 19:40:42 -0800 Committer: Jin Kyu Song <jin...@in...> CommitDate: Fri, 22 Nov 2013 11:59:14 -0800 bnd: Drop bnd prefix for relaxed short jmp instructions Reverted the redundant branch instruction patterns for bnd prefix. And when a relaxed jmp instruction becomes a short (Jb) form, bnd prefix is not needed because it does not initialize bnd registers. So in that case, bnd prefix is silently dropped. BND JMP foo -> drops bnd prefix BND JMP short foo -> shows an explicit error Signed-off-by: Jin Kyu Song <jin...@in...> --- assemble.c | 13 +++++- insns.dat | 139 ++++++++++++++++++-------------------------------------- test/mpx-64.asm | 5 +- test/mpx.asm | 5 +- 4 files changed, 65 insertions(+), 97 deletions(-) diff --git a/assemble.c b/assemble.c index a09b964..0667ef7 100644 --- a/assemble.c +++ b/assemble.c @@ -361,6 +361,7 @@ static bool jmp_match(int32_t segment, int64_t offset, int bits, int64_t isize; const uint8_t *code = temp->code; uint8_t c = code[0]; + bool is_byte; if (((c & ~1) != 0370) || (ins->oprs[0].type & STRICT)) return false; @@ -379,7 +380,14 @@ static bool jmp_match(int32_t segment, int64_t offset, int bits, return false; isize = ins->oprs[0].offset - offset - isize; /* isize is delta */ - return (isize >= -128 && isize <= 127); /* is it byte size? */ + is_byte = (isize >= -128 && isize <= 127); /* is it byte size? */ + + if (is_byte && c == 0371 && ins->prefixes[PPS_REP] == P_BND) { + /* jmp short (opcode eb) cannot be used with bnd prefix. */ + ins->prefixes[PPS_REP] = P_none; + } + + return is_byte; } int64_t assemble(int32_t segment, int64_t offset, int bits, iflags_t cp, @@ -684,6 +692,9 @@ int64_t assemble(int32_t segment, int64_t offset, int bits, iflags_t cp, error(ERR_NONFATAL, "instruction not supported in %d-bit mode", bits); break; + case MERR_BADBND: + error(ERR_NONFATAL, "bnd prefix is not allowed"); + break; default: error(ERR_NONFATAL, "invalid combination of opcode and operands"); diff --git a/insns.dat b/insns.dat index edf7db8..5464f93 100644 --- a/insns.dat +++ b/insns.dat @@ -245,18 +245,18 @@ BTS reg64,reg64 [mr: o64 0f ab /r] X64 BTS rm16,imm [mi: hle o16 0f ba /5 ib,u] 386,SB,LOCK BTS rm32,imm [mi: hle o32 0f ba /5 ib,u] 386,SB,LOCK BTS rm64,imm [mi: hle o64 0f ba /5 ib,u] X64,SB,LOCK -CALL imm [i: odf e8 rel] 8086 -CALL imm|near [i: odf e8 rel] 8086,ND +CALL imm [i: odf e8 rel] 8086,BND +CALL imm|near [i: odf e8 rel] 8086,ND,BND CALL imm|far [i: odf 9a iwd seg] 8086,ND,NOLONG ; Call/jmp near imm/reg/mem is always 64-bit in long mode. -CALL imm16 [i: o16 e8 rel] 8086,NOLONG -CALL imm16|near [i: o16 e8 rel] 8086,ND,NOLONG +CALL imm16 [i: o16 e8 rel] 8086,NOLONG,BND +CALL imm16|near [i: o16 e8 rel] 8086,ND,NOLONG,BND CALL imm16|far [i: o16 9a iwd seg] 8086,ND,NOLONG -CALL imm32 [i: o32 e8 rel] 386,NOLONG -CALL imm32|near [i: o32 e8 rel] 386,ND,NOLONG +CALL imm32 [i: o32 e8 rel] 386,NOLONG,BND +CALL imm32|near [i: o32 e8 rel] 386,ND,NOLONG,BND CALL imm32|far [i: o32 9a iwd seg] 386,ND,NOLONG -CALL imm64 [i: o64nw e8 rel] X64 -CALL imm64|near [i: o64nw e8 rel] X64,ND +CALL imm64 [i: o64nw e8 rel] X64,BND +CALL imm64|near [i: o64nw e8 rel] X64,ND,BND CALL imm:imm [ji: odf 9a iwd iw] 8086,NOLONG CALL imm16:imm [ji: o16 9a iw iw] 8086,NOLONG CALL imm:imm16 [ji: o16 9a iw iw] 8086,NOLONG @@ -267,31 +267,14 @@ CALL mem|far [m: o64 ff /3] X64 CALL mem16|far [m: o16 ff /3] 8086 CALL mem32|far [m: o32 ff /3] 386 CALL mem64|far [m: o64 ff /3] X64 -CALL mem|near [m: odf ff /2] 8086,ND -CALL rm16|near [m: o16 ff /2] 8086,NOLONG,ND -CALL rm32|near [m: o32 ff /2] 386,NOLONG,ND -CALL rm64|near [m: o64nw ff /2] X64,ND -CALL mem [m: odf ff /2] 8086 -CALL rm16 [m: o16 ff /2] 8086,NOLONG -CALL rm32 [m: o32 ff /2] 386,NOLONG -CALL rm64 [m: o64nw ff /2] X64 -; BND + CALL -CALL imm [i: odf e8 rel] 8086,MPX,BND -CALL imm|near [i: odf e8 rel] 8086,ND,MPX,BND -CALL imm16 [i: o16 e8 rel] 8086,NOLONG,MPX,BND -CALL imm16|near [i: o16 e8 rel] 8086,ND,NOLONG,MPX,BND -CALL imm32 [i: o32 e8 rel] 386,NOLONG,MPX,BND -CALL imm32|near [i: o32 e8 rel] 386,ND,NOLONG,MPX,BND -CALL imm64 [i: o64nw e8 rel] X64,MPX,BND -CALL imm64|near [i: o64nw e8 rel] X64,ND,MPX,BND -CALL mem|near [m: odf ff /2] 8086,ND,MPX,BND -CALL rm16|near [m: o16 ff /2] 8086,NOLONG,ND,MPX,BND -CALL rm32|near [m: o32 ff /2] 386,NOLONG,ND,MPX,BND -CALL rm64|near [m: o64nw ff /2] X64,ND,MPX,BND -CALL mem [m: odf ff /2] 8086,MPX,BND -CALL rm16 [m: o16 ff /2] 8086,NOLONG,MPX,BND -CALL rm32 [m: o32 ff /2] 386,NOLONG,MPX,BND -CALL rm64 [m: o64nw ff /2] X64,MPX,BND +CALL mem|near [m: odf ff /2] 8086,ND,BND +CALL rm16|near [m: o16 ff /2] 8086,NOLONG,ND,BND +CALL rm32|near [m: o32 ff /2] 386,NOLONG,ND,BND +CALL rm64|near [m: o64nw ff /2] X64,ND,BND +CALL mem [m: odf ff /2] 8086,BND +CALL rm16 [m: o16 ff /2] 8086,NOLONG,BND +CALL rm32 [m: o32 ff /2] 386,NOLONG,BND +CALL rm64 [m: o64nw ff /2] X64,BND CBW void [ o16 98] 8086 CDQ void [ o32 99] 386 @@ -696,18 +679,18 @@ JECXZ imm [i: a32 e3 rel8] 386 JRCXZ imm [i: a64 e3 rel8] X64 JMP imm|short [i: eb rel8] 8086 JMP imm [i: jmp8 eb rel8] 8086,ND -JMP imm [i: odf e9 rel] 8086 -JMP imm|near [i: odf e9 rel] 8086,ND +JMP imm [i: odf e9 rel] 8086,BND +JMP imm|near [i: odf e9 rel] 8086,ND,BND JMP imm|far [i: odf ea iwd seg] 8086,ND,NOLONG ; Call/jmp near imm/reg/mem is always 64-bit in long mode. -JMP imm16 [i: o16 e9 rel] 8086,NOLONG -JMP imm16|near [i: o16 e9 rel] 8086,ND,NOLONG +JMP imm16 [i: o16 e9 rel] 8086,NOLONG,BND +JMP imm16|near [i: o16 e9 rel] 8086,ND,NOLONG,BND JMP imm16|far [i: o16 ea iwd seg] 8086,ND,NOLONG -JMP imm32 [i: o32 e9 rel] 386,NOLONG -JMP imm32|near [i: o32 e9 rel] 386,ND,NOLONG +JMP imm32 [i: o32 e9 rel] 386,NOLONG,BND +JMP imm32|near [i: o32 e9 rel] 386,ND,NOLONG,BND JMP imm32|far [i: o32 ea iwd seg] 386,ND,NOLONG -JMP imm64 [i: o64nw e9 rel] X64 -JMP imm64|near [i: o64nw e9 rel] X64,ND +JMP imm64 [i: o64nw e9 rel] X64,BND +JMP imm64|near [i: o64nw e9 rel] X64,ND,BND JMP imm:imm [ji: odf ea iwd iw] 8086,NOLONG JMP imm16:imm [ji: o16 ea iw iw] 8086,NOLONG JMP imm:imm16 [ji: o16 ea iw iw] 8086,NOLONG @@ -718,31 +701,14 @@ JMP mem|far [m: o64 ff /5] X64 JMP mem16|far [m: o16 ff /5] 8086 JMP mem32|far [m: o32 ff /5] 386 JMP mem64|far [m: o64 ff /5] X64 -JMP mem|near [m: odf ff /4] 8086,ND -JMP rm16|near [m: o16 ff /4] 8086,NOLONG,ND -JMP rm32|near [m: o32 ff /4] 386,NOLONG,ND -JMP rm64|near [m: o64nw ff /4] X64,ND -JMP mem [m: odf ff /4] 8086 -JMP rm16 [m: o16 ff /4] 8086,NOLONG -JMP rm32 [m: o32 ff /4] 386,NOLONG -JMP rm64 [m: o64nw ff /4] X64 -; BND + JMP -JMP imm [i: odf e9 rel] 8086,MPX,BND -JMP imm|near [i: odf e9 rel] 8086,ND,MPX,BND -JMP imm16 [i: o16 e9 rel] 8086,NOLONG,MPX,BND -JMP imm16|near [i: o16 e9 rel] 8086,ND,NOLONG,MPX,BND -JMP imm32 [i: o32 e9 rel] 386,NOLONG,MPX,BND -JMP imm32|near [i: o32 e9 rel] 386,ND,NOLONG,MPX,BND -JMP imm64 [i: o64nw e9 rel] X64,MPX,BND -JMP imm64|near [i: o64nw e9 rel] X64,ND,MPX,BND -JMP mem|near [m: odf ff /4] 8086,ND,MPX,BND -JMP rm16|near [m: o16 ff /4] 8086,NOLONG,ND,MPX,BND -JMP rm32|near [m: o32 ff /4] 386,NOLONG,ND,MPX,BND -JMP rm64|near [m: o64nw ff /4] X64,ND,MPX,BND -JMP mem [m: odf ff /4] 8086,MPX,BND -JMP rm16 [m: o16 ff /4] 8086,NOLONG,MPX,BND -JMP rm32 [m: o32 ff /4] 386,NOLONG,MPX,BND -JMP rm64 [m: o64nw ff /4] X64,MPX,BND +JMP mem|near [m: odf ff /4] 8086,ND,BND +JMP rm16|near [m: o16 ff /4] 8086,NOLONG,ND,BND +JMP rm32|near [m: o32 ff /4] 386,NOLONG,ND,BND +JMP rm64|near [m: o64nw ff /4] X64,ND,BND +JMP mem [m: odf ff /4] 8086,BND +JMP rm16 [m: o16 ff /4] 8086,NOLONG,BND +JMP rm32 [m: o32 ff /4] 386,NOLONG,BND +JMP rm64 [m: o64nw ff /4] X64,BND JMPE imm [i: odf 0f b8 rel] IA64 JMPE imm16 [i: o16 0f b8 rel] IA64 @@ -1149,17 +1115,12 @@ RDMSR void [ 0f 32] PENT,PRIV RDPMC void [ 0f 33] P6 RDTSC void [ 0f 31] PENT RDTSCP void [ 0f 01 f9] X86_64 -RET void [ c3] 8086 -RET imm [i: c2 iw] 8086,SW +RET void [ c3] 8086,BND +RET imm [i: c2 iw] 8086,SW,BND RETF void [ cb] 8086 RETF imm [i: ca iw] 8086,SW -RETN void [ c3] 8086 -RETN imm [i: c2 iw] 8086,SW -; BND + RET -RET void [ c3] 8086,MPX,BND -RET imm [i: c2 iw] 8086,SW,MPX,BND -RETN void [ c3] 8086,MPX,BND -RETN imm [i: c2 iw] 8086,SW,MPX,BND +RETN void [ c3] 8086,BND +RETN imm [i: c2 iw] 8086,SW,BND ROL rm8,unity [m-: d0 /0] 8086 ROL rm8,reg_cl [m-: d2 /0] 8086 @@ -1518,25 +1479,15 @@ CMOVcc reg32,mem [rm: o32 0f 40+c /r] P6,SM CMOVcc reg32,reg32 [rm: o32 0f 40+c /r] P6 CMOVcc reg64,mem [rm: o64 0f 40+c /r] X64,SM CMOVcc reg64,reg64 [rm: o64 0f 40+c /r] X64 -Jcc imm|near [i: odf 0f 80+c rel] 386 -Jcc imm16|near [i: o16 0f 80+c rel] 386,NOLONG -Jcc imm32|near [i: o32 0f 80+c rel] 386,NOLONG -Jcc imm64|near [i: o64nw 0f 80+c rel] X64 -Jcc imm|short [i: 70+c rel8] 8086,ND -Jcc imm [i: jcc8 70+c rel8] 8086,ND -Jcc imm [i: 0f 80+c rel] 386,ND -Jcc imm [i: 71+c jlen e9 rel] 8086,ND -Jcc imm [i: 70+c rel8] 8086 -; BND + Jcc -Jcc imm|near [i: odf 0f 80+c rel] 386,MPX,BND -Jcc imm16|near [i: o16 0f 80+c rel] 386,NOLONG,MPX,BND -Jcc imm32|near [i: o32 0f 80+c rel] 386,NOLONG,MPX,BND -Jcc imm64|near [i: o64nw 0f 80+c rel] X64,MPX,BND -Jcc imm|short [i: 70+c rel8] 8086,ND,MPX,BND -Jcc imm [i: jcc8 70+c rel8] 8086,ND,MPX,BND -Jcc imm [i: 0f 80+c rel] 386,ND,MPX,BND -Jcc imm [i: 71+c jlen e9 rel] 8086,ND,MPX,BND -Jcc imm [i: 70+c rel8] 8086,MPX,BND +Jcc imm|near [i: odf 0f 80+c rel] 386,BND +Jcc imm16|near [i: o16 0f 80+c rel] 386,NOLONG,BND +Jcc imm32|near [i: o32 0f 80+c rel] 386,NOLONG,BND +Jcc imm64|near [i: o64nw 0f 80+c rel] X64,BND +Jcc imm|short [i: 70+c rel8] 8086,ND,BND +Jcc imm [i: jcc8 70+c rel8] 8086,ND,BND +Jcc imm [i: 0f 80+c rel] 386,ND,BND +Jcc imm [i: 71+c jlen e9 rel] 8086,ND,BND +Jcc imm [i: 70+c rel8] 8086,BND SETcc mem [m: 0f 90+c /0] 386,SB SETcc reg8 [m: 0f 90+c /0] 386 diff --git a/test/mpx-64.asm b/test/mpx-64.asm index bc5e7d4..d177622 100644 --- a/test/mpx-64.asm +++ b/test/mpx-64.asm @@ -111,7 +111,10 @@ BITS 64 ; bnd bnd ret bnd call foo - bnd jmp foo + bnd jmp foo ; when it becomes a Jb form - short jmp (eb), + ; bnd prefix is silently dropped + bnd jmp near 0 ; near jmp (opcode e9) +; bnd jmp short 0 ; explicit short jmp (opcode eb) : error bnd jno foo foo: bnd ret diff --git a/test/mpx.asm b/test/mpx.asm index 24ffcc8..1fd5b1d 100644 --- a/test/mpx.asm +++ b/test/mpx.asm @@ -79,7 +79,10 @@ BITS 32 ; bnd bnd ret bnd call foo - bnd jmp foo + bnd jmp foo ; when it becomes a Jb form - short jmp (eb), + ; bnd prefix is silently dropped + bnd jmp near 0 ; near jmp (opcode e9) +; bnd jmp short 0 ; explicit short jmp (opcode eb) : error bnd jno foo foo: bnd ret |
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From: nasm-bot f. J. K. S. <jin...@in...> - 2013-11-21 22:21:41
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Commit-ID: 5f80dace3a2b15ecc07d07d8ce37bac6cb5f1d4c Gitweb: http://repo.or.cz/w/nasm.git?a=commitdiff;h=5f80dace3a2b15ecc07d07d8ce37bac6cb5f1d4c Author: Jin Kyu Song <jin...@in...> AuthorDate: Tue, 19 Nov 2013 18:43:04 -0800 Committer: Jin Kyu Song <jin...@in...> CommitDate: Wed, 20 Nov 2013 11:29:42 -0800 disasm: Add EVEX decorator syntax Broadcasting, opmask, embedded rounding and SAE decorators are not added at proper position. Signed-off-by: Jin Kyu Song <jin...@in...> --- disasm.c | 101 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++------ 1 file changed, 92 insertions(+), 9 deletions(-) diff --git a/disasm.c b/disasm.c index 49c3051..50a49c5 100644 --- a/disasm.c +++ b/disasm.c @@ -266,6 +266,71 @@ static uint8_t get_disp8N(insn *ins) return n; } +static uint32_t append_evex_reg_deco(char *buf, uint32_t num, + decoflags_t deco, uint8_t *evex) +{ + const char * const er_names[] = {"rn-sae", "rd-sae", "ru-sae", "rz-sae"}; + uint32_t num_chars = 0; + + if ((deco & MASK) && (evex[2] & EVEX_P2AAA)) { + enum reg_enum opmasknum = nasm_rd_opmaskreg[evex[2] & EVEX_P2AAA]; + const char * regname = nasm_reg_names[opmasknum - EXPR_REG_START]; + + num_chars += snprintf(buf + num_chars, num - num_chars, + "{%s}", regname); + + if ((deco & Z) && (evex[2] & EVEX_P2Z)) { + num_chars += snprintf(buf + num_chars, num - num_chars, + "{z}"); + } + } + + if (evex[2] & EVEX_P2B) { + if (deco & ER) { + uint8_t er_type = (evex[2] & EVEX_P2LL) >> 5; + num_chars += snprintf(buf + num_chars, num - num_chars, + ",{%s}", er_names[er_type]); + } else if (deco & SAE) { + num_chars += snprintf(buf + num_chars, num - num_chars, + ",{sae}"); + } + } + + return num_chars; +} + +static uint32_t append_evex_mem_deco(char *buf, uint32_t num, opflags_t type, + decoflags_t deco, uint8_t *evex) +{ + uint32_t num_chars = 0; + + if ((evex[2] & EVEX_P2B) && (deco & BRDCAST_MASK)) { + decoflags_t deco_brsize = deco & BRSIZE_MASK; + opflags_t template_opsize = (deco_brsize == BR_BITS32 ? BITS32 : BITS64); + uint8_t br_num = (type & SIZE_MASK) / BITS128 * + BITS64 / template_opsize * 2; + + num_chars += snprintf(buf + num_chars, num - num_chars, + "{1to%d}", br_num); + } + + if ((deco & MASK) && (evex[2] & EVEX_P2AAA)) { + enum reg_enum opmasknum = nasm_rd_opmaskreg[evex[2] & EVEX_P2AAA]; + const char * regname = nasm_reg_names[opmasknum - EXPR_REG_START]; + + num_chars += snprintf(buf + num_chars, num - num_chars, + "{%s}", regname); + + if ((deco & Z) && (evex[2] & EVEX_P2Z)) { + num_chars += snprintf(buf + num_chars, num - num_chars, + "{z}"); + } + } + + + return num_chars; +} + /* * Process an effective address (ModRM) specification. */ @@ -1382,6 +1447,7 @@ int32_t disasm(uint8_t *data, char *output, int outbufsize, int segsize, length += data - origdata; /* fix up for prefixes */ for (i = 0; i < (*p)->operands; i++) { opflags_t t = (*p)->opd[i]; + decoflags_t deco = (*p)->deco[i]; const operand *o = &ins.oprs[i]; int64_t offs; @@ -1418,6 +1484,9 @@ int32_t disasm(uint8_t *data, char *output, int outbufsize, int segsize, slen += snprintf(output + slen, outbufsize - slen, "to "); slen += snprintf(output + slen, outbufsize - slen, "%s", nasm_reg_names[reg-EXPR_REG_START]); + if (is_evex && deco) + slen += append_evex_reg_deco(output + slen, outbufsize - slen, + deco, ins.evex_p); } else if (!(UNITY & ~t)) { output[slen++] = '1'; } else if (t & IMMEDIATE) { @@ -1477,15 +1546,25 @@ int32_t disasm(uint8_t *data, char *output, int outbufsize, int segsize, if (t & BITS80) slen += snprintf(output + slen, outbufsize - slen, "tword "); - if (t & BITS128) - slen += - snprintf(output + slen, outbufsize - slen, "oword "); - if (t & BITS256) - slen += - snprintf(output + slen, outbufsize - slen, "yword "); - if (t & BITS512) - slen += - snprintf(output + slen, outbufsize - slen, "zword "); + if ((ins.evex_p[2] & EVEX_P2B) && (deco & BRDCAST_MASK)) { + /* when broadcasting, each element size should be used */ + if (deco & BR_BITS32) + slen += + snprintf(output + slen, outbufsize - slen, "dword "); + else if (deco & BR_BITS64) + slen += + snprintf(output + slen, outbufsize - slen, "qword "); + } else { + if (t & BITS128) + slen += + snprintf(output + slen, outbufsize - slen, "oword "); + if (t & BITS256) + slen += + snprintf(output + slen, outbufsize - slen, "yword "); + if (t & BITS512) + slen += + snprintf(output + slen, outbufsize - slen, "zword "); + } if (t & FAR) slen += snprintf(output + slen, outbufsize - slen, "far "); if (t & NEAR) @@ -1602,6 +1681,10 @@ int32_t disasm(uint8_t *data, char *output, int outbufsize, int segsize, } output[slen++] = ']'; + + if (is_evex && deco) + slen += append_evex_mem_deco(output + slen, outbufsize - slen, + t, deco, ins.evex_p); } else { slen += snprintf(output + slen, outbufsize - slen, "<operand%d>", |
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From: nasm-bot f. J. K. S. <jin...@in...> - 2013-11-21 22:21:35
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Commit-ID: 9e59ace66c2892ceb84cf02a3cf063ae8871befe Gitweb: http://repo.or.cz/w/nasm.git?a=commitdiff;h=9e59ace66c2892ceb84cf02a3cf063ae8871befe Author: Jin Kyu Song <jin...@in...> AuthorDate: Fri, 8 Nov 2013 17:22:24 -0800 Committer: Jin Kyu Song <jin...@in...> CommitDate: Wed, 20 Nov 2013 11:29:42 -0800 disasm: style cleanup Fix indentation. Signed-off-by: Jin Kyu Song <jin...@in...> --- disasm.c | 1364 +++++++++++++++++++++++++++++++------------------------------- 1 file changed, 682 insertions(+), 682 deletions(-) diff --git a/disasm.c b/disasm.c index 6498610..ff6f263 100644 --- a/disasm.c +++ b/disasm.c @@ -53,34 +53,34 @@ * Flags that go into the `segment' field of `insn' structures * during disassembly. */ -#define SEG_RELATIVE 1 -#define SEG_32BIT 2 -#define SEG_RMREG 4 -#define SEG_DISP8 8 -#define SEG_DISP16 16 -#define SEG_DISP32 32 -#define SEG_NODISP 64 -#define SEG_SIGNED 128 -#define SEG_64BIT 256 +#define SEG_RELATIVE 1 +#define SEG_32BIT 2 +#define SEG_RMREG 4 +#define SEG_DISP8 8 +#define SEG_DISP16 16 +#define SEG_DISP32 32 +#define SEG_NODISP 64 +#define SEG_SIGNED 128 +#define SEG_64BIT 256 /* * Prefix information */ struct prefix_info { - uint8_t osize; /* Operand size */ - uint8_t asize; /* Address size */ - uint8_t osp; /* Operand size prefix present */ - uint8_t asp; /* Address size prefix present */ - uint8_t rep; /* Rep prefix present */ - uint8_t seg; /* Segment override prefix present */ - uint8_t wait; /* WAIT "prefix" present */ - uint8_t lock; /* Lock prefix present */ - uint8_t vex[3]; /* VEX prefix present */ - uint8_t vex_c; /* VEX "class" (VEX, XOP, ...) */ - uint8_t vex_m; /* VEX.M field */ + uint8_t osize; /* Operand size */ + uint8_t asize; /* Address size */ + uint8_t osp; /* Operand size prefix present */ + uint8_t asp; /* Address size prefix present */ + uint8_t rep; /* Rep prefix present */ + uint8_t seg; /* Segment override prefix present */ + uint8_t wait; /* WAIT "prefix" present */ + uint8_t lock; /* Lock prefix present */ + uint8_t vex[3]; /* VEX prefix present */ + uint8_t vex_c; /* VEX "class" (VEX, XOP, ...) */ + uint8_t vex_m; /* VEX.M field */ uint8_t vex_v; - uint8_t vex_lp; /* VEX.LP fields */ - uint32_t rex; /* REX prefix present */ + uint8_t vex_lp; /* VEX.LP fields */ + uint32_t rex; /* REX prefix present */ }; #define getu8(x) (*(uint8_t *)(x)) @@ -142,7 +142,7 @@ static enum reg_enum whichreg(opflags_t regflags, int regval, int rex) }; if (!(regflags & (REGISTER|REGMEM))) - return 0; /* Registers not permissible?! */ + return 0; /* Registers not permissible?! */ regflags |= REGISTER; @@ -155,10 +155,10 @@ static enum reg_enum whichreg(opflags_t regflags, int regval, int rex) return 0; if (!(REG8 & ~regflags)) { - if (rex & (REX_P|REX_NH)) - return nasm_rd_reg8_rex[regval]; - else - return nasm_rd_reg8[regval]; + if (rex & (REX_P|REX_NH)) + return nasm_rd_reg8_rex[regval]; + else + return nasm_rd_reg8[regval]; } if (!(REG16 & ~regflags)) return nasm_rd_reg16[regval]; @@ -173,8 +173,8 @@ static enum reg_enum whichreg(opflags_t regflags, int regval, int rex) if (!(REG_DREG & ~regflags)) return nasm_rd_dreg[regval]; if (!(REG_TREG & ~regflags)) { - if (regval > 7) - return 0; /* TR registers are ill-defined with rex */ + if (regval > 7) + return 0; /* TR registers are ill-defined with rex */ return nasm_rd_treg[regval]; } if (!(FPUREG & ~regflags)) @@ -193,7 +193,7 @@ static enum reg_enum whichreg(opflags_t regflags, int regval, int rex) * Process an effective address (ModRM) specification. */ static uint8_t *do_ea(uint8_t *data, int modrm, int asize, - int segsize, enum ea_type type, + int segsize, enum ea_type type, operand *op, insn *ins) { int mod, rm, scale, index, base; @@ -204,7 +204,7 @@ static uint8_t *do_ea(uint8_t *data, int modrm, int asize, rm = modrm & 07; if (mod != 3 && asize != 16 && rm == 4) - sib = *data++; + sib = *data++; rex = ins->rex; @@ -287,33 +287,33 @@ static uint8_t *do_ea(uint8_t *data, int modrm, int asize, * none, byte or *dword*), while <rm> specifies the base * register. Again, [EBP] is missing, replaced by a pure * disp32 (this time that's mod=0,rm=*5*) in 32-bit mode, - * and RIP-relative addressing in 64-bit mode. - * - * However, rm=4 + * and RIP-relative addressing in 64-bit mode. + * + * However, rm=4 * indicates not a single base register, but instead the * presence of a SIB byte... */ - int a64 = asize == 64; + int a64 = asize == 64; op->indexreg = -1; - if (a64) - op->basereg = nasm_rd_reg64[rm | ((rex & REX_B) ? 8 : 0)]; - else - op->basereg = nasm_rd_reg32[rm | ((rex & REX_B) ? 8 : 0)]; + if (a64) + op->basereg = nasm_rd_reg64[rm | ((rex & REX_B) ? 8 : 0)]; + else + op->basereg = nasm_rd_reg32[rm | ((rex & REX_B) ? 8 : 0)]; if (rm == 5 && mod == 0) { - if (segsize == 64) { - op->eaflags |= EAF_REL; - op->segment |= SEG_RELATIVE; - mod = 2; /* fake disp32 */ - } + if (segsize == 64) { + op->eaflags |= EAF_REL; + op->segment |= SEG_RELATIVE; + mod = 2; /* fake disp32 */ + } - if (asize != 64) - op->disp_size = asize; + if (asize != 64) + op->disp_size = asize; - op->basereg = -1; - mod = 2; /* fake disp32 */ + op->basereg = -1; + mod = 2; /* fake disp32 */ } @@ -324,29 +324,29 @@ static uint8_t *do_ea(uint8_t *data, int modrm, int asize, op->scale = 1 << scale; - if (type == EA_XMMVSIB) - op->indexreg = nasm_rd_xmmreg[index | ((rex & REX_X) ? 8 : 0)]; - else if (type == EA_YMMVSIB) - op->indexreg = nasm_rd_ymmreg[index | ((rex & REX_X) ? 8 : 0)]; - else if (type == EA_ZMMVSIB) - op->indexreg = nasm_rd_zmmreg[index | ((rex & REX_X) ? 8 : 0)]; - else if (index == 4 && !(rex & REX_X)) - op->indexreg = -1; /* ESP/RSP cannot be an index */ + if (type == EA_XMMVSIB) + op->indexreg = nasm_rd_xmmreg[index | ((rex & REX_X) ? 8 : 0)]; + else if (type == EA_YMMVSIB) + op->indexreg = nasm_rd_ymmreg[index | ((rex & REX_X) ? 8 : 0)]; + else if (type == EA_ZMMVSIB) + op->indexreg = nasm_rd_zmmreg[index | ((rex & REX_X) ? 8 : 0)]; + else if (index == 4 && !(rex & REX_X)) + op->indexreg = -1; /* ESP/RSP cannot be an index */ else if (a64) - op->indexreg = nasm_rd_reg64[index | ((rex & REX_X) ? 8 : 0)]; - else - op->indexreg = nasm_rd_reg32[index | ((rex & REX_X) ? 8 : 0)]; - - if (base == 5 && mod == 0) { - op->basereg = -1; - mod = 2; /* Fake disp32 */ - } else if (a64) - op->basereg = nasm_rd_reg64[base | ((rex & REX_B) ? 8 : 0)]; - else - op->basereg = nasm_rd_reg32[base | ((rex & REX_B) ? 8 : 0)]; - - if (segsize == 16) - op->disp_size = 32; + op->indexreg = nasm_rd_reg64[index | ((rex & REX_X) ? 8 : 0)]; + else + op->indexreg = nasm_rd_reg32[index | ((rex & REX_X) ? 8 : 0)]; + + if (base == 5 && mod == 0) { + op->basereg = -1; + mod = 2; /* Fake disp32 */ + } else if (a64) + op->basereg = nasm_rd_reg64[base | ((rex & REX_B) ? 8 : 0)]; + else + op->basereg = nasm_rd_reg32[base | ((rex & REX_B) ? 8 : 0)]; + + if (segsize == 16) + op->disp_size = 32; } else if (type != EA_SCALAR) { /* Can't have VSIB without SIB */ return NULL; @@ -359,12 +359,12 @@ static uint8_t *do_ea(uint8_t *data, int modrm, int asize, case 1: op->segment |= SEG_DISP8; op->offset = gets8(data); - data++; + data++; break; case 2: op->segment |= SEG_DISP32; op->offset = gets32(data); - data += 4; + data += 4; break; } return data; @@ -378,7 +378,7 @@ static uint8_t *do_ea(uint8_t *data, int modrm, int asize, #define case4(x) case (x): case (x)+1: case (x)+2: case (x)+3 static int matches(const struct itemplate *t, uint8_t *data, - const struct prefix_info *prefix, int segsize, insn *ins) + const struct prefix_info *prefix, int segsize, insn *ins) { uint8_t *r = (uint8_t *)(t->code); uint8_t *origdata = data; @@ -397,8 +397,8 @@ static int matches(const struct itemplate *t, uint8_t *data, enum ea_type eat = EA_SCALAR; for (i = 0; i < MAX_OPERANDS; i++) { - ins->oprs[i].segment = ins->oprs[i].disp_size = - (segsize == 64 ? SEG_64BIT : segsize == 32 ? SEG_32BIT : 0); + ins->oprs[i].segment = ins->oprs[i].disp_size = + (segsize == 64 ? SEG_64BIT : segsize == 32 ? SEG_32BIT : 0); } ins->condition = -1; ins->rex = prefix->rex; @@ -415,121 +415,121 @@ static int matches(const struct itemplate *t, uint8_t *data, dwait = prefix->wait ? P_WAIT : 0; while ((c = *r++) != 0) { - op1 = (c & 3) + ((opex & 1) << 2); - op2 = ((c >> 3) & 3) + ((opex & 2) << 1); - opx = &ins->oprs[op1]; - opy = &ins->oprs[op2]; - opex = 0; - - switch (c) { - case 01: - case 02: - case 03: - case 04: + op1 = (c & 3) + ((opex & 1) << 2); + op2 = ((c >> 3) & 3) + ((opex & 2) << 1); + opx = &ins->oprs[op1]; + opy = &ins->oprs[op2]; + opex = 0; + + switch (c) { + case 01: + case 02: + case 03: + case 04: while (c--) if (*r++ != *data++) return false; - break; + break; - case 05: - case 06: - case 07: - opex = c; - break; + case 05: + case 06: + case 07: + opex = c; + break; - case4(010): - { + case4(010): + { int t = *r++, d = *data++; if (d < t || d > t + 7) return false; else { opx->basereg = (d-t)+ - (ins->rex & REX_B ? 8 : 0); + (ins->rex & REX_B ? 8 : 0); opx->segment |= SEG_RMREG; } - break; - } + break; + } - case4(0274): + case4(0274): opx->offset = (int8_t)*data++; opx->segment |= SEG_SIGNED; - break; + break; - case4(020): + case4(020): opx->offset = *data++; - break; + break; - case4(024): + case4(024): opx->offset = *data++; - break; + break; - case4(030): + case4(030): opx->offset = getu16(data); - data += 2; - break; - - case4(034): - if (osize == 32) { - opx->offset = getu32(data); - data += 4; - } else { - opx->offset = getu16(data); - data += 2; - } + data += 2; + break; + + case4(034): + if (osize == 32) { + opx->offset = getu32(data); + data += 4; + } else { + opx->offset = getu16(data); + data += 2; + } if (segsize != asize) opx->disp_size = asize; - break; + break; - case4(040): + case4(040): opx->offset = getu32(data); - data += 4; - break; + data += 4; + break; case4(0254): opx->offset = gets32(data); data += 4; break; - case4(044): - switch (asize) { - case 16: - opx->offset = getu16(data); - data += 2; - if (segsize != 16) - opx->disp_size = 16; - break; - case 32: - opx->offset = getu32(data); - data += 4; - if (segsize == 16) - opx->disp_size = 32; - break; - case 64: - opx->offset = getu64(data); - opx->disp_size = 64; - data += 8; - break; - } - break; - - case4(050): + case4(044): + switch (asize) { + case 16: + opx->offset = getu16(data); + data += 2; + if (segsize != 16) + opx->disp_size = 16; + break; + case 32: + opx->offset = getu32(data); + data += 4; + if (segsize == 16) + opx->disp_size = 32; + break; + case 64: + opx->offset = getu64(data); + opx->disp_size = 64; + data += 8; + break; + } + break; + + case4(050): opx->offset = gets8(data++); opx->segment |= SEG_RELATIVE; - break; + break; - case4(054): - opx->offset = getu64(data); - data += 8; - break; + case4(054): + opx->offset = getu64(data); + data += 8; + break; - case4(060): + case4(060): opx->offset = gets16(data); - data += 2; + data += 2; opx->segment |= SEG_RELATIVE; opx->segment &= ~SEG_32BIT; - break; + break; - case4(064): /* rel */ + case4(064): /* rel */ opx->segment |= SEG_RELATIVE; /* In long mode rel is always 32 bits, sign extended. */ if (segsize == 64 || osize == 32) { @@ -545,122 +545,122 @@ static int matches(const struct itemplate *t, uint8_t *data, opx->segment &= ~SEG_32BIT; opx->type = (opx->type & ~SIZE_MASK) | BITS16; } - break; + break; - case4(070): + case4(070): opx->offset = gets32(data); - data += 4; + data += 4; opx->segment |= SEG_32BIT | SEG_RELATIVE; - break; - - case4(0100): - case4(0110): - case4(0120): - case4(0130): - { - int modrm = *data++; + break; + + case4(0100): + case4(0110): + case4(0120): + case4(0130): + { + int modrm = *data++; opx->segment |= SEG_RMREG; data = do_ea(data, modrm, asize, segsize, eat, opy, ins); - if (!data) - return false; + if (!data) + return false; opx->basereg = ((modrm >> 3) & 7) + (ins->rex & REX_R ? 8 : 0); - break; - } - - case 0172: - { - uint8_t ximm = *data++; - c = *r++; - ins->oprs[c >> 3].basereg = (ximm >> 4) & regmask; - ins->oprs[c >> 3].segment |= SEG_RMREG; - ins->oprs[c & 7].offset = ximm & 15; - } - break; - - case 0173: - { - uint8_t ximm = *data++; - c = *r++; - - if ((c ^ ximm) & 15) - return false; - - ins->oprs[c >> 4].basereg = (ximm >> 4) & regmask; - ins->oprs[c >> 4].segment |= SEG_RMREG; - } - break; - - case4(0174): - { - uint8_t ximm = *data++; - - opx->basereg = (ximm >> 4) & regmask; - opx->segment |= SEG_RMREG; - } - break; - - case4(0200): - case4(0204): - case4(0210): - case4(0214): - case4(0220): - case4(0224): - case4(0230): - case4(0234): - { + break; + } + + case 0172: + { + uint8_t ximm = *data++; + c = *r++; + ins->oprs[c >> 3].basereg = (ximm >> 4) & regmask; + ins->oprs[c >> 3].segment |= SEG_RMREG; + ins->oprs[c & 7].offset = ximm & 15; + } + break; + + case 0173: + { + uint8_t ximm = *data++; + c = *r++; + + if ((c ^ ximm) & 15) + return false; + + ins->oprs[c >> 4].basereg = (ximm >> 4) & regmask; + ins->oprs[c >> 4].segment |= SEG_RMREG; + } + break; + + case4(0174): + { + uint8_t ximm = *data++; + + opx->basereg = (ximm >> 4) & regmask; + opx->segment |= SEG_RMREG; + } + break; + + case4(0200): + case4(0204): + case4(0210): + case4(0214): + case4(0220): + case4(0224): + case4(0230): + case4(0234): + { int modrm = *data++; if (((modrm >> 3) & 07) != (c & 07)) return false; /* spare field doesn't match up */ data = do_ea(data, modrm, asize, segsize, eat, opy, ins); - if (!data) - return false; - break; - } - - case4(0260): - case 0270: - { - int vexm = *r++; - int vexwlp = *r++; - - ins->rex |= REX_V; - if ((prefix->rex & (REX_V|REX_P)) != REX_V) - return false; - - if ((vexm & 0x1f) != prefix->vex_m) - return false; - - switch (vexwlp & 060) { - case 000: - if (prefix->rex & REX_W) - return false; - break; - case 020: - if (!(prefix->rex & REX_W)) - return false; - ins->rex &= ~REX_W; - break; - case 040: /* VEX.W is a don't care */ - ins->rex &= ~REX_W; - break; - case 060: - break; - } - - /* The 010 bit of vexwlp is set if VEX.L is ignored */ - if ((vexwlp ^ prefix->vex_lp) & ((vexwlp & 010) ? 03 : 07)) - return false; - - if (c == 0270) { - if (prefix->vex_v != 0) - return false; - } else { - opx->segment |= SEG_RMREG; - opx->basereg = prefix->vex_v; - } - vex_ok = true; - break; - } + if (!data) + return false; + break; + } + + case4(0260): + case 0270: + { + int vexm = *r++; + int vexwlp = *r++; + + ins->rex |= REX_V; + if ((prefix->rex & (REX_V|REX_P)) != REX_V) + return false; + + if ((vexm & 0x1f) != prefix->vex_m) + return false; + + switch (vexwlp & 060) { + case 000: + if (prefix->rex & REX_W) + return false; + break; + case 020: + if (!(prefix->rex & REX_W)) + return false; + ins->rex &= ~REX_W; + break; + case 040: /* VEX.W is a don't care */ + ins->rex &= ~REX_W; + break; + case 060: + break; + } + + /* The 010 bit of vexwlp is set if VEX.L is ignored */ + if ((vexwlp ^ prefix->vex_lp) & ((vexwlp & 010) ? 03 : 07)) + return false; + + if (c == 0270) { + if (prefix->vex_v != 0) + return false; + } else { + opx->segment |= SEG_RMREG; + opx->basereg = prefix->vex_v; + } + vex_ok = true; + break; + } case 0271: if (prefix->rep == 0xF3) @@ -683,180 +683,180 @@ static int matches(const struct itemplate *t, uint8_t *data, } break; - case 0310: + case 0310: if (asize != 16) return false; else a_used = true; - break; + break; - case 0311: + case 0311: if (asize != 32) return false; else a_used = true; - break; + break; - case 0312: + case 0312: if (asize != segsize) return false; else a_used = true; - break; - - case 0313: - if (asize != 64) - return false; - else - a_used = true; - break; - - case 0314: - if (prefix->rex & REX_B) - return false; - break; - - case 0315: - if (prefix->rex & REX_X) - return false; - break; - - case 0316: - if (prefix->rex & REX_R) - return false; - break; - - case 0317: - if (prefix->rex & REX_W) - return false; - break; - - case 0320: + break; + + case 0313: + if (asize != 64) + return false; + else + a_used = true; + break; + + case 0314: + if (prefix->rex & REX_B) + return false; + break; + + case 0315: + if (prefix->rex & REX_X) + return false; + break; + + case 0316: + if (prefix->rex & REX_R) + return false; + break; + + case 0317: + if (prefix->rex & REX_W) + return false; + break; + + case 0320: if (osize != 16) return false; else o_used = true; - break; + break; - case 0321: + case 0321: if (osize != 32) return false; else o_used = true; - break; + break; - case 0322: + case 0322: if (osize != (segsize == 16) ? 16 : 32) return false; else o_used = true; - break; - - case 0323: - ins->rex |= REX_W; /* 64-bit only instruction */ - osize = 64; - o_used = true; - break; - - case 0324: - if (osize != 64) - return false; - o_used = true; - break; - - case 0325: - ins->rex |= REX_NH; - break; - - case 0330: - { + break; + + case 0323: + ins->rex |= REX_W; /* 64-bit only instruction */ + osize = 64; + o_used = true; + break; + + case 0324: + if (osize != 64) + return false; + o_used = true; + break; + + case 0325: + ins->rex |= REX_NH; + break; + + case 0330: + { int t = *r++, d = *data++; if (d < t || d > t + 15) return false; else ins->condition = d - t; - break; - } + break; + } case 0326: if (prefix->rep == 0xF3) return false; break; - case 0331: + case 0331: if (prefix->rep) return false; - break; + break; - case 0332: - if (prefix->rep != 0xF2) - return false; - drep = 0; - break; + case 0332: + if (prefix->rep != 0xF2) + return false; + drep = 0; + break; - case 0333: + case 0333: if (prefix->rep != 0xF3) return false; drep = 0; - break; + break; - case 0334: - if (lock) { - ins->rex |= REX_R; - lock = 0; - } - break; + case 0334: + if (lock) { + ins->rex |= REX_R; + lock = 0; + } + break; - case 0335: + case 0335: if (drep == P_REP) drep = P_REPE; - break; - - case 0336: - case 0337: - break; - - case 0340: - return false; - - case 0341: - if (prefix->wait != 0x9B) - return false; - dwait = 0; - break; - - case 0360: - if (prefix->osp || prefix->rep) - return false; - break; - - case 0361: - if (!prefix->osp || prefix->rep) - return false; - o_used = true; - break; - - case 0364: - if (prefix->osp) - return false; - break; - - case 0365: - if (prefix->asp) - return false; - break; - - case 0366: - if (!prefix->osp) - return false; - o_used = true; - break; - - case 0367: - if (!prefix->asp) - return false; - a_used = true; - break; + break; + + case 0336: + case 0337: + break; + + case 0340: + return false; + + case 0341: + if (prefix->wait != 0x9B) + return false; + dwait = 0; + break; + + case 0360: + if (prefix->osp || prefix->rep) + return false; + break; + + case 0361: + if (!prefix->osp || prefix->rep) + return false; + o_used = true; + break; + + case 0364: + if (prefix->osp) + return false; + break; + + case 0365: + if (prefix->asp) + return false; + break; + + case 0366: + if (!prefix->osp) + return false; + o_used = true; + break; + + case 0367: + if (!prefix->asp) + return false; + a_used = true; + break; case 0370: case 0371: @@ -874,61 +874,61 @@ static int matches(const struct itemplate *t, uint8_t *data, eat = EA_ZMMVSIB; break; - default: - return false; /* Unknown code */ - } + default: + return false; /* Unknown code */ + } } if (!vex_ok && (ins->rex & REX_V)) - return false; + return false; /* REX cannot be combined with VEX */ if ((ins->rex & REX_V) && (prefix->rex & REX_P)) - return false; + return false; /* * Check for unused rep or a/o prefixes. */ for (i = 0; i < t->operands; i++) { - if (ins->oprs[i].segment != SEG_RMREG) - a_used = true; + if (ins->oprs[i].segment != SEG_RMREG) + a_used = true; } if (lock) { - if (ins->prefixes[PPS_LOCK]) - return false; - ins->prefixes[PPS_LOCK] = P_LOCK; + if (ins->prefixes[PPS_LOCK]) + return false; + ins->prefixes[PPS_LOCK] = P_LOCK; } if (drep) { - if (ins->prefixes[PPS_REP]) - return false; + if (ins->prefixes[PPS_REP]) + return false; ins->prefixes[PPS_REP] = drep; } ins->prefixes[PPS_WAIT] = dwait; if (!o_used) { - if (osize != ((segsize == 16) ? 16 : 32)) { - enum prefixes pfx = 0; - - switch (osize) { - case 16: - pfx = P_O16; - break; - case 32: - pfx = P_O32; - break; - case 64: - pfx = P_O64; - break; - } - - if (ins->prefixes[PPS_OSIZE]) - return false; - ins->prefixes[PPS_OSIZE] = pfx; - } + if (osize != ((segsize == 16) ? 16 : 32)) { + enum prefixes pfx = 0; + + switch (osize) { + case 16: + pfx = P_O16; + break; + case 32: + pfx = P_O32; + break; + case 64: + pfx = P_O64; + break; + } + + if (ins->prefixes[PPS_OSIZE]) + return false; + ins->prefixes[PPS_OSIZE] = pfx; + } } if (!a_used && asize != segsize) { - if (ins->prefixes[PPS_ASIZE]) - return false; + if (ins->prefixes[PPS_ASIZE]) + return false; ins->prefixes[PPS_ASIZE] = asize == 16 ? P_A16 : P_A32; } @@ -944,7 +944,7 @@ static const char * const condition_name[16] = { }; int32_t disasm(uint8_t *data, char *output, int outbufsize, int segsize, - int32_t offset, int autosync, iflags_t prefer) + int32_t offset, int autosync, iflags_t prefer) { const struct itemplate * const *p, * const *best_p; const struct disasm_index *ix; @@ -975,138 +975,138 @@ int32_t disasm(uint8_t *data, char *output, int outbufsize, int segsize, end_prefix = false; while (!end_prefix) { - switch (*data) { - case 0xF2: - case 0xF3: + switch (*data) { + case 0xF2: + case 0xF3: prefix.rep = *data++; - break; + break; - case 0x9B: - prefix.wait = *data++; - break; + case 0x9B: + prefix.wait = *data++; + break; - case 0xF0: + case 0xF0: prefix.lock = *data++; - break; - - case 0x2E: - segover = "cs", prefix.seg = *data++; - break; - case 0x36: - segover = "ss", prefix.seg = *data++; - break; - case 0x3E: - segover = "ds", prefix.seg = *data++; - break; - case 0x26: - segover = "es", prefix.seg = *data++; - break; - case 0x64: - segover = "fs", prefix.seg = *data++; - break; - case 0x65: - segover = "gs", prefix.seg = *data++; - break; - - case 0x66: - prefix.osize = (segsize == 16) ? 32 : 16; - prefix.osp = *data++; - break; - case 0x67: - prefix.asize = (segsize == 32) ? 16 : 32; - prefix.asp = *data++; - break; - - case 0xC4: - case 0xC5: - if (segsize == 64 || (data[1] & 0xc0) == 0xc0) { - prefix.vex[0] = *data++; - prefix.vex[1] = *data++; - - prefix.rex = REX_V; - prefix.vex_c = RV_VEX; - - if (prefix.vex[0] == 0xc4) { - prefix.vex[2] = *data++; - prefix.rex |= (~prefix.vex[1] >> 5) & 7; /* REX_RXB */ - prefix.rex |= (prefix.vex[2] >> (7-3)) & REX_W; - prefix.vex_m = prefix.vex[1] & 0x1f; - prefix.vex_v = (~prefix.vex[2] >> 3) & 15; - prefix.vex_lp = prefix.vex[2] & 7; - } else { - prefix.rex |= (~prefix.vex[1] >> (7-2)) & REX_R; - prefix.vex_m = 1; - prefix.vex_v = (~prefix.vex[1] >> 3) & 15; - prefix.vex_lp = prefix.vex[1] & 7; - } - - ix = itable_vex[RV_VEX][prefix.vex_m][prefix.vex_lp & 3]; - } - end_prefix = true; - break; - - case 0x8F: - if ((data[1] & 030) != 0 && - (segsize == 64 || (data[1] & 0xc0) == 0xc0)) { - prefix.vex[0] = *data++; - prefix.vex[1] = *data++; - prefix.vex[2] = *data++; - - prefix.rex = REX_V; - prefix.vex_c = RV_XOP; - - prefix.rex |= (~prefix.vex[1] >> 5) & 7; /* REX_RXB */ - prefix.rex |= (prefix.vex[2] >> (7-3)) & REX_W; - prefix.vex_m = prefix.vex[1] & 0x1f; - prefix.vex_v = (~prefix.vex[2] >> 3) & 15; - prefix.vex_lp = prefix.vex[2] & 7; - - ix = itable_vex[RV_XOP][prefix.vex_m][prefix.vex_lp & 3]; - } - end_prefix = true; - break; - - case REX_P + 0x0: - case REX_P + 0x1: - case REX_P + 0x2: - case REX_P + 0x3: - case REX_P + 0x4: - case REX_P + 0x5: - case REX_P + 0x6: - case REX_P + 0x7: - case REX_P + 0x8: - case REX_P + 0x9: - case REX_P + 0xA: - case REX_P + 0xB: - case REX_P + 0xC: - case REX_P + 0xD: - case REX_P + 0xE: - case REX_P + 0xF: - if (segsize == 64) { - prefix.rex = *data++; - if (prefix.rex & REX_W) - prefix.osize = 64; - } - end_prefix = true; - break; - - default: - end_prefix = true; - break; - } + break; + + case 0x2E: + segover = "cs", prefix.seg = *data++; + break; + case 0x36: + segover = "ss", prefix.seg = *data++; + break; + case 0x3E: + segover = "ds", prefix.seg = *data++; + break; + case 0x26: + segover = "es", prefix.seg = *data++; + break; + case 0x64: + segover = "fs", prefix.seg = *data++; + break; + case 0x65: + segover = "gs", prefix.seg = *data++; + break; + + case 0x66: + prefix.osize = (segsize == 16) ? 32 : 16; + prefix.osp = *data++; + break; + case 0x67: + prefix.asize = (segsize == 32) ? 16 : 32; + prefix.asp = *data++; + break; + + case 0xC4: + case 0xC5: + if (segsize == 64 || (data[1] & 0xc0) == 0xc0) { + prefix.vex[0] = *data++; + prefix.vex[1] = *data++; + + prefix.rex = REX_V; + prefix.vex_c = RV_VEX; + + if (prefix.vex[0] == 0xc4) { + prefix.vex[2] = *data++; + prefix.rex |= (~prefix.vex[1] >> 5) & 7; /* REX_RXB */ + prefix.rex |= (prefix.vex[2] >> (7-3)) & REX_W; + prefix.vex_m = prefix.vex[1] & 0x1f; + prefix.vex_v = (~prefix.vex[2] >> 3) & 15; + prefix.vex_lp = prefix.vex[2] & 7; + } else { + prefix.rex |= (~prefix.vex[1] >> (7-2)) & REX_R; + prefix.vex_m = 1; + prefix.vex_v = (~prefix.vex[1] >> 3) & 15; + prefix.vex_lp = prefix.vex[1] & 7; + } + + ix = itable_vex[RV_VEX][prefix.vex_m][prefix.vex_lp & 3]; + } + end_prefix = true; + break; + + case 0x8F: + if ((data[1] & 030) != 0 && + (segsize == 64 || (data[1] & 0xc0) == 0xc0)) { + prefix.vex[0] = *data++; + prefix.vex[1] = *data++; + prefix.vex[2] = *data++; + + prefix.rex = REX_V; + prefix.vex_c = RV_XOP; + + prefix.rex |= (~prefix.vex[1] >> 5) & 7; /* REX_RXB */ + prefix.rex |= (prefix.vex[2] >> (7-3)) & REX_W; + prefix.vex_m = prefix.vex[1] & 0x1f; + prefix.vex_v = (~prefix.vex[2] >> 3) & 15; + prefix.vex_lp = prefix.vex[2] & 7; + + ix = itable_vex[RV_XOP][prefix.vex_m][prefix.vex_lp & 3]; + } + end_prefix = true; + break; + + case REX_P + 0x0: + case REX_P + 0x1: + case REX_P + 0x2: + case REX_P + 0x3: + case REX_P + 0x4: + case REX_P + 0x5: + case REX_P + 0x6: + case REX_P + 0x7: + case REX_P + 0x8: + case REX_P + 0x9: + case REX_P + 0xA: + case REX_P + 0xB: + case REX_P + 0xC: + case REX_P + 0xD: + case REX_P + 0xE: + case REX_P + 0xF: + if (segsize == 64) { + prefix.rex = *data++; + if (prefix.rex & REX_W) + prefix.osize = 64; + } + end_prefix = true; + break; + + default: + end_prefix = true; + break; + } } - best = -1; /* Worst possible */ + best = -1; /* Worst possible */ best_p = NULL; best_pref = INT_MAX; if (!ix) - return 0; /* No instruction table at all... */ + return 0; /* No instruction table at all... */ dp = data; ix += *dp++; while (ix->n == -1) { - ix = (const struct disasm_index *)ix->p + *dp++; + ix = (const struct disasm_index *)ix->p + *dp++; } p = (const struct itemplate * const *)ix->p; @@ -1115,52 +1115,52 @@ int32_t disasm(uint8_t *data, char *output, int outbufsize, int segsize, works = true; /* * Final check to make sure the types of r/m match up. - * XXX: Need to make sure this is actually correct. + * XXX: Need to make sure this is actually correct. */ for (i = 0; i < (*p)->operands; i++) { if ( - /* If it's a mem-only EA but we have a - register, die. */ - ((tmp_ins.oprs[i].segment & SEG_RMREG) && - is_class(MEMORY, (*p)->opd[i])) || - /* If it's a reg-only EA but we have a memory - ref, die. */ - (!(tmp_ins.oprs[i].segment & SEG_RMREG) && - !(REG_EA & ~(*p)->opd[i]) && - !((*p)->opd[i] & REG_SMASK)) || - /* Register type mismatch (eg FS vs REG_DESS): - die. */ - ((((*p)->opd[i] & (REGISTER | FPUREG)) || - (tmp_ins.oprs[i].segment & SEG_RMREG)) && - !whichreg((*p)->opd[i], - tmp_ins.oprs[i].basereg, tmp_ins.rex)) - ) { + /* If it's a mem-only EA but we have a + register, die. */ + ((tmp_ins.oprs[i].segment & SEG_RMREG) && + is_class(MEMORY, (*p)->opd[i])) || + /* If it's a reg-only EA but we have a memory + ref, die. */ + (!(tmp_ins.oprs[i].segment & SEG_RMREG) && + !(REG_EA & ~(*p)->opd[i]) && + !((*p)->opd[i] & REG_SMASK)) || + /* Register type mismatch (eg FS vs REG_DESS): + die. */ + ((((*p)->opd[i] & (REGISTER | FPUREG)) || + (tmp_ins.oprs[i].segment & SEG_RMREG)) && + !whichreg((*p)->opd[i], + tmp_ins.oprs[i].basereg, tmp_ins.rex)) + ) { works = false; break; } } - /* - * Note: we always prefer instructions which incorporate - * prefixes in the instructions themselves. This is to allow - * e.g. PAUSE to be preferred to REP NOP, and deal with - * MMX/SSE instructions where prefixes are used to select - * between MMX and SSE register sets or outright opcode - * selection. - */ + /* + * Note: we always prefer instructions which incorporate + * prefixes in the instructions themselves. This is to allow + * e.g. PAUSE to be preferred to REP NOP, and deal with + * MMX/SSE instructions where prefixes are used to select + * between MMX and SSE register sets or outright opcode + * selection. + */ if (works) { - int i, nprefix; + int i, nprefix; goodness = ((*p)->flags & IF_PFMASK) ^ prefer; - nprefix = 0; - for (i = 0; i < MAXPREFIX; i++) - if (tmp_ins.prefixes[i]) - nprefix++; + nprefix = 0; + for (i = 0; i < MAXPREFIX; i++) + if (tmp_ins.prefixes[i]) + nprefix++; if (nprefix < best_pref || - (nprefix == best_pref && goodness < best)) { + (nprefix == best_pref && goodness < best)) { /* This is the best one found so far */ best = goodness; best_p = p; - best_pref = nprefix; + best_pref = nprefix; best_length = length; ins = tmp_ins; } @@ -1186,38 +1186,38 @@ int32_t disasm(uint8_t *data, char *output, int outbufsize, int segsize, * be used for that purpose. */ for (i = 0; i < MAXPREFIX; i++) { - const char *prefix = prefix_name(ins.prefixes[i]); - if (prefix) - slen += snprintf(output+slen, outbufsize-slen, "%s ", prefix); + const char *prefix = prefix_name(ins.prefixes[i]); + if (prefix) + slen += snprintf(output+slen, outbufsize-slen, "%s ", prefix); } i = (*p)->opcode; if (i >= FIRST_COND_OPCODE) - slen += snprintf(output + slen, outbufsize - slen, "%s%s", - nasm_insn_names[i], condition_name[ins.condition]); + slen += snprintf(output + slen, outbufsize - slen, "%s%s", + nasm_insn_names[i], condition_name[ins.condition]); else slen += snprintf(output + slen, outbufsize - slen, "%s", - nasm_insn_names[i]); + nasm_insn_names[i]); colon = false; length += data - origdata; /* fix up for prefixes */ for (i = 0; i < (*p)->operands; i++) { - opflags_t t = (*p)->opd[i]; - const operand *o = &ins.oprs[i]; - int64_t offs; + opflags_t t = (*p)->opd[i]; + const operand *o = &ins.oprs[i]; + int64_t offs; output[slen++] = (colon ? ':' : i == 0 ? ' ' : ','); - offs = o->offset; + offs = o->offset; if (o->segment & SEG_RELATIVE) { offs += offset + length; /* * sort out wraparound */ if (!(o->segment & (SEG_32BIT|SEG_64BIT))) - offs &= 0xffff; - else if (segsize != 64) - offs &= 0xffffffff; + offs &= 0xffff; + else if (segsize != 64) + offs &= 0xffffffff; /* * add sync marker, if autosync is on @@ -1232,13 +1232,13 @@ int32_t disasm(uint8_t *data, char *output, int outbufsize, int segsize, colon = false; if ((t & (REGISTER | FPUREG)) || - (o->segment & SEG_RMREG)) { - enum reg_enum reg; + (o->segment & SEG_RMREG)) { + enum reg_enum reg; reg = whichreg(t, o->basereg, ins.rex); if (t & TO) slen += snprintf(output + slen, outbufsize - slen, "to "); slen += snprintf(output + slen, outbufsize - slen, "%s", - nasm_reg_names[reg-EXPR_REG_START]); + nasm_reg_names[reg-EXPR_REG_START]); } else if (!(UNITY & ~t)) { output[slen++] = '1'; } else if (t & IMMEDIATE) { @@ -1270,16 +1270,16 @@ int32_t disasm(uint8_t *data, char *output, int outbufsize, int segsize, } slen += snprintf(output + slen, outbufsize - slen, "0x%"PRIx64"", - offs); + offs); } else if (!(MEM_OFFS & ~t)) { slen += snprintf(output + slen, outbufsize - slen, - "[%s%s%s0x%"PRIx64"]", - (segover ? segover : ""), - (segover ? ":" : ""), - (o->disp_size == 64 ? "qword " : - o->disp_size == 32 ? "dword " : - o->disp_size == 16 ? "word " : ""), offs); + "[%s%s%s0x%"PRIx64"]", + (segover ? segover : ""), + (segover ? ":" : ""), + (o->disp_size == 64 ? "qword " : + o->disp_size == 32 ? "dword " : + o->disp_size == 16 ? "word " : ""), offs); segover = NULL; } else if (is_class(REGMEM, t)) { int started = false; @@ -1315,96 +1315,96 @@ int32_t disasm(uint8_t *data, char *output, int outbufsize, int segsize, output[slen++] = '['; if (o->disp_size) slen += snprintf(output + slen, outbufsize - slen, "%s", - (o->disp_size == 64 ? "qword " : - o->disp_size == 32 ? "dword " : - o->disp_size == 16 ? "word " : - "")); - if (o->eaflags & EAF_REL) - slen += snprintf(output + slen, outbufsize - slen, "rel "); + (o->disp_size == 64 ? "qword " : + o->disp_size == 32 ? "dword " : + o->disp_size == 16 ? "word " : + "")); + if (o->eaflags & EAF_REL) + slen += snprintf(output + slen, outbufsize - slen, "rel "); if (segover) { slen += snprintf(output + slen, outbufsize - slen, "%s:", - segover); + segover); segover = NULL; } if (o->basereg != -1) { slen += snprintf(output + slen, outbufsize - slen, "%s", - nasm_reg_names[(o->basereg-EXPR_REG_START)]); + nasm_reg_names[(o->basereg-EXPR_REG_START)]); started = true; } if (o->indexreg != -1 && !(flags & IF_MIB)) { if (started) output[slen++] = '+'; slen += snprintf(output + slen, outbufsize - slen, "%s", - nasm_reg_names[(o->indexreg-EXPR_REG_START)]); + nasm_reg_names[(o->indexreg-EXPR_REG_START)]); if (o->scale > 1) slen += snprintf(output + slen, outbufsize - slen, "*%d", - o->scale); + o->scale); started = true; } if (o->segment & SEG_DISP8) { - const char *prefix; - uint8_t offset = offs; - if ((int8_t)offset < 0) { - prefix = "-"; - offset = -offset; - } else { - prefix = "+"; - } + const char *prefix; + uint8_t offset = offs; + if ((int8_t)offset < 0) { + prefix = "-"; + offset = -offset; + } else { + prefix = "+"; + } slen += snprintf(output + slen, outbufsize - slen, "%s0x%"PRIx8"", - prefix, offset); + prefix, offset); } else if (o->segment & SEG_DISP16) { - const char *prefix; - uint16_t offset = offs; - if ((int16_t)offset < 0 && started) { - offset = -offset; - prefix = "-"; - } else { - prefix = started ? "+" : ""; - } + const char *prefix; + uint16_t offset = offs; + if ((int16_t)offset < 0 && started) { + offset = -offset; + prefix = "-"; + } else { + prefix = started ? "+" : ""; + } slen += snprintf(output + slen, outbufsize - slen, - "%s0x%"PRIx16"", prefix, offset); + "%s0x%"PRIx16"", prefix, offset); } else if (o->segment & SEG_DISP32) { - if (prefix.asize == 64) { - const char *prefix; - uint64_t offset = (int64_t)(int32_t)offs; - if ((int32_t)offs < 0 && started) { - offset = -offset; - prefix = "-"; - } else { - prefix = started ? "+" : ""; - } - slen += - snprintf(output + slen, outbufsize - slen, - "%s0x%"PRIx64"", prefix, offset); - } else { - const char *prefix; - uint32_t offset = offs; - if ((int32_t) offset < 0 && started) { - offset = -offset; - prefix = "-"; - } else { - prefix = started ? "+" : ""; - } - slen += - snprintf(output + slen, outbufsize - slen, - "%s0x%"PRIx32"", prefix, offset); - } + if (prefix.asize == 64) { + const char *prefix; + uint64_t offset = (int64_t)(int32_t)offs; + if ((int32_t)offs < 0 && started) { + offset = -offset; + prefix = "-"; + } else { + prefix = started ? "+" : ""; + } + slen += + snprintf(output + slen, outbufsize - slen, + "%s0x%"PRIx64"", prefix, offset); + } else { + const char *prefix; + uint32_t offset = offs; + if ((int32_t) offset < 0 && started) { + offset = -offset; + prefix = "-"; + } else { + prefix = started ? "+" : ""; + } + slen += + snprintf(output + slen, outbufsize - slen, + "%s0x%"PRIx32"", prefix, offset); + } } if (o->indexreg != -1 && (flags & IF_MIB)) { output[slen++] = ','; slen += snprintf(output + slen, outbufsize - slen, "%s", - nasm_reg_names[(o->indexreg-EXPR_REG_START)]); + nasm_reg_names[(o->indexreg-EXPR_REG_START)]); if (o->scale > 1) slen += snprintf(output + slen, outbufsize - slen, "*%d", - o->scale); + o->scale); started = true; } @@ -1412,7 +1412,7 @@ int32_t disasm(uint8_t *data, char *output, int outbufsize, int segsize, } else { slen += snprintf(output + slen, outbufsize - slen, "<operand%d>", - i); + i); } } output[slen] = '\0'; @@ -1436,44 +1436,44 @@ int32_t eatbyte(uint8_t *data, char *output, int outbufsize, int segsize) { uint8_t byte = *data; const char *str = NULL; - + switch (byte) { case 0xF2: - str = "repne"; - break; + str = "repne"; + break; case 0xF3: - str = "rep"; - break; + str = "rep"; + break; case 0x9B: - str = "wait"; - break; + str = "wait"; + break; case 0xF0: - str = "lock"; - break; + str = "lock"; + break; case 0x2E: - str = "cs"; - break; + str = "cs"; + break; case 0x36: - str = "ss"; - break; + str = "ss"; + break; case 0x3E: - str = "ss"; - break; + str = "ss"; + break; case 0x26: - str = "es"; - break; + str = "es"; + break; case 0x64: - str = "fs"; - break; + str = "fs"; + break; case 0x65: - str = "gs"; - break; + str = "gs"; + break; case 0x66: - str = (segsize == 16) ? "o32" : "o16"; - break; + str = (segsize == 16) ? "o32" : "o16"; + break; case 0x67: - str = (segsize == 32) ? "a16" : "a32"; - break; + str = (segsize == 32) ? "a16" : "a32"; + break; case REX_P + 0x0: case REX_P + 0x1: case REX_P + 0x2: @@ -1490,23 +1490,23 @@ int32_t eatbyte(uint8_t *data, char *output, int outbufsize, int segsize) case REX_P + 0xD: case REX_P + 0xE: case REX_P + 0xF: - if (segsize == 64) { - snprintf(output, outbufsize, "rex%s%s%s%s%s", - (byte == REX_P) ? "" : ".", - (byte & REX_W) ? "w" : "", - (byte & REX_R) ? "r" : "", - (byte & REX_X) ? "x" : "", - (byte & REX_B) ? "b" : ""); - break; - } - /* else fall through */ + if (segsize == 64) { + snprintf(output, outbufsize, "rex%s%s%s%s%s", + (byte == REX_P) ? "" : ".", + (byte & REX_W) ? "w" : "", + (byte & REX_R) ? "r" : "", + (byte & REX_X) ? "x" : "", + (byte & REX_B) ? "b" : ""); + break; + } + /* else fall through */ default: - snprintf(output, outbufsize, "db 0x%02x", byte); - break; + snprintf(output, outbufsize, "db 0x%02x", byte); + break; } if (str) - snprintf(output, outbufsize, "%s", str); + snprintf(output, outbufsize, "%s", str); return 1; } |
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From: nasm-bot f. J. K. S. <jin...@in...> - 2013-11-21 22:21:35
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Commit-ID: 5f3bfee708deba146302df4bb33d081f496399c0 Gitweb: http://repo.or.cz/w/nasm.git?a=commitdiff;h=5f3bfee708deba146302df4bb33d081f496399c0 Author: Jin Kyu Song <jin...@in...> AuthorDate: Wed, 20 Nov 2013 15:32:52 -0800 Committer: Jin Kyu Song <jin...@in...> CommitDate: Wed, 20 Nov 2013 15:40:55 -0800 disp8: Consolidate a logic to get compressed displacement Consolidated two separate but similar functions in nasm and ndisasm into a commonly linked source code. To encode and decode the compressed displacement (disp8*N) for EVEX, N value should be derived using various conditions. Signed-off-by: Jin Kyu Song <jin...@in...> --- Makefile.in | 4 +- assemble.c | 85 +-------------------------------- disasm.c | 71 +--------------------------- disp8.c | 131 +++++++++++++++++++++++++++++++++++++++++++++++++++ listing.h => disp8.h | 21 +++++---- 5 files changed, 147 insertions(+), 165 deletions(-) diff --git a/Makefile.in b/Makefile.in index d692dd2..bd807f2 100644 --- a/Makefile.in +++ b/Makefile.in @@ -89,10 +89,10 @@ NASM = nasm.$(O) nasmlib.$(O) ver.$(O) \ strfunc.$(O) tokhash.$(O) regvals.$(O) regflags.$(O) \ ilog2.$(O) \ lib/strlcpy.$(O) \ - preproc-nop.$(O) + preproc-nop.$(O) disp8.$(O) NDISASM = ndisasm.$(O) disasm.$(O) sync.$(O) nasmlib.$(O) ver.$(O) \ - insnsd.$(O) insnsb.$(O) insnsn.$(O) regs.$(O) regdis.$(O) + insnsd.$(O) insnsb.$(O) insnsn.$(O) regs.$(O) regdis.$(O) disp8.$(O) #-- End File Lists --# all: nasm$(X) ndisasm$(X) manpages rdf diff --git a/assemble.c b/assemble.c index 00acd20..a09b964 100644 --- a/assemble.c +++ b/assemble.c @@ -180,6 +180,7 @@ #include "assemble.h" #include "insns.h" #include "tables.h" +#include "disp8.h" enum match_result { /* @@ -1197,6 +1198,7 @@ static int64_t calcsize(int32_t segment, int64_t offset, int bits, } else { /* set EVEX.L'L (vector length) */ ins->evex_p[2] |= ((ins->vex_wlp << (5 - 2)) & EVEX_P2LL); + ins->evex_p[1] |= ((ins->vex_wlp << (7 - 4)) & EVEX_P1W); if (opy->decoflags & BRDCAST_MASK) { /* set EVEX.b */ ins->evex_p[2] |= EVEX_P2B; @@ -2293,89 +2295,6 @@ static enum match_result matches(const struct itemplate *itemp, } /* - * Check if offset is a multiple of N with corresponding tuple type - * if Disp8*N is available, compressed displacement is stored in compdisp - */ -static bool is_disp8n(operand *input, insn *ins, int8_t *compdisp) -{ - const uint8_t fv_n[2][2][VLMAX] = {{{16, 32, 64}, {4, 4, 4}}, - {{16, 32, 64}, {8, 8, 8}}}; - const uint8_t hv_n[2][VLMAX] = {{8, 16, 32}, {4, 4, 4}}; - const uint8_t dup_n[VLMAX] = {8, 32, 64}; - - bool evex_b = input->decoflags & BRDCAST_MASK; - enum ttypes tuple = ins->evex_tuple; - /* vex_wlp composed as [wwllpp] */ - enum vectlens vectlen = (ins->vex_wlp & 0x0c) >> 2; - /* wig(=2) is treated as w0(=0) */ - bool evex_w = (ins->vex_wlp & 0x10) >> 4; - int32_t off = input->offset; - uint8_t n = 0; - int32_t disp8; - - switch(tuple) { - case FV: - n = fv_n[evex_w][evex_b][vectlen]; - break; - case HV: - n = hv_n[evex_b][vectlen]; - break; - - case FVM: - /* 16, 32, 64 for VL 128, 256, 512 respectively*/ - n = 1 << (vectlen + 4); - break; - case T1S8: /* N = 1 */ - case T1S16: /* N = 2 */ - n = tuple - T1S8 + 1; - break; - case T1S: - /* N = 4 for 32bit, 8 for 64bit */ - n = evex_w ? 8 : 4; - break; - case T1F32: - case T1F64: - /* N = 4 for 32bit, 8 for 64bit */ - n = (tuple == T1F32 ? 4 : 8); - break; - case T2: - case T4: - case T8: - if (vectlen + 7 <= (evex_w + 5) + (tuple - T2 + 1)) - n = 0; - else - n = 1 << (tuple - T2 + evex_w + 3); - break; - case HVM: - case QVM: - case OVM: - n = 1 << (OVM - tuple + vectlen + 1); - break; - case M128: - n = 16; - break; - case DUP: - n = dup_n[vectlen]; - break; - - default: - break; - } - - if (n && !(off & (n - 1))) { - disp8 = off / n; - /* if it fits in Disp8 */ - if (disp8 >= -128 && disp8 <= 127) { - *compdisp = disp8; - return true; - } - } - - *compdisp = 0; - return false; -} - -/* * Check if ModR/M.mod should/can be 01. * - EAF_BYTEOFFS is set * - offset can fit in a byte when EVEX is not used diff --git a/disasm.c b/disasm.c index 72a0261..9064b65 100644 --- a/disasm.c +++ b/disasm.c @@ -48,6 +48,7 @@ #include "insns.h" #include "tables.h" #include "regdis.h" +#include "disp8.h" /* * Flags that go into the `segment' field of `insn' structures @@ -198,76 +199,6 @@ static enum reg_enum whichreg(opflags_t regflags, int regval, int rex) return 0; } -/* - * Find N value for compressed displacement (disp8 * N) - */ -static uint8_t get_disp8N(insn *ins) -{ - const uint8_t fv_n[2][2][VLMAX] = {{{16, 32, 64}, {4, 4, 4}}, - {{16, 32, 64}, {8, 8, 8}}}; - const uint8_t hv_n[2][VLMAX] = {{8, 16, 32}, {4, 4, 4}}; - const uint8_t dup_n[VLMAX] = {8, 32, 64}; - - bool evex_b = (ins->evex_p[2] & EVEX_P2B) >> 4; - enum ttypes tuple = ins->evex_tuple; - /* vex_wlp composed as [wwllpp] */ - enum vectlens vectlen = (ins->evex_p[2] & EVEX_P2LL) >> 5; - /* wig(=2) is treated as w0(=0) */ - bool evex_w = (ins->evex_p[1] & EVEX_P1W) >> 7; - uint8_t n = 0; - - switch(tuple) { - case FV: - n = fv_n[evex_w][evex_b][vectlen]; - break; - case HV: - n = hv_n[evex_b][vectlen]; - break; - - case FVM: - /* 16, 32, 64 for VL 128, 256, 512 respectively*/ - n = 1 << (vectlen + 4); - break; - case T1S8: /* N = 1 */ - case T1S16: /* N = 2 */ - n = tuple - T1S8 + 1; - break; - case T1S: - /* N = 4 for 32bit, 8 for 64bit */ - n = evex_w ? 8 : 4; - break; - case T1F32: - case T1F64: - /* N = 4 for 32bit, 8 for 64bit */ - n = (tuple == T1F32 ? 4 : 8); - break; - case T2: - case T4: - case T8: - if (vectlen + 7 <= (evex_w + 5) + (tuple - T2 + 1)) - n = 0; - else - n = 1 << (tuple - T2 + evex_w + 3); - break; - case HVM: - case QVM: - case OVM: - n = 1 << (OVM - tuple + vectlen + 1); - break; - case M128: - n = 16; - break; - case DUP: - n = dup_n[vectlen]; - break; - - default: - break; - } - - return n; -} - static uint32_t append_evex_reg_deco(char *buf, uint32_t num, decoflags_t deco, uint8_t *evex) { diff --git a/disp8.c b/disp8.c new file mode 100644 index 0000000..1621022 --- /dev/null +++ b/disp8.c @@ -0,0 +1,131 @@ +/* ----------------------------------------------------------------------- * + * + * Copyright 1996-2013 The NASM Authors - All Rights Reserved + * See the file AUTHORS included with the NASM distribution for + * the specific copyright holders. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following + * conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * ----------------------------------------------------------------------- */ + +/* + * disp8.c : Contains a common logic for EVEX compressed displacement + */ + +#include "disp8.h" + +/* + * Find N value for compressed displacement (disp8 * N) + */ +uint8_t get_disp8N(insn *ins) +{ + const uint8_t fv_n[2][2][VLMAX] = {{{16, 32, 64}, {4, 4, 4}}, + {{16, 32, 64}, {8, 8, 8}}}; + const uint8_t hv_n[2][VLMAX] = {{8, 16, 32}, {4, 4, 4}}; + const uint8_t dup_n[VLMAX] = {8, 32, 64}; + + bool evex_b = (ins->evex_p[2] & EVEX_P2B) >> 4; + enum ttypes tuple = ins->evex_tuple; + enum vectlens vectlen = (ins->evex_p[2] & EVEX_P2LL) >> 5; + bool evex_w = (ins->evex_p[1] & EVEX_P1W) >> 7; + uint8_t n = 0; + + switch(tuple) { + case FV: + n = fv_n[evex_w][evex_b][vectlen]; + break; + case HV: + n = hv_n[evex_b][vectlen]; + break; + + case FVM: + /* 16, 32, 64 for VL 128, 256, 512 respectively*/ + n = 1 << (vectlen + 4); + break; + case T1S8: /* N = 1 */ + case T1S16: /* N = 2 */ + n = tuple - T1S8 + 1; + break; + case T1S: + /* N = 4 for 32bit, 8 for 64bit */ + n = evex_w ? 8 : 4; + break; + case T1F32: + case T1F64: + /* N = 4 for 32bit, 8 for 64bit */ + n = (tuple == T1F32 ? 4 : 8); + break; + case T2: + case T4: + case T8: + if (vectlen + 7 <= (evex_w + 5) + (tuple - T2 + 1)) + n = 0; + else + n = 1 << (tuple - T2 + evex_w + 3); + break; + case HVM: + case QVM: + case OVM: + n = 1 << (OVM - tuple + vectlen + 1); + break; + case M128: + n = 16; + break; + case DUP: + n = dup_n[vectlen]; + break; + + default: + break; + } + + return n; +} + +/* + * Check if offset is a multiple of N with corresponding tuple type + * if Disp8*N is available, compressed displacement is stored in compdisp + */ +bool is_disp8n(operand *input, insn *ins, int8_t *compdisp) +{ + int32_t off = input->offset; + uint8_t n; + int32_t disp8; + + n = get_disp8N(ins); + + if (n && !(off & (n - 1))) { + disp8 = off / n; + /* if it fits in Disp8 */ + if (disp8 >= -128 && disp8 <= 127) { + *compdisp = disp8; + return true; + } + } + + *compdisp = 0; + return false; +} diff --git a/listing.h b/disp8.h similarity index 85% copy from listing.h copy to disp8.h index da2e849..fc18e4f 100644 --- a/listing.h +++ b/disp8.h @@ -1,6 +1,6 @@ /* ----------------------------------------------------------------------- * - * - * Copyright 1996-2009 The NASM Authors - All Rights Reserved + * + * Copyright 1996-2013 The NASM Authors - All Rights Reserved * See the file AUTHORS included with the NASM distribution for * the specific copyright holders. * @@ -14,7 +14,7 @@ * copyright notice, this list of conditions and the following * disclaimer in the documentation and/or other materials provided * with the distribution. - * + * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF @@ -31,14 +31,15 @@ * * ----------------------------------------------------------------------- */ -/* - * listing.h header file for listing.c +/* + * disp8.h header file for disp8.c */ -#ifndef NASM_LISTING_H -#define NASM_LISTING_H +#ifndef NASM_DISP8_H +#define NASM_DISP8_H -extern ListGen nasmlist; -extern int user_nolist; /* fbk - 9/1/00 */ +#include "nasm.h" -#endif +uint8_t get_disp8N(insn *ins); +bool is_disp8n(operand *input, insn *ins, int8_t *compdisp); +#endif /* NASM_DISP8_H */ |
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From: nasm-bot f. J. K. S. <jin...@in...> - 2013-11-21 22:21:35
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Commit-ID: 22b1f082bd2f7b5ce4ccff5e7c89974d72f27191 Gitweb: http://repo.or.cz/w/nasm.git?a=commitdiff;h=22b1f082bd2f7b5ce4ccff5e7c89974d72f27191 Author: Jin Kyu Song <jin...@in...> AuthorDate: Thu, 17 Oct 2013 20:37:26 -0700 Committer: Jin Kyu Song <jin...@in...> CommitDate: Wed, 20 Nov 2013 11:29:42 -0800 AVX512: Update instruction group CPUID bit for vptestnm[dq] changed. vptestnm[dq]: AVX512CD -> AVX512F Signed-off-by: Jin Kyu Song <jin...@in...> --- insns.dat | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/insns.dat b/insns.dat index 4054090..202069f 100644 --- a/insns.dat +++ b/insns.dat @@ -4046,6 +4046,8 @@ VPTERNLOGD zmmreg|mask|z,zmmreg,zmmrm512|b32,imm8 [rvmi:fv: evex. VPTERNLOGQ zmmreg|mask|z,zmmreg,zmmrm512|b64,imm8 [rvmi:fv: evex.nds.512.66.0f3a.w1 25 /r ib ] AVX512,FUTURE VPTESTMD kreg|mask,zmmreg,zmmrm512|b32 [rvm:fv: evex.nds.512.66.0f38.w0 27 /r ] AVX512,FUTURE VPTESTMQ kreg|mask,zmmreg,zmmrm512|b64 [rvm:fv: evex.nds.512.66.0f38.w1 27 /r ] AVX512,FUTURE +VPTESTNMD kreg|mask,zmmreg,zmmrm512|b32 [rvm:fv: evex.nds.512.f3.0f38.w0 27 /r ] AVX512,FUTURE +VPTESTNMQ kreg|mask,zmmreg,zmmrm512|b64 [rvm:fv: evex.nds.512.f3.0f38.w1 27 /r ] AVX512,FUTURE VPUNPCKHDQ zmmreg|mask|z,zmmreg,zmmrm512|b32 [rvm:fv: evex.nds.512.66.0f.w0 6a /r ] AVX512,FUTURE VPUNPCKHQDQ zmmreg|mask|z,zmmreg,zmmrm512|b64 [rvm:fv: evex.nds.512.66.0f.w1 6d /r ] AVX512,FUTURE VPUNPCKLDQ zmmreg|mask|z,zmmreg,zmmrm512|b32 [rvm:fv: evex.nds.512.66.0f.w0 62 /r ] AVX512,FUTURE @@ -4116,8 +4118,6 @@ VPCONFLICTD zmmreg|mask|z,zmmrm512|b32 [rm:fv: evex.512.66.0f VPCONFLICTQ zmmreg|mask|z,zmmrm512|b64 [rm:fv: evex.512.66.0f38.w1 c4 /r ] AVX512CD,FUTURE VPLZCNTD zmmreg|mask|z,zmmrm512|b32 [rm:fv: evex.512.66.0f38.w0 44 /r ] AVX512CD,FUTURE VPLZCNTQ zmmreg|mask|z,zmmrm512|b64 [rm:fv: evex.512.66.0f38.w1 44 /r ] AVX512CD,FUTURE -VPTESTNMD kreg|mask,zmmreg,zmmrm512|b32 [rvm:fv: evex.nds.512.f3.0f38.w0 27 /r ] AVX512CD,FUTURE -VPTESTNMQ kreg|mask,zmmreg,zmmrm512|b64 [rvm:fv: evex.nds.512.f3.0f38.w1 27 /r ] AVX512CD,FUTURE ; AVX-512ER (Exponential and Reciprocal) instructions VEXP2PD zmmreg|mask|z,zmmrm512|b64|sae [rm:fv: evex.512.66.0f38.w1 c8 /r ] AVX512ER,FUTURE VEXP2PS zmmreg|mask|z,zmmrm512|b32|sae [rm:fv: evex.512.66.0f38.w0 c8 /r ] AVX512ER,FUTURE |
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From: nasm-bot f. J. K. S. <jin...@in...> - 2013-11-21 22:21:33
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Commit-ID: 28d5bf811b02b4ffa61b4100df11bc0872ea84bf Gitweb: http://repo.or.cz/w/nasm.git?a=commitdiff;h=28d5bf811b02b4ffa61b4100df11bc0872ea84bf Author: Jin Kyu Song <jin...@in...> AuthorDate: Tue, 19 Nov 2013 18:44:13 -0800 Committer: Jin Kyu Song <jin...@in...> CommitDate: Wed, 20 Nov 2013 11:29:42 -0800 disasm: Add suport for bnd registers MPX uses a new bnd registers and a new mib syntax. Signed-off-by: Jin Kyu Song <jin...@in...> --- disasm.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/disasm.c b/disasm.c index 50a49c5..72a0261 100644 --- a/disasm.c +++ b/disasm.c @@ -192,6 +192,8 @@ static enum reg_enum whichreg(opflags_t regflags, int regval, int rex) return nasm_rd_zmmreg[regval]; if (!(OPMASKREG & ~regflags)) return nasm_rd_opmaskreg[regval]; + if (!(BNDREG & ~regflags)) + return nasm_rd_bndreg[regval]; return 0; } @@ -614,6 +616,11 @@ static int matches(const struct itemplate *t, uint8_t *data, break; } + case4(014): + /* this is an separate index reg position of MIB operand (ICC) */ + /* Disassembler uses NASM's split EA form only */ + break; + case4(0274): opx->offset = (int8_t)*data++; opx->segment |= SEG_SIGNED; |
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From: nasm-bot f. J. K. S. <jin...@in...> - 2013-11-21 22:21:33
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Commit-ID: 6076e8f3354529fbb0cf7be3cff01d9be2c39dbd Gitweb: http://repo.or.cz/w/nasm.git?a=commitdiff;h=6076e8f3354529fbb0cf7be3cff01d9be2c39dbd Author: Jin Kyu Song <jin...@in...> AuthorDate: Fri, 15 Nov 2013 13:20:55 -0800 Committer: Jin Kyu Song <jin...@in...> CommitDate: Wed, 20 Nov 2013 11:29:42 -0800 disasm: Add ZMM vsib ZMM registers can be used for vsib index and the number of registers has been increased to 32. Signed-off-by: Jin Kyu Song <jin...@in...> --- disasm.c | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/disasm.c b/disasm.c index 0559883..49c3051 100644 --- a/disasm.c +++ b/disasm.c @@ -406,18 +406,24 @@ static uint8_t *do_ea(uint8_t *data, int modrm, int asize, if (rm == 4) { /* process SIB */ + uint8_t vsib_hi = 0; scale = (sib >> 6) & 03; index = (sib >> 3) & 07; base = sib & 07; op->scale = 1 << scale; + if (segsize == 64) { + vsib_hi = (rex & REX_X ? 8 : 0) | + (evex[2] & EVEX_P2VP ? 0 : 16); + } + if (type == EA_XMMVSIB) - op->indexreg = nasm_rd_xmmreg[index | ((rex & REX_X) ? 8 : 0)]; + op->indexreg = nasm_rd_xmmreg[index | vsib_hi]; else if (type == EA_YMMVSIB) - op->indexreg = nasm_rd_ymmreg[index | ((rex & REX_X) ? 8 : 0)]; + op->indexreg = nasm_rd_ymmreg[index | vsib_hi]; else if (type == EA_ZMMVSIB) - op->indexreg = nasm_rd_zmmreg[index | ((rex & REX_X) ? 8 : 0)]; + op->indexreg = nasm_rd_zmmreg[index | vsib_hi]; else if (index == 4 && !(rex & REX_X)) op->indexreg = -1; /* ESP/RSP cannot be an index */ else if (a64) @@ -749,7 +755,9 @@ static int matches(const struct itemplate *t, uint8_t *data, return false; if (c == 0250) { - if ((prefix->vex_v != 0) || !(prefix->evex[2] & EVEX_P2VP)) + if ((prefix->vex_v != 0) || + (!(prefix->evex[2] & EVEX_P2VP) && + ((eat < EA_XMMVSIB) || (eat > EA_ZMMVSIB)))) return false; } else { opx->segment |= SEG_RMREG; |
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From: nasm-bot f. J. K. S. <jin...@in...> - 2013-11-21 22:21:32
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Commit-ID: 4a8dc019ef22fc8d12a992d47df9c28ecca5af69 Gitweb: http://repo.or.cz/w/nasm.git?a=commitdiff;h=4a8dc019ef22fc8d12a992d47df9c28ecca5af69 Author: Jin Kyu Song <jin...@in...> AuthorDate: Mon, 11 Nov 2013 11:49:10 -0800 Committer: Jin Kyu Song <jin...@in...> CommitDate: Wed, 20 Nov 2013 11:29:42 -0800 disasm: Add basic AVX512 support Disassembler can translate EVEX prefix, count up to 32 vector registers and recognize new ZMM / opmask registers. Signed-off-by: Jin Kyu Song <jin...@in...> --- disasm.c | 97 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++--- insns.dat | 2 +- nasm.h | 7 ++++- 3 files changed, 100 insertions(+), 6 deletions(-) diff --git a/disasm.c b/disasm.c index ff6f263..dbecde2 100644 --- a/disasm.c +++ b/disasm.c @@ -81,6 +81,7 @@ struct prefix_info { uint8_t vex_v; uint8_t vex_lp; /* VEX.LP fields */ uint32_t rex; /* REX prefix present */ + uint8_t evex[3]; /* EVEX prefix present */ }; #define getu8(x) (*(uint8_t *)(x)) @@ -133,12 +134,14 @@ static enum reg_enum whichreg(opflags_t regflags, int regval, int rex) {FPU0, R_ST0}, {XMM0, R_XMM0}, {YMM0, R_YMM0}, + {ZMM0, R_ZMM0}, {REG_ES, R_ES}, {REG_CS, R_CS}, {REG_SS, R_SS}, {REG_DS, R_DS}, {REG_FS, R_FS}, - {REG_GS, R_GS} + {REG_GS, R_GS}, + {OPMASK0, R_K0}, }; if (!(regflags & (REGISTER|REGMEM))) @@ -151,7 +154,7 @@ static enum reg_enum whichreg(opflags_t regflags, int regval, int rex) return specific_registers[i].reg; /* All the entries below look up regval in an 16-entry array */ - if (regval < 0 || regval > 15) + if (regval < 0 || regval > (rex & REX_EV ? 31 : 15)) return 0; if (!(REG8 & ~regflags)) { @@ -185,6 +188,10 @@ static enum reg_enum whichreg(opflags_t regflags, int regval, int rex) return nasm_rd_xmmreg[regval]; if (!(YMMREG & ~regflags)) return nasm_rd_ymmreg[regval]; + if (!(ZMMREG & ~regflags)) + return nasm_rd_zmmreg[regval]; + if (!(OPMASKREG & ~regflags)) + return nasm_rd_opmaskreg[regval]; return 0; } @@ -198,7 +205,9 @@ static uint8_t *do_ea(uint8_t *data, int modrm, int asize, { int mod, rm, scale, index, base; int rex; + uint8_t *evex; uint8_t sib = 0; + bool is_evex = !!(ins->rex & REX_EV); mod = (modrm >> 6) & 03; rm = modrm & 07; @@ -206,11 +215,15 @@ static uint8_t *do_ea(uint8_t *data, int modrm, int asize, if (mod != 3 && asize != 16 && rm == 4) sib = *data++; - rex = ins->rex; + rex = ins->rex; + evex = ins->evex_p; if (mod == 3) { /* pure register version */ op->basereg = rm+(rex & REX_B ? 8 : 0); op->segment |= SEG_RMREG; + if (is_evex && segsize == 64) { + op->basereg += (evex[0] & EVEX_P0X ? 0 : 16); + } return data; } @@ -564,6 +577,8 @@ static int matches(const struct itemplate *t, uint8_t *data, if (!data) return false; opx->basereg = ((modrm >> 3) & 7) + (ins->rex & REX_R ? 8 : 0); + if ((ins->rex & REX_EV) && (segsize == 64)) + opx->basereg += (ins->evex_p[0] & EVEX_P0RP ? 0 : 16); break; } @@ -617,6 +632,55 @@ static int matches(const struct itemplate *t, uint8_t *data, break; } + case4(0240): + case 0250: + { + uint8_t evexm = *r++; + uint8_t evexwlp = *r++; + ins->evex_tuple = *r++ - 0300; + + ins->rex |= REX_EV; + if ((prefix->rex & (REX_EV|REX_V|REX_P)) != REX_EV) + return false; + + if ((evexm & 0x1f) != prefix->vex_m) + return false; + + switch (evexwlp & 060) { + case 000: + if (prefix->rex & REX_W) + return false; + break; + case 020: + if (!(prefix->rex & REX_W)) + return false; + ins->rex |= REX_W; + break; + case 040: /* VEX.W is a don't care */ + ins->rex &= ~REX_W; + break; + case 060: + break; + } + + /* If EVEX.b is set, EVEX.L'L can be rounding control bits */ + if ((evexwlp ^ prefix->vex_lp) & + ((prefix->evex[2] & EVEX_P2B) ? 0x03 : 0x0f)) + return false; + + if (c == 0250) { + if ((prefix->vex_v != 0) || !(prefix->evex[2] & EVEX_P2VP)) + return false; + } else { + opx->segment |= SEG_RMREG; + opx->basereg = ((~prefix->evex[2] & EVEX_P2VP) << (4 - 3) ) | + prefix->vex_v; + } + vex_ok = true; + memcpy(ins->evex_p, prefix->evex, 3); + break; + } + case4(0260): case 0270: { @@ -879,7 +943,7 @@ static int matches(const struct itemplate *t, uint8_t *data, } } - if (!vex_ok && (ins->rex & REX_V)) + if (!vex_ok && (ins->rex & (REX_V | REX_EV))) return false; /* REX cannot be combined with VEX */ @@ -1045,6 +1109,31 @@ int32_t disasm(uint8_t *data, char *output, int outbufsize, int segsize, end_prefix = true; break; + case 0x62: + { + uint8_t evex_p0 = data[1] & 0x0f; + if (segsize == 64 || + ((evex_p0 >= 0x01) && (evex_p0 <= 0x03))) { + data++; /* 62h EVEX prefix */ + prefix.evex[0] = *data++; + prefix.evex[1] = *data++; + prefix.evex[2] = *data++; + + prefix.rex = REX_EV; + prefix.vex_c = RV_EVEX; + prefix.rex |= (~prefix.evex[0] >> 5) & 7; /* REX_RXB */ + prefix.rex |= (prefix.evex[1] >> (7-3)) & REX_W; + prefix.vex_m = prefix.evex[0] & EVEX_P0MM; + prefix.vex_v = (~prefix.evex[1] & EVEX_P1VVVV) >> 3; + prefix.vex_lp = ((prefix.evex[2] & EVEX_P2LL) >> (5-2)) | + (prefix.evex[1] & EVEX_P1PP); + + ix = itable_vex[prefix.vex_c][prefix.vex_m][prefix.vex_lp & 3]; + } + end_prefix = true; + break; + } + case 0x8F: if ((data[1] & 030) != 0 && (segsize == 64 || (data[1] & 0xc0) == 0xc0)) { diff --git a/insns.dat b/insns.dat index 9435e03..edf7db8 100644 --- a/insns.dat +++ b/insns.dat @@ -3730,8 +3730,8 @@ VEXTRACTI32X4 mem128|mask,zmmreg,imm8 [mri:t4: e VEXTRACTI32X4 xmmreg|mask|z,zmmreg,imm8 [mri: evex.512.66.0f3a.w0 39 /r ib ] AVX512,FUTURE VEXTRACTI64X4 ymmreg|mask|z,zmmreg,imm8 [mri: evex.512.66.0f3a.w1 3b /r ib ] AVX512,FUTURE VEXTRACTI64X4 mem256|mask,zmmreg,imm8 [mri:t4: evex.512.66.0f3a.w1 3b /r ib ] AVX512,FUTURE -VEXTRACTPS rm32,xmmreg,imm8 [mri:t1s: evex.128.66.0f3a.wig 17 /r ib ] AVX512,FUTURE VEXTRACTPS rm64,xmmreg,imm8 [mri:t1s: evex.128.66.0f3a.w1 17 /r ib ] AVX512,FUTURE +VEXTRACTPS rm32,xmmreg,imm8 [mri:t1s: evex.128.66.0f3a.wig 17 /r ib ] AVX512,FUTURE VFIXUPIMMPD zmmreg|mask|z,zmmreg,zmmrm512|b64|sae,imm8 [rvmi:fv: evex.nds.512.66.0f3a.w1 54 /r ib ] AVX512,FUTURE VFIXUPIMMPS zmmreg|mask|z,zmmreg,zmmrm512|b32|sae,imm8 [rvmi:fv: evex.nds.512.66.0f3a.w0 54 /r ib ] AVX512,FUTURE VFIXUPIMMSD xmmreg|mask|z,xmmreg,xmmrm64|sae,imm8 [rvmi:t1s: evex.nds.lig.66.0f3a.w1 55 /r ib ] AVX512,FUTURE diff --git a/nasm.h b/nasm.h index b68a8ba..cb786f8 100644 --- a/nasm.h +++ b/nasm.h @@ -509,8 +509,12 @@ static inline uint8_t get_cond_opcode(enum ccode c) /* * EVEX bit field */ +#define EVEX_P0MM 0x03 /* EVEX P[1:0] : Legacy escape */ #define EVEX_P0RP 0x10 /* EVEX P[4] : High-16 reg */ #define EVEX_P0X 0x40 /* EVEX P[6] : High-16 rm */ +#define EVEX_P1PP 0x03 /* EVEX P[9:8] : Legacy prefix */ +#define EVEX_P1VVVV 0x78 /* EVEX P[14:11] : NDS register */ +#define EVEX_P1W 0x80 /* EVEX P[15] : Osize extension */ #define EVEX_P2AAA 0x07 /* EVEX P[18:16] : Embedded opmask */ #define EVEX_P2VP 0x08 /* EVEX P[19] : High-16 NDS reg */ #define EVEX_P2B 0x10 /* EVEX P[20] : Broadcast / RC / SAE */ @@ -523,7 +527,8 @@ static inline uint8_t get_cond_opcode(enum ccode c) */ enum vex_class { RV_VEX = 0, /* C4/C5 */ - RV_XOP = 1 /* 8F */ + RV_XOP = 1, /* 8F */ + RV_EVEX = 2, /* 62 */ }; /* |
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From: nasm-bot f. J. K. S. <jin...@in...> - 2013-11-21 22:21:32
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Commit-ID: 6b29602bf4dd5392590a6bc4e6cbd90a5c70b486 Gitweb: http://repo.or.cz/w/nasm.git?a=commitdiff;h=6b29602bf4dd5392590a6bc4e6cbd90a5c70b486 Author: Jin Kyu Song <jin...@in...> AuthorDate: Fri, 15 Nov 2013 13:18:32 -0800 Committer: Jin Kyu Song <jin...@in...> CommitDate: Wed, 20 Nov 2013 11:29:42 -0800 disasm: Support EVEX compressed displacement When tuple type is indicated in the bytecode, disp8 is treated as a compressed disp and gets calculated back to disp8*N. Signed-off-by: Jin Kyu Song <jin...@in...> --- disasm.c | 118 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++------ 1 file changed, 107 insertions(+), 11 deletions(-) diff --git a/disasm.c b/disasm.c index dbecde2..0559883 100644 --- a/disasm.c +++ b/disasm.c @@ -197,6 +197,76 @@ static enum reg_enum whichreg(opflags_t regflags, int regval, int rex) } /* + * Find N value for compressed displacement (disp8 * N) + */ +static uint8_t get_disp8N(insn *ins) +{ + const uint8_t fv_n[2][2][VLMAX] = {{{16, 32, 64}, {4, 4, 4}}, + {{16, 32, 64}, {8, 8, 8}}}; + const uint8_t hv_n[2][VLMAX] = {{8, 16, 32}, {4, 4, 4}}; + const uint8_t dup_n[VLMAX] = {8, 32, 64}; + + bool evex_b = (ins->evex_p[2] & EVEX_P2B) >> 4; + enum ttypes tuple = ins->evex_tuple; + /* vex_wlp composed as [wwllpp] */ + enum vectlens vectlen = (ins->evex_p[2] & EVEX_P2LL) >> 5; + /* wig(=2) is treated as w0(=0) */ + bool evex_w = (ins->evex_p[1] & EVEX_P1W) >> 7; + uint8_t n = 0; + + switch(tuple) { + case FV: + n = fv_n[evex_w][evex_b][vectlen]; + break; + case HV: + n = hv_n[evex_b][vectlen]; + break; + + case FVM: + /* 16, 32, 64 for VL 128, 256, 512 respectively*/ + n = 1 << (vectlen + 4); + break; + case T1S8: /* N = 1 */ + case T1S16: /* N = 2 */ + n = tuple - T1S8 + 1; + break; + case T1S: + /* N = 4 for 32bit, 8 for 64bit */ + n = evex_w ? 8 : 4; + break; + case T1F32: + case T1F64: + /* N = 4 for 32bit, 8 for 64bit */ + n = (tuple == T1F32 ? 4 : 8); + break; + case T2: + case T4: + case T8: + if (vectlen + 7 <= (evex_w + 5) + (tuple - T2 + 1)) + n = 0; + else + n = 1 << (tuple - T2 + evex_w + 3); + break; + case HVM: + case QVM: + case OVM: + n = 1 << (OVM - tuple + vectlen + 1); + break; + case M128: + n = 16; + break; + case DUP: + n = dup_n[vectlen]; + break; + + default: + break; + } + + return n; +} + +/* * Process an effective address (ModRM) specification. */ static uint8_t *do_ea(uint8_t *data, int modrm, int asize, @@ -285,7 +355,12 @@ static uint8_t *do_ea(uint8_t *data, int modrm, int asize, break; case 1: op->segment |= SEG_DISP8; - op->offset = (int8_t)*data++; + if (ins->evex_tuple != 0) { + op->offset = gets8(data) * get_disp8N(ins); + } else { + op->offset = gets8(data); + } + data++; break; case 2: op->segment |= SEG_DISP16; @@ -371,7 +446,11 @@ static uint8_t *do_ea(uint8_t *data, int modrm, int asize, break; case 1: op->segment |= SEG_DISP8; - op->offset = gets8(data); + if (ins->evex_tuple != 0) { + op->offset = gets8(data) * get_disp8N(ins); + } else { + op->offset = gets8(data); + } data++; break; case 2: @@ -414,6 +493,7 @@ static int matches(const struct itemplate *t, uint8_t *data, (segsize == 64 ? SEG_64BIT : segsize == 32 ? SEG_32BIT : 0); } ins->condition = -1; + ins->evex_tuple = 0; ins->rex = prefix->rex; memset(ins->prefixes, 0, sizeof ins->prefixes); @@ -1023,6 +1103,7 @@ int32_t disasm(uint8_t *data, char *output, int outbufsize, int segsize, int best_pref; struct prefix_info prefix; bool end_prefix; + bool is_evex; memset(&ins, 0, sizeof ins); @@ -1289,6 +1370,7 @@ int32_t disasm(uint8_t *data, char *output, int outbufsize, int segsize, nasm_insn_names[i]); colon = false; + is_evex = !!(ins.rex & REX_EV); length += data - origdata; /* fix up for prefixes */ for (i = 0; i < (*p)->operands; i++) { opflags_t t = (*p)->opd[i]; @@ -1435,17 +1517,31 @@ int32_t disasm(uint8_t *data, char *output, int outbufsize, int segsize, if (o->segment & SEG_DISP8) { - const char *prefix; - uint8_t offset = offs; - if ((int8_t)offset < 0) { - prefix = "-"; - offset = -offset; + if (is_evex) { + const char *prefix; + uint32_t offset = offs; + if ((int32_t)offset < 0) { + prefix = "-"; + offset = -offset; + } else { + prefix = "+"; + } + slen += + snprintf(output + slen, outbufsize - slen, "%s0x%"PRIx32"", + prefix, offset); } else { - prefix = "+"; + const char *prefix; + uint8_t offset = offs; + if ((int8_t)offset < 0) { + prefix = "-"; + offset = -offset; + } else { + prefix = "+"; + } + slen += + snprintf(output + slen, outbufsize - slen, "%s0x%"PRIx8"", + prefix, offset); } - slen += - snprintf(output + slen, outbufsize - slen, "%s0x%"PRIx8"", - prefix, offset); } else if (o->segment & SEG_DISP16) { const char *prefix; uint16_t offset = offs; |
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From: nasm-bot f. J. K. S. <jin...@in...> - 2013-11-21 22:21:31
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Commit-ID: 25c221258641aec4198e9e46127536676878a4bd Gitweb: http://repo.or.cz/w/nasm.git?a=commitdiff;h=25c221258641aec4198e9e46127536676878a4bd Author: Jin Kyu Song <jin...@in...> AuthorDate: Wed, 30 Oct 2013 03:12:45 -0700 Committer: Jin Kyu Song <jin...@in...> CommitDate: Wed, 20 Nov 2013 11:29:42 -0800 match: Check the number of elements in broadcasting operands The broadcasting decorator {1to##} must describe exactly how many times the memory element is repeated in order to clearly match the correct instruction format. For example, vaddpd zmm30,zmm29,QWORD [rdx+0x3f8]{1to8} ; good vaddpd zmm30,zmm29,QWORD [rdx+0x3f8]{1to16} ; fail qword * 16 = 1024b vaddps zmm30,zmm29,DWORD [rcx]{1to16} ; good vaddps zmm30,zmm29,DWORD [rcx]{1to8} ; fail dword * 8 = 256b Signed-off-by: Jin Kyu Song <jin...@in...> --- assemble.c | 21 ++++++++++++++++++++- nasm.h | 14 ++++++++++++++ parser.c | 3 ++- 3 files changed, 36 insertions(+), 2 deletions(-) diff --git a/assemble.c b/assemble.c index a619575..00acd20 100644 --- a/assemble.c +++ b/assemble.c @@ -189,6 +189,7 @@ enum match_result { MERR_INVALOP, MERR_OPSIZEMISSING, MERR_OPSIZEMISMATCH, + MERR_BRNUMMISMATCH, MERR_BADCPU, MERR_BADMODE, MERR_BADHLE, @@ -671,6 +672,10 @@ int64_t assemble(int32_t segment, int64_t offset, int bits, iflags_t cp, case MERR_OPSIZEMISMATCH: error(ERR_NONFATAL, "mismatch in operand sizes"); break; + case MERR_BRNUMMISMATCH: + error(ERR_NONFATAL, + "mismatch in the number of broadcasting elements"); + break; case MERR_BADCPU: error(ERR_NONFATAL, "no instruction for this cpu level"); break; @@ -2163,6 +2168,7 @@ static enum match_result matches(const struct itemplate *itemp, opflags_t type = instruction->oprs[i].type; decoflags_t deco = instruction->oprs[i].decoflags; bool is_broadcast = deco & BRDCAST_MASK; + uint8_t brcast_num = 0; opflags_t template_opsize, insn_opsize; if (!(type & SIZE_MASK)) @@ -2180,13 +2186,16 @@ static enum match_result matches(const struct itemplate *itemp, if (deco_brsize) { template_opsize = (deco_brsize == BR_BITS32 ? BITS32 : BITS64); + /* calculate the proper number : {1to<brcast_num>} */ + brcast_num = (itemp->opd[i] & SIZE_MASK) / BITS128 * + BITS64 / template_opsize * 2; } else { template_opsize = 0; } } if ((itemp->opd[i] & ~type & ~SIZE_MASK) || - (itemp->deco[i] & deco) != deco) { + (deco & ~itemp->deco[i] & ~BRNUM_MASK)) { return MERR_INVALOP; } else if (template_opsize) { if (template_opsize != insn_opsize) { @@ -2200,6 +2209,16 @@ static enum match_result matches(const struct itemplate *itemp, */ opsizemissing = true; } + } else if (is_broadcast && + (brcast_num != + (8U << ((deco & BRNUM_MASK) >> BRNUM_SHIFT)))) { + /* + * broadcasting opsize matches but the number of repeated memory + * element does not match. + * if 64b double precision float is broadcasted to zmm (512b), + * broadcasting decorator must be {1to8}. + */ + return MERR_BRNUMMISMATCH; } } else if (is_register(instruction->oprs[i].basereg) && nasm_regvals[instruction->oprs[i].basereg] >= 16 && diff --git a/nasm.h b/nasm.h index 34adc69..b68a8ba 100644 --- a/nasm.h +++ b/nasm.h @@ -1048,6 +1048,7 @@ enum decorator_tokens { * .........................1...... static rounding * ........................1....... SAE * ......................11........ broadcast element size + * ....................11.......... number of broadcast elements */ #define OP_GENVAL(val, bits, shift) (((val) & ((UINT64_C(1) << (bits)) - 1)) << (shift)) @@ -1119,6 +1120,19 @@ enum decorator_tokens { #define BR_BITS32 GEN_BRSIZE(0) #define BR_BITS64 GEN_BRSIZE(1) +/* + * Number of broadcasting elements + * + * Bits: 10 - 11 + */ +#define BRNUM_SHIFT (10) +#define BRNUM_BITS (2) +#define BRNUM_MASK OP_GENMASK(BRNUM_BITS, BRNUM_SHIFT) +#define VAL_BRNUM(val) OP_GENVAL(val, BRNUM_BITS, BRNUM_SHIFT) + +#define BR_1TO8 VAL_BRNUM(0) +#define BR_1TO16 VAL_BRNUM(1) + #define MASK OPMASK_MASK /* Opmask (k1 ~ 7) can be used */ #define Z Z_MASK #define B32 (BRDCAST_MASK|BR_BITS32) /* {1to16} : broadcast 32b * 16 to zmm(512b) */ diff --git a/parser.c b/parser.c index 155308f..343f35e 100644 --- a/parser.c +++ b/parser.c @@ -947,7 +947,8 @@ is_expression: * is expected for memory reference operands */ if (tokval.t_flag & TFLAG_BRDCAST) { - brace_flags |= GEN_BRDCAST(0); + brace_flags |= GEN_BRDCAST(0) | + VAL_BRNUM(tokval.t_integer - BRC_1TO8); i = stdscan(NULL, &tokval); } else if (i == TOKEN_OPMASK) { brace_flags |= VAL_OPMASK(nasm_regvals[tokval.t_integer]); |
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From: nasm-bot f. J. K. S. <jin...@in...> - 2013-11-21 22:21:30
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Commit-ID: 945b1b8f36764a159e8890d27f80eef21bd29c14 Gitweb: http://repo.or.cz/w/nasm.git?a=commitdiff;h=945b1b8f36764a159e8890d27f80eef21bd29c14 Author: Jin Kyu Song <jin...@in...> AuthorDate: Fri, 25 Oct 2013 19:29:53 -0700 Committer: Jin Kyu Song <jin...@in...> CommitDate: Wed, 20 Nov 2013 11:29:42 -0800 AVX-512: Add {evex} instruction prefix For instructions that can be encoded either in VEX or EVEX, {evex} forces nasm to encode in EVEX. Signed-off-by: Jin Kyu Song <jin...@in...> --- assemble.c | 7 +++++++ nasm.h | 2 ++ parser.c | 2 ++ tokens.dat | 3 +++ 4 files changed, 14 insertions(+) diff --git a/assemble.c b/assemble.c index e2e24c3..100d131 100644 --- a/assemble.c +++ b/assemble.c @@ -632,6 +632,9 @@ int64_t assemble(int32_t segment, int64_t offset, int bits, iflags_t cp, case P_OSP: c = 0x66; break; + case P_EVEX: + /* EVEX */ + break; case P_none: break; default: @@ -786,6 +789,7 @@ int64_t insn_size(int32_t segment, int64_t offset, int bits, iflags_t cp, break; case P_A64: case P_O64: + case P_EVEX: case P_none: break; default: @@ -2186,6 +2190,9 @@ static enum match_result matches(const struct itemplate *itemp, nasm_regvals[instruction->oprs[i].basereg] >= 16 && !(itemp->flags & IF_AVX512)) { return MERR_ENCMISMATCH; + } else if (instruction->prefixes[PPS_EVEX] && + !(itemp->flags & IF_AVX512)) { + return MERR_ENCMISMATCH; } } diff --git a/nasm.h b/nasm.h index 5ca2aa5..34adc69 100644 --- a/nasm.h +++ b/nasm.h @@ -553,6 +553,7 @@ enum prefixes { /* instruction prefixes */ P_XACQUIRE, P_XRELEASE, P_BND, + P_EVEX, PREFIX_ENUM_LIMIT }; @@ -635,6 +636,7 @@ enum prefix_pos { PPS_SEG, /* Segment override prefix */ PPS_OSIZE, /* Operand size prefix */ PPS_ASIZE, /* Address size prefix */ + PPS_EVEX, /* EVEX prefix */ MAXPREFIX /* Total number of prefix slots */ }; diff --git a/parser.c b/parser.c index e61d0a6..700b4fc 100644 --- a/parser.c +++ b/parser.c @@ -101,6 +101,8 @@ static int prefix_slot(int prefix) case P_A64: case P_ASP: return PPS_ASIZE; + case P_EVEX: + return PPS_EVEX; default: nasm_error(ERR_PANIC, "Invalid value %d passed to prefix_slot()", prefix); return -1; diff --git a/tokens.dat b/tokens.dat index 211eb09..284cf30 100644 --- a/tokens.dat +++ b/tokens.dat @@ -122,3 +122,6 @@ rz-sae % TOKEN_DECORATOR, 0, TFLAG_BRC, BRC_* sae z + +% TOKEN_PREFIX, 0, TFLAG_BRC, P_* +evex |
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From: nasm-bot f. J. K. S. <jin...@in...> - 2013-11-21 22:21:30
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Commit-ID: 7903c07b7753fb02fc3b5ba6211dc566bc25aa7c Gitweb: http://repo.or.cz/w/nasm.git?a=commitdiff;h=7903c07b7753fb02fc3b5ba6211dc566bc25aa7c Author: Jin Kyu Song <jin...@in...> AuthorDate: Wed, 30 Oct 2013 03:00:12 -0700 Committer: Jin Kyu Song <jin...@in...> CommitDate: Wed, 20 Nov 2013 11:29:42 -0800 match: Improve broadcast opsize matching Broadcasting operand size is different from the original operand size because 32b or 64b element is repeated to form a vector. So when matching a broadcasting operand, opsize should be treated differently. The broadcasting element size is specified in the decorator information. Signed-off-by: Jin Kyu Song <jin...@in...> --- assemble.c | 55 +++++++++++++++++++++++++++++++++++-------------------- 1 file changed, 35 insertions(+), 20 deletions(-) diff --git a/assemble.c b/assemble.c index 100d131..a619575 100644 --- a/assemble.c +++ b/assemble.c @@ -2020,10 +2020,13 @@ static enum match_result find_match(const struct itemplate **tempp, if ((xsizeflags[i] & (xsizeflags[i]-1))) goto done; /* No luck */ - if (i == broadcast) + if (i == broadcast) { instruction->oprs[i].decoflags |= xsizeflags[i]; - else + instruction->oprs[i].type |= (xsizeflags[i] == BR_BITS32 ? + BITS32 : BITS64); + } else { instruction->oprs[i].type |= xsizeflags[i]; /* Set the size */ + } } /* Try matching again... */ @@ -2159,32 +2162,44 @@ static enum match_result matches(const struct itemplate *itemp, for (i = 0; i < itemp->operands; i++) { opflags_t type = instruction->oprs[i].type; decoflags_t deco = instruction->oprs[i].decoflags; + bool is_broadcast = deco & BRDCAST_MASK; + opflags_t template_opsize, insn_opsize; + if (!(type & SIZE_MASK)) type |= size[i]; + insn_opsize = type & SIZE_MASK; + if (!is_broadcast) { + template_opsize = itemp->opd[i] & SIZE_MASK; + } else { + decoflags_t deco_brsize = itemp->deco[i] & BRSIZE_MASK; + /* + * when broadcasting, the element size depends on + * the instruction type. decorator flag should match. + */ + + if (deco_brsize) { + template_opsize = (deco_brsize == BR_BITS32 ? BITS32 : BITS64); + } else { + template_opsize = 0; + } + } + if ((itemp->opd[i] & ~type & ~SIZE_MASK) || (itemp->deco[i] & deco) != deco) { return MERR_INVALOP; - } else if ((itemp->opd[i] & SIZE_MASK) && - (itemp->opd[i] & SIZE_MASK) != (type & SIZE_MASK)) { - if (type & SIZE_MASK) { - /* - * when broadcasting, the element size depends on - * the instruction type. decorator flag should match. - */ -#define MATCH_BRSZ(bits) (((type & SIZE_MASK) == BITS##bits) && \ - ((itemp->deco[i] & BRSIZE_MASK) == BR_BITS##bits)) - if (!((deco & BRDCAST_MASK) && - (MATCH_BRSZ(32) || MATCH_BRSZ(64)))) { + } else if (template_opsize) { + if (template_opsize != insn_opsize) { + if (insn_opsize) { return MERR_INVALOP; + } else if (!is_class(REGISTER, type)) { + /* + * Note: we don't honor extrinsic operand sizes for registers, + * so "missing operand size" for a register should be + * considered a wildcard match rather than an error. + */ + opsizemissing = true; } - } else if (!is_class(REGISTER, type)) { - /* - * Note: we don't honor extrinsic operand sizes for registers, - * so "missing operand size" for a register should be - * considered a wildcard match rather than an error. - */ - opsizemissing = true; } } else if (is_register(instruction->oprs[i].basereg) && nasm_regvals[instruction->oprs[i].basereg] >= 16 && |
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From: nasm-bot f. J. K. S. <jin...@in...> - 2013-11-21 22:21:30
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Commit-ID: c9486b965b8883268871aa749f4f617f9835adf2 Gitweb: http://repo.or.cz/w/nasm.git?a=commitdiff;h=c9486b965b8883268871aa749f4f617f9835adf2 Author: Jin Kyu Song <jin...@in...> AuthorDate: Mon, 28 Oct 2013 17:07:57 -0700 Committer: Jin Kyu Song <jin...@in...> CommitDate: Wed, 20 Nov 2013 11:29:42 -0800 Build: Suppress warning messages Giving a correct printf format specifier supresses the warning message. And a local pointer variable is initialized with NULL. Signed-off-by: Jin Kyu Song <jin...@in...> --- parser.c | 2 +- preproc.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/parser.c b/parser.c index 700b4fc..155308f 100644 --- a/parser.c +++ b/parser.c @@ -212,7 +212,7 @@ static bool parse_braces(decoflags_t *decoflags) do { if (i == TOKEN_OPMASK) { if (*decoflags & OPMASK_MASK) { - nasm_error(ERR_NONFATAL, "opmask k%lu is already set", + nasm_error(ERR_NONFATAL, "opmask k%"PRIu64" is already set", *decoflags & OPMASK_MASK); *decoflags &= ~OPMASK_MASK; } diff --git a/preproc.c b/preproc.c index f781f95..3a0f67b 100644 --- a/preproc.c +++ b/preproc.c @@ -2156,7 +2156,7 @@ static int do_directive(Token * tline) Context *ctx; Cond *cond; MMacro *mmac, **mmhead; - Token *t, *tt, *param_start, *macro_start, *last, **tptr, *origline; + Token *t = NULL, *tt, *param_start, *macro_start, *last, **tptr, *origline; Line *l; struct tokenval tokval; expr *evalresult; |
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From: nasm-bot f. J. K. S. <jin...@in...> - 2013-11-21 22:21:29
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Commit-ID: 267d0af79c7de8887ff1618e803cafa5a528a554 Gitweb: http://repo.or.cz/w/nasm.git?a=commitdiff;h=267d0af79c7de8887ff1618e803cafa5a528a554 Author: Jin Kyu Song <jin...@in...> AuthorDate: Wed, 23 Oct 2013 18:39:03 -0700 Committer: Jin Kyu Song <jin...@in...> CommitDate: Wed, 20 Nov 2013 11:29:42 -0800 PREFETCHWT1: Add a new instruction flag PREFETCHWT1 instruction's CPUID was TBD before. Now it has its new CPUID bit : PREFETCHWT1 Signed-off-by: Jin Kyu Song <jin...@in...> --- insns.dat | 2 +- insns.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/insns.dat b/insns.dat index 202069f..9435e03 100644 --- a/insns.dat +++ b/insns.dat @@ -4146,7 +4146,7 @@ VSCATTERPF1DPD ymem64|mask [m:t1s: vsiby evex.512.66.0f38.w1 c6 /6 ] AVX51 VSCATTERPF1DPS zmem32|mask [m:t1s: vsibz evex.512.66.0f38.w0 c6 /6 ] AVX512PF,FUTURE VSCATTERPF1QPD zmem64|mask [m:t1s: vsibz evex.512.66.0f38.w1 c7 /6 ] AVX512PF,FUTURE VSCATTERPF1QPS zmem32|mask [m:t1s: vsibz evex.512.66.0f38.w0 c7 /6 ] AVX512PF,FUTURE -PREFETCHWT1 mem8 [m: 0f 0d /2 ] FUTURE +PREFETCHWT1 mem8 [m: 0f 0d /2 ] PREFETCHWT1,FUTURE ; MPX instructions BNDMK bndreg,mem32 [rm: o32 f3 0f 1b /r ] MPX,SD,FUTURE diff --git a/insns.h b/insns.h index 0320e8d..dd447c5 100644 --- a/insns.h +++ b/insns.h @@ -135,6 +135,7 @@ extern const uint8_t nasm_bytecodes[]; #define IF_AVX512PF (UINT64_C(0x1800000000)|IF_AVX512) /* AVX-512 Prefetch instructions */ #define IF_MPX UINT64_C(0x1900000000) /* MPX instructions */ #define IF_SHA UINT64_C(0x1A00000000) /* SHA instructions */ +#define IF_PREFETCHWT1 UINT64_C(0x1F00000000) /* PREFETCHWT1 instructions */ #define IF_INSMASK UINT64_C(0xFF00000000) /* the mask for instruction set types */ #define IF_PMASK UINT64_C(0xFF000000) /* the mask for processor types */ #define IF_PLEVEL UINT64_C(0x0F000000) /* the mask for processor instr. level */ |
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From: nasm-bot f. J. K. S. <jin...@in...> - 2013-11-21 22:21:29
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Commit-ID: b4e1ae18e2b1cf136b345f85535ddeffb9f52869 Gitweb: http://repo.or.cz/w/nasm.git?a=commitdiff;h=b4e1ae18e2b1cf136b345f85535ddeffb9f52869 Author: Jin Kyu Song <jin...@in...> AuthorDate: Fri, 8 Nov 2013 13:31:58 -0800 Committer: Jin Kyu Song <jin...@in...> CommitDate: Wed, 20 Nov 2013 11:29:42 -0800 MPX: Move BND prefix indication from bytecode to iflags As BND prefix validity check conflicts with jcc8 prefix, IF_BND is added for the instruction templates which can have bnd prefix for preserving the content of bound register. Signed-off-by: Jin Kyu Song <jin...@in...> --- assemble.c | 6 ++--- disasm.c | 7 +---- insns.dat | 91 +++++++++++++++++++++++++++++++------------------------------- insns.h | 1 + insns.pl | 1 - 5 files changed, 50 insertions(+), 56 deletions(-) diff --git a/assemble.c b/assemble.c index d62b930..e2e24c3 100644 --- a/assemble.c +++ b/assemble.c @@ -162,7 +162,6 @@ * \367 - address-size prefix (0x67) used as opcode extension * \370,\371 - match only if operand 0 meets byte jump criteria. * 370 is used for Jcc, 371 is used for JMP. - * \372 - BND prefix (0xF2 byte) used for preserving bnd0..3 * \373 - assemble 0x03 if bits==16, 0x05 if bits==32; * used for conditional jump over longer jump * \374 - this instruction takes an XMM VSIB memory EA @@ -1124,7 +1123,8 @@ static int64_t calcsize(int32_t segment, int64_t offset, int bits, length++; break; - case3(0370): + case 0370: + case 0371: break; case 0373: @@ -2244,7 +2244,7 @@ static enum match_result matches(const struct itemplate *itemp, /* * Check if BND prefix is allowed */ - if ((itemp->code[0] != 0372) && + if ((IF_BND & ~itemp->flags) && has_prefix(instruction, PPS_REP, P_BND)) return MERR_BADBND; diff --git a/disasm.c b/disasm.c index eace1e9..6498610 100644 --- a/disasm.c +++ b/disasm.c @@ -408,7 +408,7 @@ static int matches(const struct itemplate *t, uint8_t *data, return false; if (prefix->rep == 0xF2) - drep = P_REPNE; + drep = (t->flags & IF_BND ? P_BND : P_REPNE); else if (prefix->rep == 0xF3) drep = P_REP; @@ -862,11 +862,6 @@ static int matches(const struct itemplate *t, uint8_t *data, case 0371: break; - case 0372: - if (prefix->rep == 0xF2) - drep = P_BND; - break; - case 0374: eat = EA_XMMVSIB; break; diff --git a/insns.dat b/insns.dat index f60ea8e..4054090 100644 --- a/insns.dat +++ b/insns.dat @@ -276,22 +276,22 @@ CALL rm16 [m: o16 ff /2] 8086,NOLONG CALL rm32 [m: o32 ff /2] 386,NOLONG CALL rm64 [m: o64nw ff /2] X64 ; BND + CALL -CALL imm [i: bnd odf e8 rel] 8086,MPX -CALL imm|near [i: bnd odf e8 rel] 8086,ND,MPX -CALL imm16 [i: bnd o16 e8 rel] 8086,NOLONG,MPX -CALL imm16|near [i: bnd o16 e8 rel] 8086,ND,NOLONG,MPX -CALL imm32 [i: bnd o32 e8 rel] 386,NOLONG,MPX -CALL imm32|near [i: bnd o32 e8 rel] 386,ND,NOLONG,MPX -CALL imm64 [i: bnd o64nw e8 rel] X64,MPX -CALL imm64|near [i: bnd o64nw e8 rel] X64,ND,MPX -CALL mem|near [m: bnd odf ff /2] 8086,ND,MPX -CALL rm16|near [m: bnd o16 ff /2] 8086,NOLONG,ND,MPX -CALL rm32|near [m: bnd o32 ff /2] 386,NOLONG,ND,MPX -CALL rm64|near [m: bnd o64nw ff /2] X64,ND,MPX -CALL mem [m: bnd odf ff /2] 8086,MPX -CALL rm16 [m: bnd o16 ff /2] 8086,NOLONG,MPX -CALL rm32 [m: bnd o32 ff /2] 386,NOLONG,MPX -CALL rm64 [m: bnd o64nw ff /2] X64,MPX +CALL imm [i: odf e8 rel] 8086,MPX,BND +CALL imm|near [i: odf e8 rel] 8086,ND,MPX,BND +CALL imm16 [i: o16 e8 rel] 8086,NOLONG,MPX,BND +CALL imm16|near [i: o16 e8 rel] 8086,ND,NOLONG,MPX,BND +CALL imm32 [i: o32 e8 rel] 386,NOLONG,MPX,BND +CALL imm32|near [i: o32 e8 rel] 386,ND,NOLONG,MPX,BND +CALL imm64 [i: o64nw e8 rel] X64,MPX,BND +CALL imm64|near [i: o64nw e8 rel] X64,ND,MPX,BND +CALL mem|near [m: odf ff /2] 8086,ND,MPX,BND +CALL rm16|near [m: o16 ff /2] 8086,NOLONG,ND,MPX,BND +CALL rm32|near [m: o32 ff /2] 386,NOLONG,ND,MPX,BND +CALL rm64|near [m: o64nw ff /2] X64,ND,MPX,BND +CALL mem [m: odf ff /2] 8086,MPX,BND +CALL rm16 [m: o16 ff /2] 8086,NOLONG,MPX,BND +CALL rm32 [m: o32 ff /2] 386,NOLONG,MPX,BND +CALL rm64 [m: o64nw ff /2] X64,MPX,BND CBW void [ o16 98] 8086 CDQ void [ o32 99] 386 @@ -727,22 +727,22 @@ JMP rm16 [m: o16 ff /4] 8086,NOLONG JMP rm32 [m: o32 ff /4] 386,NOLONG JMP rm64 [m: o64nw ff /4] X64 ; BND + JMP -JMP imm [i: bnd odf e9 rel] 8086,MPX -JMP imm|near [i: bnd odf e9 rel] 8086,ND,MPX -JMP imm16 [i: bnd o16 e9 rel] 8086,NOLONG,MPX -JMP imm16|near [i: bnd o16 e9 rel] 8086,ND,NOLONG,MPX -JMP imm32 [i: bnd o32 e9 rel] 386,NOLONG,MPX -JMP imm32|near [i: bnd o32 e9 rel] 386,ND,NOLONG,MPX -JMP imm64 [i: bnd o64nw e9 rel] X64,MPX -JMP imm64|near [i: bnd o64nw e9 rel] X64,ND,MPX -JMP mem|near [m: bnd odf ff /4] 8086,ND,MPX -JMP rm16|near [m: bnd o16 ff /4] 8086,NOLONG,ND,MPX -JMP rm32|near [m: bnd o32 ff /4] 386,NOLONG,ND,MPX -JMP rm64|near [m: bnd o64nw ff /4] X64,ND,MPX -JMP mem [m: bnd odf ff /4] 8086,MPX -JMP rm16 [m: bnd o16 ff /4] 8086,NOLONG,MPX -JMP rm32 [m: bnd o32 ff /4] 386,NOLONG,MPX -JMP rm64 [m: bnd o64nw ff /4] X64,MPX +JMP imm [i: odf e9 rel] 8086,MPX,BND +JMP imm|near [i: odf e9 rel] 8086,ND,MPX,BND +JMP imm16 [i: o16 e9 rel] 8086,NOLONG,MPX,BND +JMP imm16|near [i: o16 e9 rel] 8086,ND,NOLONG,MPX,BND +JMP imm32 [i: o32 e9 rel] 386,NOLONG,MPX,BND +JMP imm32|near [i: o32 e9 rel] 386,ND,NOLONG,MPX,BND +JMP imm64 [i: o64nw e9 rel] X64,MPX,BND +JMP imm64|near [i: o64nw e9 rel] X64,ND,MPX,BND +JMP mem|near [m: odf ff /4] 8086,ND,MPX,BND +JMP rm16|near [m: o16 ff /4] 8086,NOLONG,ND,MPX,BND +JMP rm32|near [m: o32 ff /4] 386,NOLONG,ND,MPX,BND +JMP rm64|near [m: o64nw ff /4] X64,ND,MPX,BND +JMP mem [m: odf ff /4] 8086,MPX,BND +JMP rm16 [m: o16 ff /4] 8086,NOLONG,MPX,BND +JMP rm32 [m: o32 ff /4] 386,NOLONG,MPX,BND +JMP rm64 [m: o64nw ff /4] X64,MPX,BND JMPE imm [i: odf 0f b8 rel] IA64 JMPE imm16 [i: o16 0f b8 rel] IA64 @@ -1156,10 +1156,10 @@ RETF imm [i: ca iw] 8086,SW RETN void [ c3] 8086 RETN imm [i: c2 iw] 8086,SW ; BND + RET -RET void [ bnd c3] 8086,MPX -RET imm [i: bnd c2 iw] 8086,SW,MPX -RETN void [ bnd c3] 8086,MPX -RETN imm [i: bnd c2 iw] 8086,SW,MPX +RET void [ c3] 8086,MPX,BND +RET imm [i: c2 iw] 8086,SW,MPX,BND +RETN void [ c3] 8086,MPX,BND +RETN imm [i: c2 iw] 8086,SW,MPX,BND ROL rm8,unity [m-: d0 /0] 8086 ROL rm8,reg_cl [m-: d2 /0] 8086 @@ -1528,16 +1528,15 @@ Jcc imm [i: 0f 80+c rel] 386,ND Jcc imm [i: 71+c jlen e9 rel] 8086,ND Jcc imm [i: 70+c rel8] 8086 ; BND + Jcc -Jcc imm|near [i: bnd odf 0f 80+c rel] 386,MPX -Jcc imm16|near [i: bnd o16 0f 80+c rel] 386,NOLONG,MPX -Jcc imm32|near [i: bnd o32 0f 80+c rel] 386,NOLONG,MPX -Jcc imm64|near [i: bnd o64nw 0f 80+c rel] X64,MPX -Jcc imm|short [i: bnd 70+c rel8] 8086,ND,MPX -; TODO: check if bnd and jcc8 can be used together -;Jcc imm [i: bnd jcc8 70+c rel8] 8086,ND,MPX -Jcc imm [i: bnd 0f 80+c rel] 386,ND,MPX -Jcc imm [i: bnd 71+c jlen e9 rel] 8086,ND,MPX -Jcc imm [i: bnd 70+c rel8] 8086,MPX +Jcc imm|near [i: odf 0f 80+c rel] 386,MPX,BND +Jcc imm16|near [i: o16 0f 80+c rel] 386,NOLONG,MPX,BND +Jcc imm32|near [i: o32 0f 80+c rel] 386,NOLONG,MPX,BND +Jcc imm64|near [i: o64nw 0f 80+c rel] X64,MPX,BND +Jcc imm|short [i: 70+c rel8] 8086,ND,MPX,BND +Jcc imm [i: jcc8 70+c rel8] 8086,ND,MPX,BND +Jcc imm [i: 0f 80+c rel] 386,ND,MPX,BND +Jcc imm [i: 71+c jlen e9 rel] 8086,ND,MPX,BND +Jcc imm [i: 70+c rel8] 8086,MPX,BND SETcc mem [m: 0f 90+c /0] 386,SB SETcc reg8 [m: 0f 90+c /0] 386 diff --git a/insns.h b/insns.h index a170533..0320e8d 100644 --- a/insns.h +++ b/insns.h @@ -105,6 +105,7 @@ extern const uint8_t nasm_bytecodes[]; #define IF_LONG UINT64_C(0x00001000) /* long mode instruction */ #define IF_NOHLE UINT64_C(0x00002000) /* HLE prefixes forbidden */ #define IF_MIB UINT64_C(0x00004000) /* Disassemble with split EA */ +#define IF_BND UINT64_C(0x00008000) /* BND (0xF2) prefix available */ /* These flags are currently not used for anything - intended for insn set */ #define IF_UNDOC UINT64_C(0x8000000000) /* it's an undocumented instruction */ #define IF_HLE UINT64_C(0x4000000000) /* HACK NEED TO REORGANIZE THESE BITS */ diff --git a/insns.pl b/insns.pl index 2953a4d..8bd76ab 100755 --- a/insns.pl +++ b/insns.pl @@ -765,7 +765,6 @@ sub byte_code_compile($$) { 'resb' => 0340, 'jcc8' => 0370, # Match only if Jcc possible with single byte 'jmp8' => 0371, # Match only if JMP possible with single byte - 'bnd' => 0372, # BND (0xF2) prefix available 'jlen' => 0373, # Length of jump 'hlexr' => 0271, 'hlenl' => 0272, |
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