[nasm:master] BR 3392218: Disassemble 82h opcodes

[nasm-bot for H. Peter Anvin <hpa@zy...>]

Commit-ID:  eb867fe78e2ac71256ded5559f04a899ae93ab89
Gitweb:     http://repo.or.cz/w/nasm.git?a=commitdiff;h=eb867fe78e2ac71256ded5559f04a899ae93ab89
Author:     H. Peter Anvin <hpa@...>
AuthorDate: Sat, 28 Jul 2012 15:28:48 -0700
Committer:  H. Peter Anvin <hpa@...>
CommitDate: Sat, 28 Jul 2012 15:28:48 -0700

BR 3392218: Disassemble 82h opcodes

The 82h opcodes are undocumented aliases for the 80h opcodes, except
in 64-bit mode.  We don't generate them, but let the disassembler
handle them correctly.

Signed-off-by: H. Peter Anvin <hpa@...>


---
 insns.dat |    8 ++++++++
 1 files changed, 8 insertions(+), 0 deletions(-)

diff --git a/insns.dat b/insns.dat
index a4461a4..2b5228f 100644
--- a/insns.dat
+++ b/insns.dat
@@ -103,6 +103,7 @@ ADC		rm64,imm			[mi:	hle o64 81+s /2 ibd,s]			X64,SM,LOCK
 ADC		mem,imm8			[mi:	hle 80 /2 ib]				8086,SM,LOCK
 ADC		mem,imm16			[mi:	hle o16 81+s /2 ibw]			8086,SM,LOCK
 ADC		mem,imm32			[mi:	hle o32 81+s /2 ibd]			386,SM,LOCK
+ADC		rm8,imm				[mi:	hle 82 /2 ib]				8086,SM,LOCK,ND,NOLONG
 ADD		mem,reg8			[mr:	hle 00 /r]				8086,SM,LOCK
 ADD		reg8,reg8			[mr:	00 /r]					8086
 ADD		mem,reg16			[mr:	hle o16 01 /r]				8086,SM,LOCK
@@ -136,6 +137,7 @@ ADD		rm64,imm			[mi:	hle o64 81+s /0 ibd,s]			X64,SM,LOCK
 ADD		mem,imm8			[mi:	hle 80 /0 ib]				8086,SM,LOCK
 ADD		mem,imm16			[mi:	hle o16 81+s /0 ibw]			8086,SM,LOCK
 ADD		mem,imm32			[mi:	hle o32 81+s /0 ibd]			386,SM,LOCK
+ADD		rm8,imm				[mi:	hle 82 /0 ib]				8086,SM,LOCK,ND,NOLONG
 AND		mem,reg8			[mr:	hle 20 /r]				8086,SM,LOCK
 AND		reg8,reg8			[mr:	20 /r]					8086
 AND		mem,reg16			[mr:	hle o16 21 /r]				8086,SM,LOCK
@@ -169,6 +171,7 @@ AND		rm64,imm			[mi:	hle o64 81+s /4 ibd,s]			X64,SM,LOCK
 AND		mem,imm8			[mi:	hle 80 /4 ib]				8086,SM,LOCK
 AND		mem,imm16			[mi:	hle o16 81+s /4 ibw]			8086,SM,LOCK
 AND		mem,imm32			[mi:	hle o32 81+s /4 ibd]			386,SM,LOCK
+AND		rm8,imm				[mi:	hle 82 /4 ib]				8086,SM,LOCK,ND,NOLONG
 ARPL		mem,reg16			[mr:	63 /r]					286,PROT,SM,NOLONG
 ARPL		reg16,reg16			[mr:	63 /r]					286,PROT,NOLONG
 BB0_RESET	void				[	0f 3a]					PENT,CYRIX,ND
@@ -298,6 +301,7 @@ CMP		rm64,imm			[mi:	o64 81+s /7 ibd,s]			X64,SM
 CMP		mem,imm8			[mi:	80 /7 ib]				8086,SM
 CMP		mem,imm16			[mi:	o16 81+s /7 ibw]			8086,SM
 CMP		mem,imm32			[mi:	o32 81+s /7 ibd]			386,SM
+CMP		rm8,imm				[mi:	82 /7 ib]				8086,SM,ND,NOLONG
 CMPSB		void				[	repe a6]				8086
 CMPSD		void				[	repe o32 a7]				386
 CMPSQ		void				[	repe o64 a7]				X64
@@ -911,6 +915,7 @@ OR		rm64,imm			[mi:	hle o64 81+s /1 ibd,s]			X64,SM,LOCK
 OR		mem,imm8			[mi:	hle 80 /1 ib]				8086,SM,LOCK
 OR		mem,imm16			[mi:	hle o16 81+s /1 ibw]			8086,SM,LOCK
 OR		mem,imm32			[mi:	hle o32 81+s /1 ibd]			386,SM,LOCK
+OR		rm8,imm				[mi:	hle 82 /1 ib]				8086,SM,LOCK,ND,NOLONG
 OUT		imm,reg_al			[i-:	e6 ib,u]				8086,SB
 OUT		imm,reg_ax			[i-:	o16 e7 ib,u]				8086,SB
 OUT		imm,reg_eax			[i-:	o32 e7 ib,u]				386,SB
@@ -1167,6 +1172,7 @@ SBB		rm64,imm			[mi:	hle o64 81+s /3 ibd,s]			X64,SM,LOCK
 SBB		mem,imm8			[mi:	hle 80 /3 ib]				8086,SM,LOCK
 SBB		mem,imm16			[mi:	hle o16 81+s /3 ibw]			8086,SM,LOCK
 SBB		mem,imm32			[mi:	hle o32 81+s /3 ibd]			386,SM,LOCK
+SBB		rm8,imm				[mi:	hle 82 /3 ib]				8086,SM,LOCK,ND,NOLONG
 SCASB		void				[	repe ae]				8086
 SCASD		void				[	repe o32 af]				386
 SCASQ		void				[	repe o64 af]				X64
@@ -1283,6 +1289,7 @@ SUB		rm64,imm			[mi:	hle o64 81+s /5 ibd,s]			X64,SM,LOCK
 SUB		mem,imm8			[mi:	hle 80 /5 ib]				8086,SM,LOCK
 SUB		mem,imm16			[mi:	hle o16 81+s /5 ibw]			8086,SM,LOCK
 SUB		mem,imm32			[mi:	hle o32 81+s /5 ibd]			386,SM,LOCK
+SUB		rm8,imm				[mi:	hle 82 /5 ib]				8086,SM,LOCK,ND,NOLONG
 SVDC		mem80,reg_sreg			[mr:	0f 78 /r]				486,CYRIX,SMM
 SVLDT		mem80				[m:	0f 7a /0]				486,CYRIX,SMM,ND
 SVTS		mem80				[m:	0f 7c /0]				486,CYRIX,SMM
@@ -1413,6 +1420,7 @@ XOR		rm64,imm			[mi:	hle o64 81+s /6 ibd,s]			X64,SM,LOCK
 XOR		mem,imm8			[mi:	hle 80 /6 ib]				8086,SM,LOCK
 XOR		mem,imm16			[mi:	hle o16 81+s /6 ibw]			8086,SM,LOCK
 XOR		mem,imm32			[mi:	hle o32 81+s /6 ibd]			386,SM,LOCK
+XOR		rm8,imm				[mi:	hle 82 /6 ib]				8086,SM,LOCK,ND,NOLONG
 CMOVcc		reg16,mem			[rm:	o16 0f 40+c /r]				P6,SM
 CMOVcc		reg16,reg16			[rm:	o16 0f 40+c /r]				P6
 CMOVcc		reg32,mem			[rm:	o32 0f 40+c /r]				P6,SM

[nasm:master] NASM 2.10.03

[nasm-bot for H. Peter Anvin <hpa@zy...>]

Commit-ID:  c95747598fe6abd3300fa47dca6c7e1fe89f998a
Gitweb:     http://repo.or.cz/w/nasm.git?a=commitdiff;h=c95747598fe6abd3300fa47dca6c7e1fe89f998a
Author:     H. Peter Anvin <hpa@...>
AuthorDate: Sun, 22 Jul 2012 21:09:20 -0700
Committer:  H. Peter Anvin <hpa@...>
CommitDate: Sun, 22 Jul 2012 21:09:20 -0700

NASM 2.10.03



---
 version |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/version b/version
index c768ffd..7397ba2 100644
--- a/version
+++ b/version
@@ -1 +1 @@
-2.10.02
+2.10.03

[nasm:master] hle: opcode A2 forbidden with HLE prefixes

[nasm-bot for H. Peter Anvin <hpa@zy...>]

Commit-ID:  56bff2df92f721c5be9dacb66ea3cb8f6a3ab7d9
Gitweb:     http://repo.or.cz/w/nasm.git?a=commitdiff;h=56bff2df92f721c5be9dacb66ea3cb8f6a3ab7d9
Author:     H. Peter Anvin <hpa@...>
AuthorDate: Sun, 22 Jul 2012 21:04:20 -0700
Committer:  H. Peter Anvin <hpa@...>
CommitDate: Sun, 22 Jul 2012 21:04:20 -0700

hle: opcode A2 forbidden with HLE prefixes

The moffset opcodes A2 and A3 do not support HLE.  Unfortunately
checkin

fb3f4e6d HLE: Change NOHLE to be an instruction flag

... inadvertently lost the NOHLE flag for opcode A2.

Signed-off-by: H. Peter Anvin <hpa@...>


---
 insns.dat    |    2 +-
 test/hle.asm |    4 ++++
 2 files changed, 5 insertions(+), 1 deletions(-)

diff --git a/insns.dat b/insns.dat
index 3f43214..a4461a4 100644
--- a/insns.dat
+++ b/insns.dat
@@ -790,7 +790,7 @@ MOV		reg_al,mem_offs			[-i:	a0 iwdq]				8086,SM
 MOV		reg_ax,mem_offs			[-i:	o16 a1 iwdq]				8086,SM
 MOV		reg_eax,mem_offs		[-i:	o32 a1 iwdq]				386,SM
 MOV		reg_rax,mem_offs		[-i:	o64 a1 iwdq]				X64,SM
-MOV		mem_offs,reg_al			[i-:	a2 iwdq]				8086,SM
+MOV		mem_offs,reg_al			[i-:	a2 iwdq]				8086,SM,NOHLE
 MOV		mem_offs,reg_ax			[i-:	o16 a3 iwdq]				8086,SM,NOHLE
 MOV		mem_offs,reg_eax		[i-:	o32 a3 iwdq]				386,SM,NOHLE
 MOV		mem_offs,reg_rax		[i-:	o64 a3 iwdq]				X64,SM,NOHLE
diff --git a/test/hle.asm b/test/hle.asm
index e93b0b9..e59b4f5 100644
--- a/test/hle.asm
+++ b/test/hle.asm
@@ -12,4 +12,8 @@
 	xrelease mov [sym],eax
 	xacquire mov [sym],eax
 
+	mov [sym],al
+	xrelease mov [sym],al
+	xacquire mov [sym],al
+
 sym	dd 0

[nasm:master] doc: document XRELEASE MOV fix

[nasm-bot for H. Peter Anvin <hpa@zy...>]

Commit-ID:  7f9a43a7cb19d631ac3a14ee0b2e07c94dd0b40c
Gitweb:     http://repo.or.cz/w/nasm.git?a=commitdiff;h=7f9a43a7cb19d631ac3a14ee0b2e07c94dd0b40c
Author:     H. Peter Anvin <hpa@...>
AuthorDate: Sun, 22 Jul 2012 21:08:30 -0700
Committer:  H. Peter Anvin <hpa@...>
CommitDate: Sun, 22 Jul 2012 21:08:30 -0700

doc: document XRELEASE MOV fix

Signed-off-by: H. Peter Anvin <hpa@...>


---
 doc/changes.src |   10 ++++++++++
 1 files changed, 10 insertions(+), 0 deletions(-)

diff --git a/doc/changes.src b/doc/changes.src
index c7d1576..eff3098 100644
--- a/doc/changes.src
+++ b/doc/changes.src
@@ -7,6 +7,16 @@
 The NASM 2 series support x86-64, and is the production version of NASM
 since 2007.
 
+\S{cl-2.10.03} Version 2.10.03
+
+\b Correct the assembly of the instruction:
+
+\c XRELEASE MOV [absolute],AL
+
+Previous versions would incorrectly generate \c{F3 A2} for this
+instruction and issue a warning; correct behavior is to emit \c{F3 88
+05}.
+
 \S{cl-2.10.02} Version 2.10.02
 
 \b Add the \c{ifunc} macro package with integer functions, currently

[nasm:master] changes: add changes since 2.10.01

[nasm-bot for H. Peter Anvin <hpa@zy...>]

Commit-ID:  5c4c50683450a729aaf3d054e8d85bb12494a656
Gitweb:     http://repo.or.cz/w/nasm.git?a=commitdiff;h=5c4c50683450a729aaf3d054e8d85bb12494a656
Author:     H. Peter Anvin <hpa@...>
AuthorDate: Fri, 20 Jul 2012 17:53:55 -0700
Committer:  H. Peter Anvin <hpa@...>
CommitDate: Fri, 20 Jul 2012 17:53:55 -0700

changes: add changes since 2.10.01

ilog2*() and new instructions.

Signed-off-by: H. Peter Anvin <hpa@...>


---
 doc/changes.src |    7 +++++++
 1 files changed, 7 insertions(+), 0 deletions(-)

diff --git a/doc/changes.src b/doc/changes.src
index 09ff7d3..c7d1576 100644
--- a/doc/changes.src
+++ b/doc/changes.src
@@ -7,6 +7,13 @@
 The NASM 2 series support x86-64, and is the production version of NASM
 since 2007.
 
+\S{cl-2.10.02} Version 2.10.02
+
+\b Add the \c{ifunc} macro package with integer functions, currently
+only integer logarithms.  See \k{pkg_ifunc}.
+
+\b Add the \c{RDSEED}, \c{ADCX} and \c{ADOX} instructions.
+
 \S{cl-2.10.01} Version 2.10.01
 
 \b Add missing VPMOVMSKB instruction with reg32, ymmreg operands.

[nasm:master] doc: document ifunc()

[nasm-bot for H. Peter Anvin <hpa@zy...>]

Commit-ID:  96eace3841c14b1618f561e6766ea4cfb2534b9f
Gitweb:     http://repo.or.cz/w/nasm.git?a=commitdiff;h=96eace3841c14b1618f561e6766ea4cfb2534b9f
Author:     H. Peter Anvin <hpa@...>
AuthorDate: Fri, 20 Jul 2012 17:51:57 -0700
Committer:  H. Peter Anvin <hpa@...>
CommitDate: Fri, 20 Jul 2012 17:51:57 -0700

doc: document ifunc()

Signed-off-by: H. Peter Anvin <hpa@...>


---
 doc/nasmdoc.src |   52 ++++++++++++++++++++++++++++++++++++++++++++--------
 1 files changed, 44 insertions(+), 8 deletions(-)

diff --git a/doc/nasmdoc.src b/doc/nasmdoc.src
index 5664b5b..0d21090 100644
--- a/doc/nasmdoc.src
+++ b/doc/nasmdoc.src
@@ -1787,16 +1787,24 @@ Since the \c{%} character is used extensively by the macro
 modulo operators are followed by white space wherever they appear.
 
 
-\S{expmul} \i{Unary Operators}: \I{+ opunary}\c{+}, \I{- opunary}\c{-},
-\i\c{~}, \I{! opunary}\c{!} and \i\c{SEG}
-
-The highest-priority operators in NASM's expression grammar are
-those which only apply to one argument. \c{-} negates its operand,
-\c{+} does nothing (it's provided for symmetry with \c{-}), \c{~}
-computes the \i{one's complement} of its operand, \c{!} is the
-\i{logical negation} operator, and \c{SEG} provides the \i{segment address}
+\S{expmul} \i{Unary Operators}
+
+The highest-priority operators in NASM's expression grammar are those
+which only apply to one argument.  These are \I{+ opunary}\c{+}, \I{-
+opunary}\c{-}, \i\c{~}, \I{! opunary}\c{!}, \i\c{SEG}, and the
+\i{integer functions} operators.
+
+\c{-} negates its operand, \c{+} does nothing (it's provided for
+symmetry with \c{-}), \c{~} computes the \i{one's complement} of its
+operand, \c{!} is the \i{logical negation} operator.
+
+\c{SEG} provides the \i{segment address}
 of its operand (explained in more detail in \k{segwrt}).
 
+A set of additional operators with leading and trailing double
+underscores are used to implement the integer functions of the
+\c{ifunc} macro package, see \k{pkg_ifunc}.
+
 
 \H{segwrt} \i\c{SEG} and \i\c{WRT}
 
@@ -4276,6 +4284,34 @@ This packages contains the following floating-point convenience macros:
 \c %define float128h(x)    __float128h__(x)
 
 
+\H{pkg_ifunc} \i\c{ifunc}: \i{Integer functions}
+
+This package contains a set of macros which implement integer
+functions.  These are actually implemented as special operators, but
+are most conveniently accessed via this macro package.
+
+The macros provided are:
+
+\S{ilog2} \i{Integer logarithms}
+
+These functions calculate the integer logarithm base 2 of their
+argument, considered as an unsigned integer.  The only differences
+between the functions is their behavior if the argument provided is
+not a power of two.
+
+The function \i\c{ilog2e()} (alias \i\c{ilog2()}) generate an error if
+the argument is not a power of two.
+
+The function \i\c{ilog2w()} generate a warning if the argument is not
+a power of two.
+
+The function \i\c{ilog2f()} rounds the argument down to the nearest
+power of two; if the argument is zero it returns zero.
+
+The function \i\c{ilog2c()} rounds the argument up to the nearest
+power of two.
+
+
 \C{directive} \i{Assembler Directives}
 
 NASM, though it attempts to avoid the bureaucracy of assemblers like

[nasm:master] NASM 2.10.02

[nasm-bot for H. Peter Anvin <hpa@zy...>]

Commit-ID:  46a80636c2fb0385ac6dec97e33e2f9e29f283d9
Gitweb:     http://repo.or.cz/w/nasm.git?a=commitdiff;h=46a80636c2fb0385ac6dec97e33e2f9e29f283d9
Author:     H. Peter Anvin <hpa@...>
AuthorDate: Fri, 20 Jul 2012 17:55:37 -0700
Committer:  H. Peter Anvin <hpa@...>
CommitDate: Fri, 20 Jul 2012 17:55:37 -0700

NASM 2.10.02



---
 version |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/version b/version
index 26e5946..c768ffd 100644
--- a/version
+++ b/version
@@ -1 +1 @@
-2.10.01
+2.10.02

[nasm:master] isnsn.dat: add norexw to instructions with only 32- and 64-bit forms

[nasm-bot for H. Peter Anvin <hpa@zy...>]

Commit-ID:  0498f87a64413dfeac644eeb16846239b9d1ed38
Gitweb:     http://repo.or.cz/w/nasm.git?a=commitdiff;h=0498f87a64413dfeac644eeb16846239b9d1ed38
Author:     H. Peter Anvin <hpa@...>
AuthorDate: Fri, 20 Jul 2012 17:15:25 -0700
Committer:  H. Peter Anvin <hpa@...>
CommitDate: Fri, 20 Jul 2012 17:15:25 -0700

isnsn.dat: add norexw to instructions with only 32- and 64-bit forms

Add norexw to the 32-bit versions of instructions with only 32- and
64-bit forms (66 ignored as a size override.)

Signed-off-by: H. Peter Anvin <hpa@...>


---
 insns.dat |   12 ++++++------
 1 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/insns.dat b/insns.dat
index 5622de0..3f43214 100644
--- a/insns.dat
+++ b/insns.dat
@@ -2861,16 +2861,16 @@ VFNMSUB321SD	xmmreg,xmmreg,xmmrm64		[rvm:	vex.dds.128.66.0f38.w1 bf /r]		FMA,FUT
 ;# Intel post-32 nm processor instructions
 ;
 ; Per AVX spec revision 7, document 319433-007
-RDFSBASE	reg32				[m:	f3 0f ae /0]				LONG,FUTURE
+RDFSBASE	reg32				[m:	norexw f3 0f ae /0]			LONG,FUTURE
 RDFSBASE	reg64				[m:	o64 f3 0f ae /0]			LONG,FUTURE
-RDGSBASE	reg32				[m:	f3 0f ae /1]				LONG,FUTURE
+RDGSBASE	reg32				[m:	norexw f3 0f ae /1]			LONG,FUTURE
 RDGSBASE	reg64				[m:	o64 f3 0f ae /1]			LONG,FUTURE
 RDRAND		reg16				[m:	o16 0f c7 /6]				FUTURE
 RDRAND		reg32				[m:	o32 0f c7 /6]				FUTURE
 RDRAND		reg64				[m:	o64 0f c7 /6]				LONG,FUTURE
-WRFSBASE	reg32				[m:	f3 0f ae /2]				LONG,FUTURE
+WRFSBASE	reg32				[m:	norexw f3 0f ae /2]			LONG,FUTURE
 WRFSBASE	reg64				[m:	o64 f3 0f ae /2]			LONG,FUTURE
-WRGSBASE	reg32				[m:	f3 0f ae /3]				LONG,FUTURE
+WRGSBASE	reg32				[m:	norexw f3 0f ae /3]			LONG,FUTURE
 WRGSBASE	reg64				[m:	o64 f3 0f ae /3]			LONG,FUTURE
 VCVTPH2PS	ymmreg,xmmrm128			[rm:	vex.256.66.0f38.w0 13 /r]		AVX,FUTURE
 VCVTPH2PS	xmmreg,xmmrm64			[rm:	vex.128.66.0f38.w0 13 /r]		AVX,FUTURE
@@ -2878,9 +2878,9 @@ VCVTPS2PH	xmmrm128,ymmreg,imm8		[mri:	vex.256.66.0f3a.w0 1d /r ib]		AVX,FUTURE
 VCVTPS2PH	xmmrm64,xmmreg,imm8		[mri:	vex.128.66.0f3a.w0 1d /r ib]		AVX,FUTURE
 
 ; Per AVX spec revision 13, document 319433-013
-ADCX		reg32,rm32			[rm:	66 0f 38 f6 /r]				FUTURE
+ADCX		reg32,rm32			[rm:	norexw 66 0f 38 f6 /r]			FUTURE
 ADCX		reg64,rm64			[rm:	o64 66 0f 38 f6 /r]			LONG,FUTURE
-ADOX		reg32,rm32			[rm:	f3 0f 38 f6 /r]				FUTURE
+ADOX		reg32,rm32			[rm:	norexw f3 0f 38 f6 /r]			FUTURE
 ADOX		reg64,rm64			[rm:	o64 f3 0f 38 f6 /r]			LONG,FUTURE
 RDSEED		reg16				[m:	o16 0f c7 /7]				FUTURE
 RDSEED		reg32				[m:	o32 0f c7 /7]				FUTURE

[nasm:master] insns.dat: new instructions from the 013 AVX spec

[nasm-bot for H. Peter Anvin <hpa@li...>]

Commit-ID:  d73d7db48fba69c3cc4544f82ce886e7098aeeb0
Gitweb:     http://repo.or.cz/w/nasm.git?a=commitdiff;h=d73d7db48fba69c3cc4544f82ce886e7098aeeb0
Author:     H. Peter Anvin <hpa@...>
AuthorDate: Fri, 13 Jul 2012 09:58:20 +0200
Committer:  H. Peter Anvin <hpa@...>
CommitDate: Fri, 13 Jul 2012 09:58:20 +0200

insns.dat: new instructions from the 013 AVX spec

New instructions (ADCX, ADOX, RDSEED) from the 013 AVX spec
(Intel® Architecture Instruction Set Extensions Programming
Reference).

Note: ADCX in 64-bit mode disassembles incorrectly with a 64-bit
argument.  This still needs to be fixed before a 2.10.02 release.

Signed-off-by: H. Peter Anvin <hpa@...>


---
 insns.dat |    9 +++++++++
 1 files changed, 9 insertions(+), 0 deletions(-)

diff --git a/insns.dat b/insns.dat
index 1f277a9..5622de0 100644
--- a/insns.dat
+++ b/insns.dat
@@ -2877,6 +2877,15 @@ VCVTPH2PS	xmmreg,xmmrm64			[rm:	vex.128.66.0f38.w0 13 /r]		AVX,FUTURE
 VCVTPS2PH	xmmrm128,ymmreg,imm8		[mri:	vex.256.66.0f3a.w0 1d /r ib]		AVX,FUTURE
 VCVTPS2PH	xmmrm64,xmmreg,imm8		[mri:	vex.128.66.0f3a.w0 1d /r ib]		AVX,FUTURE
 
+; Per AVX spec revision 13, document 319433-013
+ADCX		reg32,rm32			[rm:	66 0f 38 f6 /r]				FUTURE
+ADCX		reg64,rm64			[rm:	o64 66 0f 38 f6 /r]			LONG,FUTURE
+ADOX		reg32,rm32			[rm:	f3 0f 38 f6 /r]				FUTURE
+ADOX		reg64,rm64			[rm:	o64 f3 0f 38 f6 /r]			LONG,FUTURE
+RDSEED		reg16				[m:	o16 0f c7 /7]				FUTURE
+RDSEED		reg32				[m:	o32 0f c7 /7]				FUTURE
+RDSEED		reg64				[m:	o64 0f c7 /7]				LONG,FUTURE
+
 ;# VIA (Centaur) security instructions
 XSTORE		void				[	0f a7 c0]				PENT,CYRIX
 XCRYPTECB	void				[	mustrep 0f a7 c8]			PENT,CYRIX