nasm-cvs — CVS commit messages

[nasm:master] NASM 2.11.03

[nasm-bot f. H. P. A. <hp...@zy...>]

Commit-ID:  1179a67a8e538b058e2ffbb7c408b7d9128ce2d0
Gitweb:     http://repo.or.cz/w/nasm.git?a=commitdiff;h=1179a67a8e538b058e2ffbb7c408b7d9128ce2d0
Author:     H. Peter Anvin <hp...@zy...>
AuthorDate: Mon, 5 May 2014 11:22:02 -0700
Committer:  H. Peter Anvin <hp...@zy...>
CommitDate: Mon, 5 May 2014 11:22:02 -0700

NASM 2.11.03



---
 version | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/version b/version
index 4369326..ca6e6b5 100644
--- a/version
+++ b/version
@@ -1 +1 @@
-2.11.02
+2.11.03

[nasm:master] NASM 2.11.02

[nasm-bot f. H. P. A. <hp...@li...>]

Commit-ID:  429beab924958b75b91606f9b2da354804ca6eb5
Gitweb:     http://repo.or.cz/w/nasm.git?a=commitdiff;h=429beab924958b75b91606f9b2da354804ca6eb5
Author:     H. Peter Anvin <hp...@li...>
AuthorDate: Wed, 19 Feb 2014 15:50:26 -0800
Committer:  H. Peter Anvin <hp...@li...>
CommitDate: Wed, 19 Feb 2014 15:50:26 -0800

NASM 2.11.02



---
 version | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/version b/version
index 85bfc81..4369326 100644
--- a/version
+++ b/version
@@ -1 +1 @@
-2.11.01
+2.11.02

[nasm:master] Add CLFLUSHOPT instruction

[nasm-bot f. H. P. A. <hp...@li...>]

Commit-ID:  727eb3f8f60ad8806aba3d07ea6b0bbd450b5ae5
Gitweb:     http://repo.or.cz/w/nasm.git?a=commitdiff;h=727eb3f8f60ad8806aba3d07ea6b0bbd450b5ae5
Author:     H. Peter Anvin <hp...@li...>
AuthorDate: Wed, 19 Feb 2014 15:39:57 -0800
Committer:  H. Peter Anvin <hp...@li...>
CommitDate: Wed, 19 Feb 2014 15:40:53 -0800

Add CLFLUSHOPT instruction

Add the CLFLUSHOPT instruction from the Intel Instruction Set
Architecture Extensions document version 319433-018 (Feb 2014).

Signed-off-by: H. Peter Anvin <hp...@li...>


---
 doc/changes.src | 2 ++
 insns.dat       | 3 +++
 2 files changed, 5 insertions(+)

diff --git a/doc/changes.src b/doc/changes.src
index 7e11f58..beabdd9 100644
--- a/doc/changes.src
+++ b/doc/changes.src
@@ -11,6 +11,8 @@ since 2007.
 
 \b Add the \c{XSAVEC}, \c{XSAVES} and \c{XRSTORS} family instructions.
 
+\b Add the \c{CLFLUSHOPT} instruction.
+
 \S{cl-2.11.01} Version 2.11.01
 
 \b Allow instructions which implicitly uses \c{XMM0} (\c{VBLENDVPD},
diff --git a/insns.dat b/insns.dat
index ddc305d..e5622ec 100644
--- a/insns.dat
+++ b/insns.dat
@@ -4142,6 +4142,9 @@ SHA256RNDS2 xmmreg,xmmrm128         [rm:        0f 38 cb /r ]    SHA,FUTURE
 SHA256MSG1  xmmreg,xmmrm128         [rm:        0f 38 cc /r ]    SHA,FUTURE
 SHA256MSG2  xmmreg,xmmrm128         [rm:        0f 38 cd /r ]    SHA,FUTURE
 
+; New memory instructions
+CLFLUSHOPT	mem				[m:	66 0f ae /7]				FUTURE
+
 ;# Systematic names for the hinting nop instructions
 ; These should be last in the file
 HINT_NOP0	rm16				[m:	o16 0f 18 /0]				P6,UNDOC

[nasm:master] insns: add XSAVEC, XSAVES and XRSTORS instructions

[nasm-bot f. H. P. A. <hp...@li...>]

Commit-ID:  0b7db57deb2240f4455bb24341636f352194ca44
Gitweb:     http://repo.or.cz/w/nasm.git?a=commitdiff;h=0b7db57deb2240f4455bb24341636f352194ca44
Author:     H. Peter Anvin <hp...@li...>
AuthorDate: Wed, 19 Feb 2014 14:55:54 -0800
Committer:  H. Peter Anvin <hp...@li...>
CommitDate: Wed, 19 Feb 2014 14:58:42 -0800

insns: add XSAVEC, XSAVES and XRSTORS instructions

Add the XSAVEC, XSAVES, and XRSTORS instructions from the Intel SDM
release 253665-050US (Feb 2014).

Signed-off-by: H. Peter Anvin <hp...@li...>


---
 doc/changes.src | 4 ++++
 insns.dat       | 6 ++++++
 2 files changed, 10 insertions(+)

diff --git a/doc/changes.src b/doc/changes.src
index f4b2842..7e11f58 100644
--- a/doc/changes.src
+++ b/doc/changes.src
@@ -7,6 +7,10 @@
 The NASM 2 series supports x86-64, and is the production version of NASM
 since 2007.
 
+\S{cl-2.11.02} Version 2.11.02
+
+\b Add the \c{XSAVEC}, \c{XSAVES} and \c{XRSTORS} family instructions.
+
 \S{cl-2.11.01} Version 2.11.01
 
 \b Allow instructions which implicitly uses \c{XMM0} (\c{VBLENDVPD},
diff --git a/insns.dat b/insns.dat
index 1b8d85a..ddc305d 100644
--- a/insns.dat
+++ b/insns.dat
@@ -1586,10 +1586,16 @@ XGETBV		void				[	0f 01 d0]				NEHALEM
 XSETBV		void				[	0f 01 d1]				NEHALEM,PRIV
 XSAVE		mem				[m:	np 0f ae /4]				NEHALEM
 XSAVE64		mem				[m:	o64 np 0f ae /4]			LONG,NEHALEM
+XSAVEC		mem				[m:	np 0f c7 /4]				FUTURE
+XSAVEC64	mem				[m:	o64 np 0f c7 /4]			LONG,FUTURE
 XSAVEOPT	mem				[m:	np 0f ae /6]				FUTURE
 XSAVEOPT64	mem				[m:	o64 np 0f ae /6]			LONG,FUTURE
+XSAVES		mem				[m:	np 0f c7 /5]				FUTURE
+XSAVES64	mem				[m:	o64 np 0f c7 /5]			LONG,FUTURE
 XRSTOR		mem				[m:	np 0f ae /5]				NEHALEM
 XRSTOR64	mem				[m:	o64 np 0f ae /5]			LONG,NEHALEM
+XRSTORS		mem				[m:	np 0f c7 /3]				FUTURE
+XRSTORS64	mem				[m:	o64 np 0f c7 /3]			LONG,FUTURE
 
 ; These instructions are not SSE-specific; they are
 ;# Generic memory operations

[nasm:master] changes.src: changelog for 2.11.01

[nasm-bot f. H. P. A. <hp...@li...>]

Commit-ID:  f2d2569bb6cd5b46770e3427aff17be307f37c9a
Gitweb:     http://repo.or.cz/w/nasm.git?a=commitdiff;h=f2d2569bb6cd5b46770e3427aff17be307f37c9a
Author:     H. Peter Anvin <hp...@li...>
AuthorDate: Tue, 18 Feb 2014 14:05:14 -0800
Committer:  H. Peter Anvin <hp...@li...>
CommitDate: Tue, 18 Feb 2014 14:05:14 -0800

changes.src: changelog for 2.11.01

Signed-off-by: H. Peter Anvin <hp...@li...>


---
 doc/changes.src | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/doc/changes.src b/doc/changes.src
index ba3e7d3..f4b2842 100644
--- a/doc/changes.src
+++ b/doc/changes.src
@@ -7,6 +7,19 @@
 The NASM 2 series supports x86-64, and is the production version of NASM
 since 2007.
 
+\S{cl-2.11.01} Version 2.11.01
+
+\b Allow instructions which implicitly uses \c{XMM0} (\c{VBLENDVPD},
+\c{VBLENDVPS}, \c{PBLENDVB} and \c{SHA256RNDS2}) to be specified
+without an explicit \c{xmm0} on the assembly line.  In other words,
+the following two lines produce the same output:
+
+\c      vblendvpd xmm2,xmm1,xmm0      ; Last operand is fixed xmm0
+\c      vblendvpd xmm2,xmm1           ; Implicit xmm0 omitted
+
+\b In the ELF backends, don't crash the assembler if \c{section align}
+is specified without a value.
+
 \S{cl-2.11} Version 2.11
 
 \b Add support for the Intel AVX-512 instruction set:

[nasm:master] NASM 2.11.01

[nasm-bot f. H. P. A. <hp...@li...>]

Commit-ID:  31f23b05f42befcdbc7f2d9a8d65294d3ea6a5be
Gitweb:     http://repo.or.cz/w/nasm.git?a=commitdiff;h=31f23b05f42befcdbc7f2d9a8d65294d3ea6a5be
Author:     H. Peter Anvin <hp...@li...>
AuthorDate: Tue, 18 Feb 2014 14:05:52 -0800
Committer:  H. Peter Anvin <hp...@li...>
CommitDate: Tue, 18 Feb 2014 14:05:52 -0800

NASM 2.11.01



---
 version | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/version b/version
index 6a5fe6e..85bfc81 100644
--- a/version
+++ b/version
@@ -1 +1 @@
-2.11
+2.11.01

[nasm:master] outelf: Error out on "section align" without value

[nasm-bot f. H. P. A. <hp...@li...>]

Commit-ID:  0ace62cb6a45b2cd710220a82a9b197c9e30b4f9
Gitweb:     http://repo.or.cz/w/nasm.git?a=commitdiff;h=0ace62cb6a45b2cd710220a82a9b197c9e30b4f9
Author:     H. Peter Anvin <hp...@li...>
AuthorDate: Tue, 18 Feb 2014 13:23:27 -0800
Committer:  H. Peter Anvin <hp...@li...>
CommitDate: Tue, 18 Feb 2014 13:30:44 -0800

outelf: Error out on "section align" without value

If someone specifies "section align" without =value, error out.

Reported-by: Ilya Albrekht <ily...@gm...>
Signed-off-by: H. Peter Anvin <hp...@li...>


---
 output/outelf.c | 23 ++++++++++++++---------
 1 file changed, 14 insertions(+), 9 deletions(-)

diff --git a/output/outelf.c b/output/outelf.c
index bfbf625..61ae1fc 100644
--- a/output/outelf.c
+++ b/output/outelf.c
@@ -1,6 +1,6 @@
 /* ----------------------------------------------------------------------- *
  *   
- *   Copyright 1996-2010 The NASM Authors - All Rights Reserved
+ *   Copyright 1996-2014 The NASM Authors - All Rights Reserved
  *   See the file AUTHORS included with the NASM distribution for
  *   the specific copyright holders.
  *
@@ -76,15 +76,20 @@ void section_attrib(char *name, char *attr, int pass,
         return;
 
     while ((opt = nasm_opt_val(opt, &val, &next))) {
-        if (!nasm_stricmp(opt, "align") && val) {
-            *align = atoi(val);
-            if (*align == 0) {
-                *align = SHA_ANY;
-            } else if (!is_power2(*align)) {
+        if (!nasm_stricmp(opt, "align")) {
+            if (!val) {
                 nasm_error(ERR_NONFATAL,
-                           "section alignment %"PRId64" is not a power of two",
-                           *align);
-                *align = SHA_ANY;
+                           "section align without value specified");
+            } else {
+                *align = atoi(val);
+                if (*align == 0) {
+                    *align = SHA_ANY;
+                } else if (!is_power2(*align)) {
+                    nasm_error(ERR_NONFATAL,
+                               "section alignment %"PRId64" is not a power of two",
+                               *align);
+                    *align = SHA_ANY;
+                }
             }
         } else if (!nasm_stricmp(opt, "alloc")) {
             *flags_and  |= SHF_ALLOC;

[nasm:master] BR 3392275: Don't require xmm0 to be specified when implicit

[nasm-bot f. H. P. A. <hp...@li...>]

Commit-ID:  1eef781594b08a7f2d3a715f8f4fa4c28a29e65a
Gitweb:     http://repo.or.cz/w/nasm.git?a=commitdiff;h=1eef781594b08a7f2d3a715f8f4fa4c28a29e65a
Author:     H. Peter Anvin <hp...@li...>
AuthorDate: Sun, 16 Feb 2014 10:25:25 -0800
Committer:  H. Peter Anvin <hp...@li...>
CommitDate: Sun, 16 Feb 2014 10:25:25 -0800

BR 3392275: Don't require xmm0 to be specified when implicit

BR 3392275 complains about xmm0 having to be explicitly included in
the assembly syntax when it is implicit in the encoding.  In the
interest of "be liberal in what you accept", accept either form in the
input.

Signed-off-by: H. Peter Anvin <hp...@li...>


---
 insns.dat     |  6 +++++-
 test/xmm0.asm | 12 ++++++++++++
 2 files changed, 17 insertions(+), 1 deletion(-)

diff --git a/insns.dat b/insns.dat
index 7125749..1b8d85a 100644
--- a/insns.dat
+++ b/insns.dat
@@ -1,6 +1,6 @@
 ;; --------------------------------------------------------------------------
 ;;
-;;   Copyright 1996-2013 The NASM Authors - All Rights Reserved
+;;   Copyright 1996-2014 The NASM Authors - All Rights Reserved
 ;;   See the file AUTHORS included with the NASM distribution for
 ;;   the specific copyright holders.
 ;;
@@ -1919,7 +1919,9 @@ LZCNT		reg64,rm64			[rm:	o64 f3i 0f bd /r]			X64,AMD
 BLENDPD		xmmreg,xmmrm,imm		[rmi:	66 0f 3a 0d /r ib,u]			SSE41
 BLENDPS		xmmreg,xmmrm,imm		[rmi:	66 0f 3a 0c /r ib,u]			SSE41
 BLENDVPD	xmmreg,xmmrm,xmm0		[rm-:	66 0f 38 15 /r]				SSE41
+BLENDVPD	xmmreg,xmmrm			[rm:	66 0f 38 15 /r]				SSE41
 BLENDVPS	xmmreg,xmmrm,xmm0		[rm-:	66 0f 38 14 /r]				SSE41
+BLENDVPS	xmmreg,xmmrm			[rm:	66 0f 38 14 /r]				SSE41
 DPPD		xmmreg,xmmrm,imm		[rmi:	66 0f 3a 41 /r ib,u]			SSE41
 DPPS		xmmreg,xmmrm,imm		[rmi:	66 0f 3a 40 /r ib,u]			SSE41
 EXTRACTPS	rm32,xmmreg,imm			[mri:	66 0f 3a 17 /r ib,u]			SSE41
@@ -1929,6 +1931,7 @@ MOVNTDQA	xmmreg,mem128			[rm:	66 0f 38 2a /r]				SSE41
 MPSADBW		xmmreg,xmmrm,imm		[rmi:	66 0f 3a 42 /r ib,u]			SSE41
 PACKUSDW	xmmreg,xmmrm			[rm:	66 0f 38 2b /r]				SSE41
 PBLENDVB	xmmreg,xmmrm,xmm0		[rm-:	66 0f 38 10 /r]				SSE41
+PBLENDVB	xmmreg,xmmrm			[rm:	66 0f 38 10 /r]				SSE41
 PBLENDW		xmmreg,xmmrm,imm		[rmi:	66 0f 3a 0e /r ib,u]			SSE41
 PCMPEQQ		xmmreg,xmmrm			[rm:	66 0f 38 29 /r]				SSE41
 PEXTRB		reg32,xmmreg,imm		[mri:	66 0f 3a 14 /r ib,u]			SSE41
@@ -4129,6 +4132,7 @@ SHA1NEXTE   xmmreg,xmmrm128         [rm:        0f 38 c8 /r ]    SHA,FUTURE
 SHA1MSG1    xmmreg,xmmrm128         [rm:        0f 38 c9 /r ]    SHA,FUTURE
 SHA1MSG2    xmmreg,xmmrm128         [rm:        0f 38 ca /r ]    SHA,FUTURE
 SHA256RNDS2 xmmreg,xmmrm128,xmm0    [rm-:       0f 38 cb /r ]    SHA,FUTURE
+SHA256RNDS2 xmmreg,xmmrm128         [rm:        0f 38 cb /r ]    SHA,FUTURE
 SHA256MSG1  xmmreg,xmmrm128         [rm:        0f 38 cc /r ]    SHA,FUTURE
 SHA256MSG2  xmmreg,xmmrm128         [rm:        0f 38 cd /r ]    SHA,FUTURE
 
diff --git a/test/xmm0.asm b/test/xmm0.asm
new file mode 100644
index 0000000..4823143
--- /dev/null
+++ b/test/xmm0.asm
@@ -0,0 +1,12 @@
+; BR 3392275: don't require xmm0 to be explicitly declared when implicit
+
+	bits 32
+
+	blendvpd xmm2,xmm1,xmm0
+	blendvpd xmm2,xmm1
+	blendvps xmm2,xmm1,xmm0
+	blendvps xmm2,xmm1
+	pblendvb xmm2,xmm1,xmm0
+	pblendvb xmm2,xmm1
+	sha256rnds2 xmm2,xmm1,xmm0
+	sha256rnds2 xmm2,xmm1

[nasm:master] BR3392274: output: Elf -- Don't crash on erronious syntax

[nasm-bot f. C. G. <gor...@gm...>]

Commit-ID:  d0293d339272af18b2258d702d3e1e44c0501292
Gitweb:     http://repo.or.cz/w/nasm.git?a=commitdiff;h=d0293d339272af18b2258d702d3e1e44c0501292
Author:     Cyrill Gorcunov <gor...@gm...>
AuthorDate: Sat, 15 Feb 2014 18:40:12 +0400
Committer:  Cyrill Gorcunov <gor...@gm...>
CommitDate: Sat, 15 Feb 2014 18:40:12 +0400

BR3392274: output: Elf -- Don't crash on erronious syntax

Elf align section attribute requires syntax "align=value",
but in case if '=' is missed we pass nil pointer into
atoi function which cause libc to crash.

Signed-off-by: Cyrill Gorcunov <gor...@gm...>


---
 output/outelf.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/output/outelf.c b/output/outelf.c
index 9ec0035..bfbf625 100644
--- a/output/outelf.c
+++ b/output/outelf.c
@@ -76,7 +76,7 @@ void section_attrib(char *name, char *attr, int pass,
         return;
 
     while ((opt = nasm_opt_val(opt, &val, &next))) {
-        if (!nasm_stricmp(opt, "align")) {
+        if (!nasm_stricmp(opt, "align") && val) {
             *align = atoi(val);
             if (*align == 0) {
                 *align = SHA_ANY;

[nasm:master] changes: Document change in [nosplit reg]

[nasm-bot f. H. P. A. <hp...@zy...>]

Commit-ID:  be1d052fffdca447fe7a5af7cb02b7245be680d3
Gitweb:     http://repo.or.cz/w/nasm.git?a=commitdiff;h=be1d052fffdca447fe7a5af7cb02b7245be680d3
Author:     H. Peter Anvin <hp...@zy...>
AuthorDate: Tue, 31 Dec 2013 10:35:12 -0800
Committer:  H. Peter Anvin <hp...@zy...>
CommitDate: Tue, 31 Dec 2013 10:35:12 -0800

changes: Document change in [nosplit reg]

Document that [nosplit reg] as opposed to [nosplit reg*1] will no
longer force an index register.

Signed-off-by: H. Peter Anvin <hp...@zy...>


---
 doc/changes.src | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/doc/changes.src b/doc/changes.src
index 98da2b1..a366c3f 100644
--- a/doc/changes.src
+++ b/doc/changes.src
@@ -54,9 +54,15 @@ This is expected to be most useful for the MPX instructions.
 have NASM encode the corresponding instruction, if possible, with an EVEX,
 3-byte VEX, or 2-byte VEX prefix, respectively.
 
-
 \b Support for section names longer than 8 bytes in Win32/Win64 COFF.
 
+\b The \c{NOSPLIT} directive by itself no longer forces a single
+register to become an index register, unless it has an explicit
+multiplier.
+
+\c      mov eax,[nosplit eax]       ; eax as base register
+\c      mov eax,[nosplit eax*1]     ; eax as index register
+
 \S{cl-2.10.09} Version 2.10.09
 
 \b Pregenerate man pages.

[nasm:master] doc: Document DEFAULT BND/NOBND in changes, add use case

[nasm-bot f. H. P. A. <hp...@zy...>]

Commit-ID:  b2fcac9a1d54cf133160539ea64cbb27542d3c3f
Gitweb:     http://repo.or.cz/w/nasm.git?a=commitdiff;h=b2fcac9a1d54cf133160539ea64cbb27542d3c3f
Author:     H. Peter Anvin <hp...@zy...>
AuthorDate: Tue, 31 Dec 2013 10:38:51 -0800
Committer:  H. Peter Anvin <hp...@zy...>
CommitDate: Tue, 31 Dec 2013 10:38:51 -0800

doc: Document DEFAULT BND/NOBND in changes, add use case

Add DEFAULT BND/NOBND to the change history, and explain the use case.

Signed-off-by: H. Peter Anvin <hp...@zy...>


---
 doc/changes.src | 5 +++++
 doc/nasmdoc.src | 3 +++
 2 files changed, 8 insertions(+)

diff --git a/doc/changes.src b/doc/changes.src
index a366c3f..ba3e7d3 100644
--- a/doc/changes.src
+++ b/doc/changes.src
@@ -50,6 +50,11 @@ This is expected to be most useful for the MPX instructions.
 
 \b Support \c{BND} prefix for branch instructions (for MPX).
 
+\b The \c{DEFAULT} directive can now take \c{BND} and \c{NOBND}
+options to indicate whether all relevant branches should be getting
+\c{BND} prefixes.  This is expected to be the normal for use in MPX
+code.
+
 \b Add \c{{evex}}, \c{{vex3}} and \c{{vex2}} instruction prefixes to
 have NASM encode the corresponding instruction, if possible, with an EVEX,
 3-byte VEX, or 2-byte VEX prefix, respectively.
diff --git a/doc/nasmdoc.src b/doc/nasmdoc.src
index dbf8e70..55a6313 100644
--- a/doc/nasmdoc.src
+++ b/doc/nasmdoc.src
@@ -4471,6 +4471,9 @@ be used.
 \c{DEFAULT NOBND} can disable \c{DEFAULT BND} and then \c{BND} prefix will be
 added only when explicitly specified in code.
 
+\c{DEFAULT BND} is expected to be the normal configuration for writing
+MPX-enabled code.
+
 \H{section} \i\c{SECTION} or \i\c{SEGMENT}: Changing and \i{Defining
 Sections}
 

[nasm:master] NASM 2.11

[nasm-bot f. H. P. A. <hp...@zy...>]

Commit-ID:  af10bfe167d6dac990b25b4b88aafb9f6709fb20
Gitweb:     http://repo.or.cz/w/nasm.git?a=commitdiff;h=af10bfe167d6dac990b25b4b88aafb9f6709fb20
Author:     H. Peter Anvin <hp...@zy...>
AuthorDate: Tue, 31 Dec 2013 10:40:10 -0800
Committer:  H. Peter Anvin <hp...@zy...>
CommitDate: Tue, 31 Dec 2013 10:40:10 -0800

NASM 2.11



---
 version | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/version b/version
index 7c27acc..6a5fe6e 100644
--- a/version
+++ b/version
@@ -1 +1 @@
-2.11rc4
+2.11

[nasm:master] mpx: Clean up instruction data

[nasm-bot f. J. K. S. <jin...@in...>]

Commit-ID:  b0c729baeb2de639ff79951d976817dd6414a0a5
Gitweb:     http://repo.or.cz/w/nasm.git?a=commitdiff;h=b0c729baeb2de639ff79951d976817dd6414a0a5
Author:     Jin Kyu Song <jin...@in...>
AuthorDate: Wed, 18 Dec 2013 21:31:51 -0800
Committer:  Jin Kyu Song <jin...@in...>
CommitDate: Wed, 18 Dec 2013 22:37:36 -0800

mpx: Clean up instruction data

Cleaned up unneccessary size specifiers in the instruction data.

Signed-off-by: Jin Kyu Song <jin...@in...>


---
 insns.dat    | 42 ++++++++++++++++++++++--------------------
 test/mpx.asm |  1 +
 2 files changed, 23 insertions(+), 20 deletions(-)

diff --git a/insns.dat b/insns.dat
index 34136c4..7125749 100644
--- a/insns.dat
+++ b/insns.dat
@@ -4100,26 +4100,28 @@ VSCATTERPF1QPS  zmem32|mask  [m:t1s:    vsibz evex.512.66.0f38.w0 c7 /6 ]  AVX51
 PREFETCHWT1     mem8         [m:                               0f 0d /2 ]  PREFETCHWT1,FUTURE
 
 ; MPX instructions
-BNDMK       bndreg,mem32           [rm:     o32 f3 0f 1b /r ]  MPX,SD,FUTURE
-BNDMK       bndreg,mem64           [rm:   o64nw f3 0f 1b /r ]  MPX,SQ,FUTURE
-BNDCL       bndreg,rm32            [rm:     o32 f3 0f 1a /r ]  MPX,SD,FUTURE
-BNDCL       bndreg,rm64            [rm:   o64nw f3 0f 1a /r ]  MPX,SQ,FUTURE
-BNDCU       bndreg,rm32            [rm:     o32 f2 0f 1a /r ]  MPX,SD,FUTURE
-BNDCU       bndreg,rm64            [rm:   o64nw f2 0f 1a /r ]  MPX,SQ,FUTURE
-BNDCN       bndreg,rm32            [rm:     o32 f2 0f 1b /r ]  MPX,SD,FUTURE
-BNDCN       bndreg,rm64            [rm:   o64nw f2 0f 1b /r ]  MPX,SQ,FUTURE
-BNDMOV      bndreg,bndrm64         [rm:         66 0f 1a /r ]  MPX,SQ,FUTURE
-BNDMOV      bndreg,bndrm128        [rm:         66 0f 1a /r ]  MPX,SO,FUTURE
-BNDMOV      bndrm64,bndreg         [mr:         66 0f 1b /r ]  MPX,SQ,FUTURE
-BNDMOV      bndrm128,bndreg        [mr:         66 0f 1b /r ]  MPX,SO,FUTURE
-BNDLDX      bndreg,mem128          [rm:            0f 1a /r ]  MPX,MIB,FUTURE
-BNDLDX      bndreg,mem128,reg64    [rmx:           0f 1a /r ]  MPX,MIB,FUTURE
-BNDSTX      mem64,bndreg           [mr:            0f 1b /r ]  MPX,MIB,SQ,FUTURE
-BNDSTX      mem64,reg32,bndreg     [mxr:           0f 1b /r ]  MPX,MIB,FUTURE
-BNDSTX      mem64,bndreg,reg32     [mrx:           0f 1b /r ]  MPX,MIB,FUTURE
-BNDSTX      mem128,bndreg          [mr:            0f 1b /r ]  MPX,MIB,SO,FUTURE
-BNDSTX      mem128,reg64,bndreg    [mxr:           0f 1b /r ]  MPX,MIB,FUTURE
-BNDSTX      mem128,bndreg,reg64    [mrx:           0f 1b /r ]  MPX,MIB,FUTURE
+BNDMK       bndreg,mem             [rm:         f3 0f 1b /r ]  MPX,MIB,FUTURE
+BNDCL       bndreg,mem             [rm:         f3 0f 1a /r ]  MPX,FUTURE
+BNDCL       bndreg,reg32           [rm:         f3 0f 1a /r ]  MPX,NOLONG,FUTURE
+BNDCL       bndreg,reg64           [rm:   o64nw f3 0f 1a /r ]  MPX,LONG,FUTURE
+BNDCU       bndreg,mem             [rm:         f2 0f 1a /r ]  MPX,FUTURE
+BNDCU       bndreg,reg32           [rm:         f2 0f 1a /r ]  MPX,NOLONG,FUTURE
+BNDCU       bndreg,reg64           [rm:   o64nw f2 0f 1a /r ]  MPX,LONG,FUTURE
+BNDCN       bndreg,mem             [rm:         f2 0f 1b /r ]  MPX,FUTURE
+BNDCN       bndreg,reg32           [rm:         f2 0f 1b /r ]  MPX,NOLONG,FUTURE
+BNDCN       bndreg,reg64           [rm:   o64nw f2 0f 1b /r ]  MPX,LONG,FUTURE
+BNDMOV      bndreg,bndreg          [rm:         66 0f 1a /r ]  MPX,FUTURE
+BNDMOV      bndreg,mem             [rm:         66 0f 1a /r ]  MPX,FUTURE
+BNDMOV      bndreg,bndreg          [mr:         66 0f 1b /r ]  MPX,FUTURE
+BNDMOV      mem,bndreg             [mr:         66 0f 1b /r ]  MPX,FUTURE
+BNDLDX      bndreg,mem             [rm:            0f 1a /r ]  MPX,MIB,FUTURE
+BNDLDX      bndreg,mem,reg32       [rmx:           0f 1a /r ]  MPX,MIB,NOLONG,FUTURE
+BNDLDX      bndreg,mem,reg64       [rmx:           0f 1a /r ]  MPX,MIB,LONG,FUTURE
+BNDSTX      mem,bndreg             [mr:            0f 1b /r ]  MPX,MIB,FUTURE
+BNDSTX      mem,reg32,bndreg       [mxr:           0f 1b /r ]  MPX,MIB,NOLONG,FUTURE
+BNDSTX      mem,reg64,bndreg       [mxr:           0f 1b /r ]  MPX,MIB,LONG,FUTURE
+BNDSTX      mem,bndreg,reg32       [mrx:           0f 1b /r ]  MPX,MIB,NOLONG,FUTURE
+BNDSTX      mem,bndreg,reg64       [mrx:           0f 1b /r ]  MPX,MIB,LONG,FUTURE
 
 ; SHA instructions
 SHA1RNDS4   xmmreg,xmmrm128,imm8    [rmi:    0f 3a cc /r ib ]    SHA,FUTURE
diff --git a/test/mpx.asm b/test/mpx.asm
index 1fd5b1d..4e98156 100644
--- a/test/mpx.asm
+++ b/test/mpx.asm
@@ -74,6 +74,7 @@ BITS 32
 	bndldx bnd2, [ecx*1]
 	bndldx bnd3, [edx+0x399]
 	bndldx bnd2, [1*ebx+3]
+	bndldx bnd2, [3], ebx
 	bndldx bnd1, [edx]
 
 	; bnd

[nasm:master] mib: Avoid RIP-relative addressing in mib

[nasm-bot f. J. K. S. <jin...@in...>]

Commit-ID:  97f6faec62979ef5db9c0f4b42e127f4f913115e
Gitweb:     http://repo.or.cz/w/nasm.git?a=commitdiff;h=97f6faec62979ef5db9c0f4b42e127f4f913115e
Author:     Jin Kyu Song <jin...@in...>
AuthorDate: Wed, 18 Dec 2013 21:28:17 -0800
Committer:  Jin Kyu Song <jin...@in...>
CommitDate: Wed, 18 Dec 2013 22:27:47 -0800

mib: Avoid RIP-relative addressing in mib

Using RIP relative for mib operands causes #UD exception.

Signed-off-by: Jin Kyu Song <jin...@in...>


---
 assemble.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/assemble.c b/assemble.c
index 4ff9e25..9184800 100644
--- a/assemble.c
+++ b/assemble.c
@@ -2426,6 +2426,12 @@ static enum ea_type process_ea(operand *input, ea *output, int bits,
                 input->type |= MEMORY;
             }
 
+            if (bits == 64 &&
+                !(IP_REL & ~input->type) && (eaflags & EAF_MIB)) {
+                nasm_error(ERR_NONFATAL, "RIP-relative addressing is prohibited for mib.");
+                return -1;
+            }
+
             if (eaflags & EAF_BYTEOFFS ||
                 (eaflags & EAF_WORDOFFS &&
                  input->disp_size != (addrbits != 16 ? 32 : 16))) {

[nasm:master] nosplit: Limit the effect of NOSPLIT

[nasm-bot f. J. K. S. <jin...@in...>]

Commit-ID:  3d06af2bd998cd06c99b7e63a8166a11f7ac798f
Gitweb:     http://repo.or.cz/w/nasm.git?a=commitdiff;h=3d06af2bd998cd06c99b7e63a8166a11f7ac798f
Author:     Jin Kyu Song <jin...@in...>
AuthorDate: Wed, 18 Dec 2013 21:28:41 -0800
Committer:  Jin Kyu Song <jin...@in...>
CommitDate: Wed, 18 Dec 2013 22:37:30 -0800

nosplit: Limit the effect of NOSPLIT

[nosplit eax+eax] was encoded [eax*2] previously but
this seems against the user's intention.
So in this case, nosplit is ignored now and [eax+eax] will be
generated.
Document is also updated accordingly.

Signed-off-by: Jin Kyu Song <jin...@in...>


---
 assemble.c      | 2 +-
 doc/nasmdoc.src | 6 ++++--
 2 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/assemble.c b/assemble.c
index 9184800..fbd7caf 100644
--- a/assemble.c
+++ b/assemble.c
@@ -2629,7 +2629,7 @@ static enum ea_type process_ea(operand *input, ea *output, int bits,
                     }
                 } else {
                     if (((s == 2 && it != REG_NUM_ESP &&
-                          !(eaflags & EAF_TIMESTWO)) ||
+                          (!(eaflags & EAF_TIMESTWO) || (ht == EAH_SUMMED))) ||
                          s == 3 || s == 5 || s == 9) && bt == -1) {
                         /* convert 3*EAX to EAX+2*EAX */
                         bt = it, bx = ix, s--;
diff --git a/doc/nasmdoc.src b/doc/nasmdoc.src
index 327e3cf..8554a34 100644
--- a/doc/nasmdoc.src
+++ b/doc/nasmdoc.src
@@ -1460,6 +1460,8 @@ fact, it will also split \c{[eax*2+offset]} into
 \c{[eax+eax+offset]}. You can combat this behaviour by the use of
 the \c{NOSPLIT} keyword: \c{[nosplit eax*2]} will force
 \c{[eax*2+0]} to be generated literally.
+However, \c{NOSPLIT} in \c{[nosplit eax+eax]} will be ignored because user's
+intention here is considered as \c{[eax+eax]}.
 
 In 64-bit mode, NASM will by default generate absolute addresses.  The
 \i\c{REL} keyword makes it produce \c{RIP}-relative addresses. Since
@@ -4465,8 +4467,8 @@ be used.
 \c      call foo            ; BND will be prefixed
 \c      nobnd call foo      ; BND will NOT be prefixed
 
-DEFAULT NOBND can disable DEFAULT BND and then \c{BND} prefix will be added
-only when explicitly specified in code.
+\c{DEFAULT NOBND} can disable \c{DEFAULT BND} and then \c{BND} prefix will be
+added only when explicitly specified in code.
 
 \H{section} \i\c{SECTION} or \i\c{SEGMENT}: Changing and \i{Defining
 Sections}

[nasm:master] nosplit: Generate index-only EA only when a multiplier is used.

[nasm-bot f. J. K. S. <jin...@in...>]

Commit-ID:  26ddad67ca57bb45e2bd45740309265ed2a9502d
Gitweb:     http://repo.or.cz/w/nasm.git?a=commitdiff;h=26ddad67ca57bb45e2bd45740309265ed2a9502d
Author:     Jin Kyu Song <jin...@in...>
AuthorDate: Wed, 18 Dec 2013 22:01:14 -0800
Committer:  Jin Kyu Song <jin...@in...>
CommitDate: Wed, 18 Dec 2013 22:38:44 -0800

nosplit: Generate index-only EA only when a multiplier is used.

[nosplit eax] has been encoded as [eax*1+0] since 0.98.34.
But this seems like unexpected behavior.
So only when a register is multiplied, that will be treated
as an index. ([nosplit eax*1] -> [eax*1+0])
Document is updated accordingly.

Signed-off-by: Jin Kyu Song <jin...@in...>


---
 assemble.c      | 5 +++--
 doc/nasmdoc.src | 3 ++-
 2 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/assemble.c b/assemble.c
index fbd7caf..eeab9bb 100644
--- a/assemble.c
+++ b/assemble.c
@@ -2635,9 +2635,10 @@ static enum ea_type process_ea(operand *input, ea *output, int bits,
                         bt = it, bx = ix, s--;
                     }
                     if (it == -1 && (bt & 7) != REG_NUM_ESP &&
-                        (eaflags & EAF_TIMESTWO)) {
+                        (eaflags & EAF_TIMESTWO) &&
+                        (hb == b && ht == EAH_NOTBASE)) {
                         /*
-                         * convert [NOSPLIT EAX]
+                         * convert [NOSPLIT EAX*1]
                          * to sib format with 0x0 displacement - [EAX*1+0].
                          */
                         it = bt, ix = bx, bt = -1, bx = 0, s = 1;
diff --git a/doc/nasmdoc.src b/doc/nasmdoc.src
index 8554a34..dbf8e70 100644
--- a/doc/nasmdoc.src
+++ b/doc/nasmdoc.src
@@ -1459,7 +1459,8 @@ that allows the offset field to be absent and space to be saved; in
 fact, it will also split \c{[eax*2+offset]} into
 \c{[eax+eax+offset]}. You can combat this behaviour by the use of
 the \c{NOSPLIT} keyword: \c{[nosplit eax*2]} will force
-\c{[eax*2+0]} to be generated literally.
+\c{[eax*2+0]} to be generated literally. \c{[nosplit eax*1]} also has the
+same effect. In another way, a split EA form \c{[0, eax*2]} can be used, too.
 However, \c{NOSPLIT} in \c{[nosplit eax+eax]} will be ignored because user's
 intention here is considered as \c{[eax+eax]}.
 

[nasm:master] insns: Mark LOADALL, LOADALL286 with ND flag

[nasm-bot f. C. G. <gor...@gm...>]

Commit-ID:  0b900cc7e1f197364fd3919f7050bf4dd10d112c
Gitweb:     http://repo.or.cz/w/nasm.git?a=commitdiff;h=0b900cc7e1f197364fd3919f7050bf4dd10d112c
Author:     Cyrill Gorcunov <gor...@gm...>
AuthorDate: Fri, 13 Dec 2013 10:59:39 +0400
Committer:  Cyrill Gorcunov <gor...@gm...>
CommitDate: Fri, 13 Dec 2013 11:00:43 +0400

insns: Mark LOADALL, LOADALL286 with ND flag

Otherwise disassembler treat syscall, sysret incorrectly.

Signed-off-by: Cyrill Gorcunov <gor...@gm...>


---
 insns.dat | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/insns.dat b/insns.dat
index 156abfd..34136c4 100644
--- a/insns.dat
+++ b/insns.dat
@@ -751,8 +751,8 @@ LLDT		reg16				[m:	0f 00 /2]				286,PROT,PRIV
 LMSW		mem				[m:	0f 01 /6]				286,PRIV
 LMSW		mem16				[m:	0f 01 /6]				286,PRIV
 LMSW		reg16				[m:	0f 01 /6]				286,PRIV
-LOADALL		void				[	0f 07]					386,UNDOC
-LOADALL286	void				[	0f 05]					286,UNDOC
+LOADALL		void				[	0f 07]					386,UNDOC,ND
+LOADALL286	void				[	0f 05]					286,UNDOC,ND
 LODSB		void				[	ac]					8086
 LODSD		void				[	o32 ad]					386
 LODSQ		void				[	o64 ad]					X64

[nasm:master] mib: Handle MIB EA in a different way from regular EA's

[nasm-bot f. J. K. S. <jin...@in...>]

Commit-ID:  4360ba28f0e4767ffe28ef3a037aaa103b5660b6
Gitweb:     http://repo.or.cz/w/nasm.git?a=commitdiff;h=4360ba28f0e4767ffe28ef3a037aaa103b5660b6
Author:     Jin Kyu Song <jin...@in...>
AuthorDate: Tue, 10 Dec 2013 16:24:45 -0800
Committer:  Jin Kyu Song <jin...@in...>
CommitDate: Wed, 11 Dec 2013 16:56:19 -0800

mib: Handle MIB EA in a different way from regular EA's

In mib operands, users' intention should be preserved.
e.g.) [eax + eax*1] and [eax*2] must be distinguished and encoded differently.

So  a new EA flag EAF_MIB for mib operands is added.
And a new EA hint EAH_SUMMED for the case of [eax+eax*4] being parsed
as [eax*5] is also added.

NOSPLIT specifier does not have an effect in mib, so [nosplit eax + eax*1]
will be encoded as [eax, eax] rather than [eax*2] as in a regular EA.

Signed-off-by: Jin Kyu Song <jin...@in...>


---
 assemble.c | 85 ++++++++++++++++++++++++++++++++++++--------------------------
 eval.c     |  5 +++-
 nasm.h     |  6 +++--
 3 files changed, 57 insertions(+), 39 deletions(-)

diff --git a/assemble.c b/assemble.c
index bdf9a10..4ff9e25 100644
--- a/assemble.c
+++ b/assemble.c
@@ -1231,27 +1231,18 @@ static int64_t calcsize(int32_t segment, int64_t offset, int bits,
                     }
                 }
 
-                /*
-                 * if a separate form of MIB (ICC style) is used,
-                 * the index reg info is merged into mem operand
-                 */
-                if (mib_index != R_none) {
-                    opy->indexreg = mib_index;
-                    opy->scale = 1;
-                    opy->hintbase = mib_index;
-                    opy->hinttype = EAH_NOTBASE;
-                }
-
-                /*
-                 * only for mib operands, make a single reg index [reg*1].
-                 * gas uses this form to explicitly denote index register.
-                 */
-                if (itemp_has(temp, IF_MIB) &&
-                    (opy->indexreg == -1 && opy->hintbase == opy->basereg &&
-                     opy->hinttype == EAH_NOTBASE)) {
-                    opy->indexreg = opy->basereg;
-                    opy->basereg  = -1;
-                    opy->scale    = 1;
+                if (itemp_has(temp, IF_MIB)) {
+                    opy->eaflags |= EAF_MIB;
+                    /*
+                     * if a separate form of MIB (ICC style) is used,
+                     * the index reg info is merged into mem operand
+                     */
+                    if (mib_index != R_none) {
+                        opy->indexreg = mib_index;
+                        opy->scale = 1;
+                        opy->hintbase = mib_index;
+                        opy->hinttype = EAH_NOTBASE;
+                    }
                 }
 
                 if (process_ea(opy, &ea_data, bits,
@@ -2379,6 +2370,7 @@ static enum ea_type process_ea(operand *input, ea *output, int bits,
 {
     bool forw_ref = !!(input->opflags & OPFLAG_UNKNOWN);
     int addrbits = ins->addr_size;
+    int eaflags = input->eaflags;
 
     output->type    = EA_SCALAR;
     output->rip     = false;
@@ -2434,8 +2426,8 @@ static enum ea_type process_ea(operand *input, ea *output, int bits,
                 input->type |= MEMORY;
             }
 
-            if (input->eaflags & EAF_BYTEOFFS ||
-                (input->eaflags & EAF_WORDOFFS &&
+            if (eaflags & EAF_BYTEOFFS ||
+                (eaflags & EAF_WORDOFFS &&
                  input->disp_size != (addrbits != 16 ? 32 : 16))) {
                 nasm_error(ERR_WARNING | ERR_PASS1, "displacement size ignored on absolute address");
             }
@@ -2556,7 +2548,7 @@ static enum ea_type process_ea(operand *input, ea *output, int bits,
                     base = (bt & 7);
                     if (base != REG_NUM_EBP && o == 0 &&
                         seg == NO_SEG && !forw_ref &&
-                        !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
+                        !(eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
                         mod = 0;
                     else if (IS_MOD_01())
                         mod = 1;
@@ -2611,19 +2603,40 @@ static enum ea_type process_ea(operand *input, ea *output, int bits,
                     t = bt, bt = it, it = t;
                     x = bx, bx = ix, ix = x;
                 }
-                if (bt == it)     /* convert EAX+2*EAX to 3*EAX */
-                    bt = -1, bx = 0, s++;
+
                 if (bt == -1 && s == 1 && !(hb == i && ht == EAH_NOTBASE)) {
                     /* make single reg base, unless hint */
                     bt = it, bx = ix, it = -1, ix = 0;
                 }
-                if (((s == 2 && it != REG_NUM_ESP && !(input->eaflags & EAF_TIMESTWO)) ||
-                      s == 3 || s == 5 || s == 9) && bt == -1)
-                    bt = it, bx = ix, s--; /* convert 3*EAX to EAX+2*EAX */
-                if (it == -1 && (bt & 7) != REG_NUM_ESP &&
-                    (input->eaflags & EAF_TIMESTWO))
-                    it = bt, ix = bx, bt = -1, bx = 0, s = 1;
-                /* convert [NOSPLIT EAX] to sib format with 0x0 displacement */
+                if (eaflags & EAF_MIB) {
+                    /* only for mib operands */
+                    if (it == -1 && (hb == b && ht == EAH_NOTBASE)) {
+                        /*
+                         * make a single reg index [reg*1].
+                         * gas uses this form for an explicit index register.
+                         */
+                        it = bt, ix = bx, bt = -1, bx = 0, s = 1;
+                    }
+                    if ((ht == EAH_SUMMED) && bt == -1) {
+                        /* separate once summed index into [base, index] */
+                        bt = it, bx = ix, s--;
+                    }
+                } else {
+                    if (((s == 2 && it != REG_NUM_ESP &&
+                          !(eaflags & EAF_TIMESTWO)) ||
+                         s == 3 || s == 5 || s == 9) && bt == -1) {
+                        /* convert 3*EAX to EAX+2*EAX */
+                        bt = it, bx = ix, s--;
+                    }
+                    if (it == -1 && (bt & 7) != REG_NUM_ESP &&
+                        (eaflags & EAF_TIMESTWO)) {
+                        /*
+                         * convert [NOSPLIT EAX]
+                         * to sib format with 0x0 displacement - [EAX*1+0].
+                         */
+                        it = bt, ix = bx, bt = -1, bx = 0, s = 1;
+                    }
+                }
                 if (s == 1 && it == REG_NUM_ESP) {
                     /* swap ESP into base if scale is 1 */
                     t = it, it = bt, bt = t;
@@ -2647,7 +2660,7 @@ static enum ea_type process_ea(operand *input, ea *output, int bits,
                         rm = (bt & 7);
                         if (rm != REG_NUM_EBP && o == 0 &&
                             seg == NO_SEG && !forw_ref &&
-                            !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
+                            !(eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
                             mod = 0;
                         else if (IS_MOD_01())
                             mod = 1;
@@ -2691,7 +2704,7 @@ static enum ea_type process_ea(operand *input, ea *output, int bits,
                         base = (bt & 7);
                         if (base != REG_NUM_EBP && o == 0 &&
                             seg == NO_SEG && !forw_ref &&
-                            !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
+                            !(eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
                             mod = 0;
                         else if (IS_MOD_01())
                             mod = 1;
@@ -2776,7 +2789,7 @@ static enum ea_type process_ea(operand *input, ea *output, int bits,
                     goto err;        /* so panic if it does */
 
                 if (o == 0 && seg == NO_SEG && !forw_ref && rm != 6 &&
-                    !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
+                    !(eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
                     mod = 0;
                 else if (IS_MOD_01())
                     mod = 1;
diff --git a/eval.c b/eval.c
index c57ff04..403a793 100644
--- a/eval.c
+++ b/eval.c
@@ -148,8 +148,11 @@ static expr *add_vectors(expr * p, expr * q)
             lasttype = p++->type;
         } else {                /* *p and *q have same type */
             int64_t sum = p->value + q->value;
-            if (sum)
+            if (sum) {
                 addtotemp(p->type, sum);
+                if (hint)
+                    hint->type = EAH_SUMMED;
+            }
             lasttype = p->type;
             p++, q++;
         }
diff --git a/nasm.h b/nasm.h
index 736c290..18de37c 100644
--- a/nasm.h
+++ b/nasm.h
@@ -584,13 +584,15 @@ enum ea_flags { /* special EA flags */
     EAF_TIMESTWO    =  4,   /* really do EAX*2 not EAX+EAX */
     EAF_REL         =  8,   /* IP-relative addressing */
     EAF_ABS         = 16,   /* non-IP-relative addressing */
-    EAF_FSGS        = 32    /* fs/gs segment override present */
+    EAF_FSGS        = 32,   /* fs/gs segment override present */
+    EAF_MIB         = 64,   /* mib operand */
 };
 
 enum eval_hint { /* values for `hinttype' */
     EAH_NOHINT   = 0,       /* no hint at all - our discretion */
     EAH_MAKEBASE = 1,       /* try to make given reg the base */
-    EAH_NOTBASE  = 2        /* try _not_ to make reg the base */
+    EAH_NOTBASE  = 2,       /* try _not_ to make reg the base */
+    EAH_SUMMED   = 3,       /* base and index are summed into index */
 };
 
 typedef struct operand { /* operand to an instruction */

[nasm:master] misc/release: Generate manpages

[nasm-bot f. H. P. A. <hp...@zy...>]

Commit-ID:  478f2dafff5b58c7c965cfe2277ff71e1492815a
Gitweb:     http://repo.or.cz/w/nasm.git?a=commitdiff;h=478f2dafff5b58c7c965cfe2277ff71e1492815a
Author:     H. Peter Anvin <hp...@zy...>
AuthorDate: Wed, 11 Dec 2013 12:09:09 -0800
Committer:  H. Peter Anvin <hp...@zy...>
CommitDate: Wed, 11 Dec 2013 12:10:27 -0800

misc/release: Generate manpages

asciidoc/xmlto are not tools we require every users to have, so each
tarball should contain them.  That means the release script needs to
know about them.

Signed-off-by: H. Peter Anvin <hp...@zy...>


---
 misc/release | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/misc/release b/misc/release
index 0abaf77..14e750a 100755
--- a/misc/release
+++ b/misc/release
@@ -42,7 +42,7 @@ rm -rf nasm/.git nasm/.gitignore
 cd nasm
 ./autogen.sh
 ./configure --prefix=/usr/local
-make perlreq spec
+make perlreq spec manpages
 make alldeps
 make distclean
 cd ..

[nasm:master] iflag: Don't use c99 array initialization

[nasm-bot f. C. G. <gor...@gm...>]

Commit-ID:  d578b511c936f35468f8c783db1237982ce3c0e1
Gitweb:     http://repo.or.cz/w/nasm.git?a=commitdiff;h=d578b511c936f35468f8c783db1237982ce3c0e1
Author:     Cyrill Gorcunov <gor...@gm...>
AuthorDate: Tue, 10 Dec 2013 11:09:49 +0400
Committer:  Cyrill Gorcunov <gor...@gm...>
CommitDate: Tue, 10 Dec 2013 11:10:19 +0400

iflag: Don't use c99 array initialization

It's sad but not all compilers support c99 features, so drop
off IFLAG_INIT helper.

Reported-by: H. Peter Anvin <hp...@zy...>
Signed-off-by: Cyrill Gorcunov <gor...@gm...>


---
 iflag.h | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/iflag.h b/iflag.h
index 583e68a..a3d9736 100644
--- a/iflag.h
+++ b/iflag.h
@@ -13,8 +13,6 @@ int ilog2_32(uint32_t v);
 
 #define IF_GENBIT(bit)          (UINT32_C(1) << (bit))
 
-#define IFLAG_INIT              (iflag_t){ .field = { 0 }, }
-
 static inline unsigned int iflag_test(const iflag_t *f, unsigned int bit)
 {
     unsigned int index = bit / 32;
@@ -145,7 +143,9 @@ static inline int iflag_cmp_cpu_level(const iflag_t *a, const iflag_t *b)
 
 static inline iflag_t _iflag_pfmask(const iflag_t *a)
 {
-    iflag_t r = IFLAG_INIT;
+    iflag_t r;
+
+    iflag_clear_all(&r);
 
     if (iflag_test(a, IF_CYRIX))
         iflag_set(&r, IF_CYRIX);

[nasm:master] insns-iflags: Drop occasionally introduced \Tab's

[nasm-bot f. C. G. <gor...@gm...>]

Commit-ID:  f8d12d5011f16730da919b437e245a80b7054683
Gitweb:     http://repo.or.cz/w/nasm.git?a=commitdiff;h=f8d12d5011f16730da919b437e245a80b7054683
Author:     Cyrill Gorcunov <gor...@gm...>
AuthorDate: Sat, 7 Dec 2013 16:15:03 +0400
Committer:  Cyrill Gorcunov <gor...@gm...>
CommitDate: Sat, 7 Dec 2013 16:15:03 +0400

insns-iflags: Drop occasionally introduced \Tab's

Signed-off-by: Cyrill Gorcunov <gor...@gm...>


---
 insns-iflags.pl | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/insns-iflags.pl b/insns-iflags.pl
index 97c0863..cd8f8f1 100644
--- a/insns-iflags.pl
+++ b/insns-iflags.pl
@@ -192,7 +192,7 @@ sub insns_flag_index(@) {
         }
 
 	my $str = join(',', map { sprintf("UINT32_C(0x%08x)",$_) } @newkey);
-	
+
         push @insns_flag_values, $str;
         $insns_flag_hash{$key} = $#insns_flag_values;
     }
@@ -221,7 +221,7 @@ sub write_iflaggen_h() {
 
     print N "\n";
     printf N "extern const iflag_t insns_flags[%d];\n\n",
-    	$#insns_flag_values + 1;
+	$#insns_flag_values + 1;
 
     print N "#endif /* NASM_IFLAGGEN_H */\n";
     close N;

[nasm:master] iflag: Introduce IFLAG_INIT helper

[nasm-bot f. C. G. <gor...@gm...>]

Commit-ID:  71f71c0dbe204d8d6a58e695c038bf0508d3b406
Gitweb:     http://repo.or.cz/w/nasm.git?a=commitdiff;h=71f71c0dbe204d8d6a58e695c038bf0508d3b406
Author:     Cyrill Gorcunov <gor...@gm...>
AuthorDate: Sat, 7 Dec 2013 16:12:07 +0400
Committer:  Cyrill Gorcunov <gor...@gm...>
CommitDate: Sat, 7 Dec 2013 16:12:07 +0400

iflag: Introduce IFLAG_INIT helper

Signed-off-by: Cyrill Gorcunov <gor...@gm...>


---
 iflag.h | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/iflag.h b/iflag.h
index 7bc31cc..66e340e 100644
--- a/iflag.h
+++ b/iflag.h
@@ -13,6 +13,8 @@ int ilog2_32(uint32_t v);
 
 #define IF_GENBIT(bit)          (UINT32_C(1) << (bit))
 
+#define IFLAG_INIT              (iflag_t){ .field = { 0 }, }
+
 static inline unsigned int iflag_test(const iflag_t *f, unsigned int bit)
 {
     unsigned int index = bit / 32;
@@ -143,9 +145,7 @@ static inline int iflag_cmp_cpu_level(const iflag_t *a, const iflag_t *b)
 
 static inline iflag_t _iflag_pfmask(const iflag_t *a)
 {
-	iflag_t r;
-
-	memset(&r, 0, sizeof(r));
+	iflag_t r = IFLAG_INIT;
 
 	if (iflag_test(a, IF_CYRIX))
 		iflag_set(&r, IF_CYRIX);

[nasm:master] NASM 2.11rc4

[nasm-bot f. H. P. A. <hp...@zy...>]

Commit-ID:  20df33d2a5f325cb2f89103b2fe0e98773cf5854
Gitweb:     http://repo.or.cz/w/nasm.git?a=commitdiff;h=20df33d2a5f325cb2f89103b2fe0e98773cf5854
Author:     H. Peter Anvin <hp...@zy...>
AuthorDate: Thu, 5 Dec 2013 00:06:45 -0800
Committer:  H. Peter Anvin <hp...@zy...>
CommitDate: Thu, 5 Dec 2013 00:06:45 -0800

NASM 2.11rc4



---
 version | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/version b/version
index 2a8ed36..7c27acc 100644
--- a/version
+++ b/version
@@ -1 +1 @@
-2.11rc3
+2.11rc4

[nasm:master] bnd: Add a new nobnd prefix

[nasm-bot f. J. K. S. <jin...@in...>]

Commit-ID:  b287ff0ddbfb997663ca9432ca3456e3d15ae9ed
Gitweb:     http://repo.or.cz/w/nasm.git?a=commitdiff;h=b287ff0ddbfb997663ca9432ca3456e3d15ae9ed
Author:     Jin Kyu Song <jin...@in...>
AuthorDate: Wed, 4 Dec 2013 20:05:55 -0800
Committer:  Jin Kyu Song <jin...@in...>
CommitDate: Wed, 4 Dec 2013 20:10:08 -0800

bnd: Add a new nobnd prefix

bnd and nobnd prifixes can be used for each instruction line to
direct whether bnd registers should be preserved or not.

And those are also added as options for DEFAULT directive.
Once bnd is set with default, DEFAULT BND, all bnd-prefix
available instructions are prefixed with bnd. To override it,
nobnd prefix can be used.

In the other way, DEFAULT NOBND can disable DEFAULT BND and
have nasm encode in the normal way.

Signed-off-by: Jin Kyu Song <jin...@in...>


---
 assemble.c   | 27 +++++++++++++++++++++++++--
 nasm.c       |  9 ++++++++-
 nasm.h       |  2 ++
 parser.c     |  1 +
 standard.mac | 13 +++++++++++++
 tokens.dat   |  1 +
 6 files changed, 50 insertions(+), 3 deletions(-)

diff --git a/assemble.c b/assemble.c
index f06cee8..bdf9a10 100644
--- a/assemble.c
+++ b/assemble.c
@@ -196,6 +196,7 @@ enum match_result {
     MERR_BADHLE,
     MERR_ENCMISMATCH,
     MERR_BADBND,
+    MERR_BADREPNE,
     /*
      * Matching success; the conditional ones first
      */
@@ -647,6 +648,7 @@ int64_t assemble(int32_t segment, int64_t offset, int bits, iflag_t cp,
                     case P_EVEX:
                     case P_VEX3:
                     case P_VEX2:
+                    case P_NOBND:
                     case P_none:
                         break;
                     default:
@@ -700,6 +702,11 @@ int64_t assemble(int32_t segment, int64_t offset, int bits, iflag_t cp,
         case MERR_BADBND:
             error(ERR_NONFATAL, "bnd prefix is not allowed");
             break;
+        case MERR_BADREPNE:
+            error(ERR_NONFATAL, "%s prefix is not allowed",
+                  (has_prefix(instruction, PPS_REP, P_REPNE) ?
+                   "repne" : "repnz"));
+            break;
         default:
             error(ERR_NONFATAL,
                   "invalid combination of opcode and operands");
@@ -814,6 +821,7 @@ int64_t insn_size(int32_t segment, int64_t offset, int bits, iflag_t cp,
             case P_EVEX:
             case P_VEX3:
             case P_VEX2:
+            case P_NOBND:
             case P_none:
                 break;
             default:
@@ -1351,6 +1359,15 @@ static int64_t calcsize(int32_t segment, int64_t offset, int bits,
 
     bad_hle_warn(ins, hleok);
 
+    /*
+     * when BND prefix is set by DEFAULT directive,
+     * BND prefix is added to every appropriate instruction line
+     * unless it is overridden by NOBND prefix.
+     */
+    if (globalbnd &&
+        (itemp_has(temp, IF_BND) && !has_prefix(ins, PPS_REP, P_NOBND)))
+            ins->prefixes[PPS_REP] = P_BND;
+
     return length;
 }
 
@@ -2328,11 +2345,17 @@ static enum match_result matches(const struct itemplate *itemp,
         return MOK_JUMP;
 
     /*
-     * Check if BND prefix is allowed
+     * Check if BND prefix is allowed.
+     * Other 0xF2 (REPNE/REPNZ) prefix is prohibited.
      */
     if (!itemp_has(itemp, IF_BND) &&
-        has_prefix(instruction, PPS_REP, P_BND))
+        (has_prefix(instruction, PPS_REP, P_BND) ||
+         has_prefix(instruction, PPS_REP, P_NOBND)))
         return MERR_BADBND;
+    else if (itemp_has(itemp, IF_BND) &&
+             (has_prefix(instruction, PPS_REP, P_REPNE) ||
+              has_prefix(instruction, PPS_REP, P_REPNZ)))
+        return MERR_BADREPNE;
 
     return MOK_GOOD;
 }
diff --git a/nasm.c b/nasm.c
index d10ddbc..2bb3029 100644
--- a/nasm.c
+++ b/nasm.c
@@ -89,6 +89,7 @@ bool tasm_compatible_mode = false;
 int pass0, passn;
 int maxbits = 0;
 int globalrel = 0;
+int globalbnd = 0;
 
 static time_t official_compile_time;
 
@@ -1525,7 +1526,7 @@ static void assemble_file(char *fname, StrList **depend_ptr)
                     stdscan_reset();
                     stdscan_set(value);
                     tokval.t_type = TOKEN_INVALID;
-                    if (stdscan(NULL, &tokval) == TOKEN_SPECIAL) {
+                    if (stdscan(NULL, &tokval) != TOKEN_INVALID) {
                         switch ((int)tokval.t_integer) {
                         case S_REL:
                             globalrel = 1;
@@ -1533,6 +1534,12 @@ static void assemble_file(char *fname, StrList **depend_ptr)
                         case S_ABS:
                             globalrel = 0;
                             break;
+                        case P_BND:
+                            globalbnd = 1;
+                            break;
+                        case P_NOBND:
+                            globalbnd = 0;
+                            break;
                         default:
                             err = 1;
                             break;
diff --git a/nasm.h b/nasm.h
index f499c49..736c290 100644
--- a/nasm.h
+++ b/nasm.h
@@ -564,6 +564,7 @@ enum prefixes { /* instruction prefixes */
     P_XACQUIRE,
     P_XRELEASE,
     P_BND,
+    P_NOBND,
     P_EVEX,
     P_VEX3,
     P_VEX2,
@@ -1172,6 +1173,7 @@ extern bool tasm_compatible_mode;
 extern int optimizing;
 extern int globalbits;          /* 16, 32 or 64-bit mode */
 extern int globalrel;           /* default to relative addressing? */
+extern int globalbnd;           /* default to using bnd prefix? */
 extern int maxbits;             /* max bits supported by output */
 
 /*
diff --git a/parser.c b/parser.c
index 4f0898c..2d8d4ff 100644
--- a/parser.c
+++ b/parser.c
@@ -90,6 +90,7 @@ static int prefix_slot(int prefix)
     case P_XACQUIRE:
     case P_XRELEASE:
     case P_BND:
+    case P_NOBND:
         return PPS_REP;
     case P_O16:
     case P_O32:
diff --git a/standard.mac b/standard.mac
index b2dff8d..60c0387 100644
--- a/standard.mac
+++ b/standard.mac
@@ -205,6 +205,19 @@
     [default %1]
 %endmacro
 
+%imacro userel 0.nolist
+    [default rel]
+%endmacro
+%imacro useabs 0.nolist
+    [default abs]
+%endmacro
+%imacro usebnd 0.nolist
+    [default bnd]
+%endmacro
+%imacro usenobnd 0.nolist
+    [default nobnd]
+%endmacro
+
 %imacro incbin 1-2+.nolist 0
     %push
         %pathsearch %$dep %1
diff --git a/tokens.dat b/tokens.dat
index 09d4b9f..0e44641 100644
--- a/tokens.dat
+++ b/tokens.dat
@@ -55,6 +55,7 @@ wait
 xacquire
 xrelease
 bnd
+nobnd
 
 % TOKEN_SPECIAL, 0, 0, S_*
 abs

[nasm:master] bnd: Show warning when bnd prefix is dropped

[nasm-bot f. J. K. S. <jin...@in...>]

Commit-ID:  bb8cf3fa77e63f7c6a02d23bbfe3426beff26358
Gitweb:     http://repo.or.cz/w/nasm.git?a=commitdiff;h=bb8cf3fa77e63f7c6a02d23bbfe3426beff26358
Author:     Jin Kyu Song <jin...@in...>
AuthorDate: Fri, 29 Nov 2013 00:38:29 -0800
Committer:  Jin Kyu Song <jin...@in...>
CommitDate: Wed, 4 Dec 2013 20:06:23 -0800

bnd: Show warning when bnd prefix is dropped

When bnd prefix is dropped as jmp is encoded as jmp short,
nasm shows a warning message, which can be suppressed with a new
command line option, -w-bnd.

Signed-off-by: Jin Kyu Song <jin...@in...>


---
 assemble.c | 2 ++
 nasm.c     | 1 +
 nasmlib.h  | 3 ++-
 3 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/assemble.c b/assemble.c
index bf1490d..f06cee8 100644
--- a/assemble.c
+++ b/assemble.c
@@ -385,6 +385,8 @@ static bool jmp_match(int32_t segment, int64_t offset, int bits,
     if (is_byte && c == 0371 && ins->prefixes[PPS_REP] == P_BND) {
         /* jmp short (opcode eb) cannot be used with bnd prefix. */
         ins->prefixes[PPS_REP] = P_none;
+        errfunc(ERR_WARNING | ERR_WARN_BND | ERR_PASS2 ,
+                "jmp short does not init bnd regs - bnd prefix dropped.");
     }
 
     return is_byte;
diff --git a/nasm.c b/nasm.c
index b83810d..d10ddbc 100644
--- a/nasm.c
+++ b/nasm.c
@@ -166,6 +166,7 @@ static const struct warning {
     {"user", "%warning directives", true},
     {"lock", "lock prefix on unlockable instructions", true},
     {"hle", "invalid hle prefixes", true},
+    {"bnd", "invalid bnd prefixes", true},
 };
 
 static bool want_usage;
diff --git a/nasmlib.h b/nasmlib.h
index 2210748..d11e6e0 100644
--- a/nasmlib.h
+++ b/nasmlib.h
@@ -134,7 +134,8 @@ void nasm_set_verror(vefunc);
 #define ERR_WARN_USER           WARN(11) /* %warning directives */
 #define ERR_WARN_LOCK		WARN(12) /* bad LOCK prefixes */
 #define ERR_WARN_HLE		WARN(13) /* bad HLE prefixes */
-#define ERR_WARN_MAX            13       /* the highest numbered one */
+#define ERR_WARN_BND		WARN(14) /* bad BND prefixes */
+#define ERR_WARN_MAX            14       /* the highest numbered one */
 
 /*
  * Wrappers around malloc, realloc and free. nasm_malloc will