myhdl-list — Mailing list for discussions on MyHDL

Re: [myhdl-list] Error in Intbv class?

[Christopher F. <chr...@gm...>]

On 3/3/2016 1:19 PM, Forumulator Bing wrote:
> True, because the value wrapped by the class is still a standard
> unconstrained int. Thus, accessing something like:
>
>>> a=intbv(5)[4:] a[6]
> false
>
> Where as it should raise an out of bounds exception.Can someone
> comment on this so that I could possibly try to fix this.

I don't know if this was an original design decision
to allow the out of index range access to occur?  It does
return the correct value for the position if you imagine
it was sign-extended.

     >>> a = intbv(0)[8:]
     >>> b = intbv(-1, min=-1000, max=1000)
     >>> print("{:1d} and {:1d}".format(a[1000000], b[1000000]))
     0 and 1

But with that said, it seems like we are missing an
opportunity to flag errors, especially since one off
errors are so common.

You might need to wait for Jan D. to comment or someone
else that might know the history (or someone with strong
feelings one way or the other :)

Regards,
Chris

Re: [myhdl-list] Error in Intbv class?

[Forumulator B. <for...@gm...>]

True, because the value wrapped by the class is still a standard
unconstrained int. Thus, accessing something like:

>>a=intbv(5)[4:]
>>a[6]
false

Where as it should raise an out of bounds exception.Can someone comment on
this so that I could possibly try to fix this.

While we're on the topic, i also think that the __setitem__ method should
be seperately implemented for modbv too, so that wrap around behaviour can
be extended to slices of an object. For example.

>>a=modbv(5)[4:]
>>a[4:1]=20

should give a value of 12 for a instead of giving an error. Are these
issues trivial?

On Thu, Mar 3, 2016 at 8:35 PM, Samuele Disegna <sm...@gm...> wrote:

> Hi again, while analyzing the _intbv code I noticed a related problem:
>
> An Exception is Not risen when accessing a out of bound bit of a
> constrained intbv.
> This seems a real problem to me.
>
> I tested it by using the example code at
> http://docs.myhdl.org/en/stable/manual/hwtypes.html#bit-indexing and
> modifing it for using a constrained intbv:
>
> from myhdl import Signal, delay, Simulation, always_comb, instance, intbv,
> bin
>
> def bin2gray(B, G, width):
>     """ Gray encoder.
>
>     B -- input intbv signal, binary encoded
>     G -- output intbv signal, gray encoded
>     width -- bit width
>     """
>
>     @always_comb
>     def logic():
>         for i in range(width):
>             G.next[i] = B[i+1] ^ B[i]
>
>     return logic
>
> def testBench(width):
>
>     B = Signal(intbv(0)[3:])
>     G = Signal(intbv(0)[3:])
>
>     dut = bin2gray(B, G, width)
>
>     @instance
>     def stimulus():
>         for i in range(2**width):
>             B.next = intbv(i)[3:]
>             yield delay(10)
>             print("B: " + bin(B, width) + "| G: " + bin(G, width))
>
>     return dut, stimulus
>
> sim = Simulation(testBench(width=3))
> sim.run()
>
>
> On Thu, Mar 3, 2016 at 2:24 PM, Samuele Disegna <sm...@gm...> wrote:
>
>> Hello, Last message was empty, my mistake.
>>
>> On Thu, Mar 3, 2016 at 2:10 PM, Samuele Disegna <sm...@gm...> wrote:
>>
>>>
>>>
>>> On Thu, Mar 3, 2016 at 1:14 PM, Forumulator Bing <for...@gm...>
>>> wrote:
>>>
>>>> Hello,
>>>>
>>>> I may have found a potential bug in intbv:
>>>>
>>>> >>> a=intbv(5)[4:0]
>>>> >>> a[6:0]=20
>>>> Traceback (most recent call last):
>>>>   File "<stdin>", line 1, in <module>
>>>>   File "/usr/local/lib/python3.4/dist-packages/myhdl/_intbv.py", line
>>>> 180, in __setitem__
>>>>     self._handleBounds()
>>>>   File "/usr/local/lib/python3.4/dist-packages/myhdl/_intbv.py", line
>>>> 77, in _handleBounds
>>>>     (self._val, self._max))
>>>> ValueError: intbv value 20 >= maximum 16
>>>> >>> a
>>>> intbv(20)
>>>>
>>>> It gives a ValueError, but still sets the value of a to 20. Would this
>>>> be considered a bug since an exception is thrown?
>>>>
>>>>
>>> From what I see on myhdl code min/max bounds handling is done later than
>> assignment and it seems independent.
>> Therefore I would say it is not a bug. We could document this behaviour.
>> Is it possible to subclass the exception to a documented ValueBoundError
>> that define the behaviour?
>>
>> You can find the related code at
>> https://github.com/jandecaluwe/myhdl/blob/master/myhdl/_intbv.py
>> def __setitem__(self, key, val):
>>
>> Regards
>>
>
>
>
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>

Re: [myhdl-list] Error in Intbv class?

[Samuele D. <sm...@gm...>]

Hi again, while analyzing the _intbv code I noticed a related problem:

An Exception is Not risen when accessing a out of bound bit of a
constrained intbv.
This seems a real problem to me.

I tested it by using the example code at
http://docs.myhdl.org/en/stable/manual/hwtypes.html#bit-indexing and
modifing it for using a constrained intbv:

from myhdl import Signal, delay, Simulation, always_comb, instance, intbv,
bin

def bin2gray(B, G, width):
    """ Gray encoder.

    B -- input intbv signal, binary encoded
    G -- output intbv signal, gray encoded
    width -- bit width
    """

    @always_comb
    def logic():
        for i in range(width):
            G.next[i] = B[i+1] ^ B[i]

    return logic

def testBench(width):

    B = Signal(intbv(0)[3:])
    G = Signal(intbv(0)[3:])

    dut = bin2gray(B, G, width)

    @instance
    def stimulus():
        for i in range(2**width):
            B.next = intbv(i)[3:]
            yield delay(10)
            print("B: " + bin(B, width) + "| G: " + bin(G, width))

    return dut, stimulus

sim = Simulation(testBench(width=3))
sim.run()


On Thu, Mar 3, 2016 at 2:24 PM, Samuele Disegna <sm...@gm...> wrote:

> Hello, Last message was empty, my mistake.
>
> On Thu, Mar 3, 2016 at 2:10 PM, Samuele Disegna <sm...@gm...> wrote:
>
>>
>>
>> On Thu, Mar 3, 2016 at 1:14 PM, Forumulator Bing <for...@gm...>
>> wrote:
>>
>>> Hello,
>>>
>>> I may have found a potential bug in intbv:
>>>
>>> >>> a=intbv(5)[4:0]
>>> >>> a[6:0]=20
>>> Traceback (most recent call last):
>>>   File "<stdin>", line 1, in <module>
>>>   File "/usr/local/lib/python3.4/dist-packages/myhdl/_intbv.py", line
>>> 180, in __setitem__
>>>     self._handleBounds()
>>>   File "/usr/local/lib/python3.4/dist-packages/myhdl/_intbv.py", line
>>> 77, in _handleBounds
>>>     (self._val, self._max))
>>> ValueError: intbv value 20 >= maximum 16
>>> >>> a
>>> intbv(20)
>>>
>>> It gives a ValueError, but still sets the value of a to 20. Would this
>>> be considered a bug since an exception is thrown?
>>>
>>>
>> From what I see on myhdl code min/max bounds handling is done later than
> assignment and it seems independent.
> Therefore I would say it is not a bug. We could document this behaviour.
> Is it possible to subclass the exception to a documented ValueBoundError
> that define the behaviour?
>
> You can find the related code at
> https://github.com/jandecaluwe/myhdl/blob/master/myhdl/_intbv.py
> def __setitem__(self, key, val):
>
> Regards
>

Re: [myhdl-list] Error in Intbv class?

[Samuele D. <sm...@gm...>]

Hello, Last message was empty, my mistake.

On Thu, Mar 3, 2016 at 2:10 PM, Samuele Disegna <sm...@gm...> wrote:

>
>
> On Thu, Mar 3, 2016 at 1:14 PM, Forumulator Bing <for...@gm...>
> wrote:
>
>> Hello,
>>
>> I may have found a potential bug in intbv:
>>
>> >>> a=intbv(5)[4:0]
>> >>> a[6:0]=20
>> Traceback (most recent call last):
>>   File "<stdin>", line 1, in <module>
>>   File "/usr/local/lib/python3.4/dist-packages/myhdl/_intbv.py", line
>> 180, in __setitem__
>>     self._handleBounds()
>>   File "/usr/local/lib/python3.4/dist-packages/myhdl/_intbv.py", line 77,
>> in _handleBounds
>>     (self._val, self._max))
>> ValueError: intbv value 20 >= maximum 16
>> >>> a
>> intbv(20)
>>
>> It gives a ValueError, but still sets the value of a to 20. Would this be
>> considered a bug since an exception is thrown?
>>
>>
> From what I see on myhdl code min/max bounds handling is done later than
assignment and it seems independent.
Therefore I would say it is not a bug. We could document this behaviour.
Is it possible to subclass the exception to a documented ValueBoundError
that define the behaviour?

You can find the related code at
https://github.com/jandecaluwe/myhdl/blob/master/myhdl/_intbv.py
def __setitem__(self, key, val):

Regards

Re: [myhdl-list] Error in Intbv class?

[Samuele D. <sm...@gm...>]

On Thu, Mar 3, 2016 at 1:14 PM, Forumulator Bing <for...@gm...>
wrote:

> Hello,
>
> I may have found a potential bug in intbv:
>
> >>> a=intbv(5)[4:0]
> >>> a[6:0]=20
> Traceback (most recent call last):
>   File "<stdin>", line 1, in <module>
>   File "/usr/local/lib/python3.4/dist-packages/myhdl/_intbv.py", line 180,
> in __setitem__
>     self._handleBounds()
>   File "/usr/local/lib/python3.4/dist-packages/myhdl/_intbv.py", line 77,
> in _handleBounds
>     (self._val, self._max))
> ValueError: intbv value 20 >= maximum 16
> >>> a
> intbv(20)
>
> It gives a ValueError, but still sets the value of a to 20. Would this be
> considered a bug since an exception is thrown?
>
>
>
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>
>

[myhdl-list] Error in Intbv class?

[Forumulator B. <for...@gm...>]

Hello,

I may have found a potential bug in intbv:

>>> a=intbv(5)[4:0]
>>> a[6:0]=20
Traceback (most recent call last):
  File "<stdin>", line 1, in <module>
  File "/usr/local/lib/python3.4/dist-packages/myhdl/_intbv.py", line 180,
in __setitem__
    self._handleBounds()
  File "/usr/local/lib/python3.4/dist-packages/myhdl/_intbv.py", line 77,
in _handleBounds
    (self._val, self._max))
ValueError: intbv value 20 >= maximum 16
>>> a
intbv(20)

It gives a ValueError, but still sets the value of a to 20. Would this be
considered a bug since an exception is thrown?

Re: [myhdl-list] GSoC'16 | JPEG Encoder

[Nicolas P. <nic...@aa...>]

Hi,
Le 02/03/2016 15:09, Henry Gomersall a écrit :
> On 02/03/16 13:59, Henry Gomersall wrote:
>> E.g. when the DSP has to be pipelined to maximize throughput, it's no
>> longer just a multiplier and the code has to reflect that. You could
>> create a multiplier block with pipeline stages incorporated, but then
>> you're more or less doing as I suggest (and still with no guarantees the
>> synthesizer will do the right thing).
> I wrote an inline complex multiplier based around a single DSP which
> really gets into the guts of the DSP core. It's hard to see how one
> would do this in plain VHDL with a hope that it would be inferred
> correctly (the difficulty is in things like flicking control registers
> mid pipeline from multiply-add to multiply-accumulate to
> multiply-deccumulate).
I have discovered MyHDL recently and considering using it.
I have followed your discussion and get questions :
- How is it possible to "switch" the underlying resources  ("inner 
primitive blocks can be switched") ?
- Why do you say you can do things with MyHDL but not VHDL (your complex 
multiplier) ?

Nicolas
>
> Cheers,
>
> Henry
>
> ------------------------------------------------------------------------------
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> .
>


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*** ni...@aa... <mailto:ni...@aa...>

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Re: [myhdl-list] GSoC'16 | JPEG Encoder

[Henry G. <he...@ma...>]

On 02/03/16 21:37, Martin Strubel wrote:
> Hi,
>> > 
>> > What do you mean my VLIW microcode? Why does it need to be VL?
>> > 
> It's like the parallel instructions for some DSPs like the Intel Micro
> Signal Architecture (Blackfin). To avoid extra decoding stages, the
> opcodes just turned out simplest as "VLIW". Snippet:
> 
> #     LD  SELB  VADD   PERM  MODE          ST
> 	( 0,   1,   1,     3,    MODE_ASAA,     0, ),  #0:
> 	( 3,   0,   1,     3,    MODE_ASAA,     2, ),  #1:
> ...
> 
> For example, portions of a long opcode control the different stage
> switches of the pipeline (whether you do just a mul, a mac or de-mac).

Ah that makes sense - it's essentially a concatenation of the control
signals.

Henry

Re: [myhdl-list] GSoC'16 | JPEG Encoder

[Martin S. <ha...@se...>]

Hi,
> 
> What do you mean my VLIW microcode? Why does it need to be VL?
> 

It's like the parallel instructions for some DSPs like the Intel Micro
Signal Architecture (Blackfin). To avoid extra decoding stages, the
opcodes just turned out simplest as "VLIW". Snippet:

#     LD  SELB  VADD   PERM  MODE          ST
	( 0,   1,   1,     3,    MODE_ASAA,     0, ),  #0:
	( 3,   0,   1,     3,    MODE_ASAA,     2, ),  #1:
...

For example, portions of a long opcode control the different stage
switches of the pipeline (whether you do just a mul, a mac or de-mac).

Greetings,

- Martin

Re: [myhdl-list] GSoC'16 | JPEG Encoder

[Henry G. <he...@ma...>]

On 02/03/16 15:16, Martin Strubel wrote:
>> I wrote an inline complex multiplier based around a single DSP which
>> > really gets into the guts of the DSP core. It's hard to see how one
>> > would do this in plain VHDL with a hope that it would be inferred
>> > correctly (the difficulty is in things like flicking control registers
>> > mid pipeline from multiply-add to multiply-accumulate to
>> > multiply-deccumulate).
>> > 
> I never had troubles getting the right thing instanced when staying
> below the 18 bit of the classic multiplier primitive. Above that, it can
> get funky on some toolchains WRT timing, but the nice thing about MyHDL
> is that it allows you to swap out the primitives in a much more
> configurable/reusable way than on the VHDL level.
> For the pipeline control, I typically use VLIW microcode that can be
> adapted easily if one of the MAC primitives needs to use a higher delay
> within the pipeline. So on the high level 'synthesis', you spell out the
> ops done in the pipeline in Python and the architecture (FPGA vendor)
> specific translator rolls out the rest. So a DCT is just a "hardware
> applet". If you spell it out in pure (vendor independent) VHDL, the
> synth tools always did it right so far, it just wasn't always optimal
> for their architecture and this is where the manual optimizations get
> nasty and way less reusable than in MyHDL.

I don't fully understand what you're getting at, but I think your
suggesting much the same as me :)

What do you mean my VLIW microcode? Why does it need to be VL?

Cheers,

Henry

Re: [myhdl-list] GSoC'16 | JPEG Encoder

[Martin S. <ha...@se...>]

Hi all,

> 
> I wrote an inline complex multiplier based around a single DSP which
> really gets into the guts of the DSP core. It's hard to see how one
> would do this in plain VHDL with a hope that it would be inferred
> correctly (the difficulty is in things like flicking control registers
> mid pipeline from multiply-add to multiply-accumulate to
> multiply-deccumulate).
> 

I never had troubles getting the right thing instanced when staying
below the 18 bit of the classic multiplier primitive. Above that, it can
get funky on some toolchains WRT timing, but the nice thing about MyHDL
is that it allows you to swap out the primitives in a much more
configurable/reusable way than on the VHDL level.
For the pipeline control, I typically use VLIW microcode that can be
adapted easily if one of the MAC primitives needs to use a higher delay
within the pipeline. So on the high level 'synthesis', you spell out the
ops done in the pipeline in Python and the architecture (FPGA vendor)
specific translator rolls out the rest. So a DCT is just a "hardware
applet". If you spell it out in pure (vendor independent) VHDL, the
synth tools always did it right so far, it just wasn't always optimal
for their architecture and this is where the manual optimizations get
nasty and way less reusable than in MyHDL.

Greetings,

- Strubi

Re: [myhdl-list] GSoC'16 | JPEG Encoder

[Henry G. <he...@ma...>]

On 02/03/16 13:59, Henry Gomersall wrote:
> E.g. when the DSP has to be pipelined to maximize throughput, it's no
> longer just a multiplier and the code has to reflect that. You could
> create a multiplier block with pipeline stages incorporated, but then
> you're more or less doing as I suggest (and still with no guarantees the
> synthesizer will do the right thing).

I wrote an inline complex multiplier based around a single DSP which
really gets into the guts of the DSP core. It's hard to see how one
would do this in plain VHDL with a hope that it would be inferred
correctly (the difficulty is in things like flicking control registers
mid pipeline from multiply-add to multiply-accumulate to
multiply-deccumulate).

Cheers,

Henry

Re: [myhdl-list] GSoC'16 | JPEG Encoder

[Henry G. <he...@ma...>]

On 02/03/16 13:53, Christopher Felton wrote:
>> >
>> > Specifically, most FPGAs have various mutually incompatible primitives,
>> > things like DSPs and RAM blocks. It would be great, for example, to have
>> > a MyHDL DSP structure that can be _just used_, and then switched to
>> > support whatever hardware.
> "can be just used" on whatever hardware is best supported
> (most portable) when you have generic HDL without specific
> primitives.  You can guide the HDL so the synthesizer
> infers the correct primitives e.g. DSP blocks can safely
> be inferred when the correct widths, delay slots, etc.
> This could be controlled with a couple parameters and the
> HDL could be modular to fit various structures - maybe?
> 

Yeah, absolutely. The problem comes when really pushing the bounds.

E.g. when the DSP has to be pipelined to maximize throughput, it's no
longer just a multiplier and the code has to reflect that. You could
create a multiplier block with pipeline stages incorporated, but then
you're more or less doing as I suggest (and still with no guarantees the
synthesizer will do the right thing).

It was a broader point than GSoC - more me thinking out loud.

Cheers,

Henry

Re: [myhdl-list] GSoC'16 | JPEG Encoder

[Christopher F. <chr...@gm...>]

On 3/2/2016 7:24 AM, Henry Gomersall wrote:
> On 02/03/16 12:06, Christopher Felton wrote:
>> The students will not be starting from scratch, they will be
>> using existing open-source encoders [1] to "port".  But this
>> will not be a simple port, they will be creating a design that
>> is more modular, scalable, and reusable than the existing
>> version.  As well as having a more exhaustive set of tests.
>
> Something just came to mind in light of this. I do wonder if it would be
> useful to have some mechanism by which inner primitive blocks can be
> switched.

In my opinion this is all do able, one has to decide
how they want to manage this in their design.  How does
the information permeate to submodules (sub-sub-sub).

>
> Specifically, most FPGAs have various mutually incompatible primitives,
> things like DSPs and RAM blocks. It would be great, for example, to have
> a MyHDL DSP structure that can be _just used_, and then switched to
> support whatever hardware.

"can be just used" on whatever hardware is best supported
(most portable) when you have generic HDL without specific
primitives.  You can guide the HDL so the synthesizer
infers the correct primitives e.g. DSP blocks can safely
be inferred when the correct widths, delay slots, etc.
This could be controlled with a couple parameters and the
HDL could be modular to fit various structures - maybe?

>
> Clearly, this sort of goal fits within something like rhea, but I'm not
> sure if there is an explicit drive towards it.
>
> In many instances, the primitives can be inferred from the V*, but more
> complicated designs (e.g. a JPEG encoder) can be made more efficient of
> resources by time slicing primitives, something the synthesizers are not
> good at [1].
>

This is all good but I doubt the students will get to this
level of optimization.  They will be striving for functional
correctness and reasonable performance (no performance
requirement).  If done correctly, a complete set of tests,
playing exploring optimizations and refactoring for performance
should be straightforward.

Regards,
Chris

Re: [myhdl-list] GSoC'16 | JPEG Encoder

[Henry G. <he...@ma...>]

On 02/03/16 12:06, Christopher Felton wrote:
> The students will not be starting from scratch, they will be
> using existing open-source encoders [1] to "port".  But this
> will not be a simple port, they will be creating a design that
> is more modular, scalable, and reusable than the existing
> version.  As well as having a more exhaustive set of tests.

Something just came to mind in light of this. I do wonder if it would be
useful to have some mechanism by which inner primitive blocks can be
switched.

Specifically, most FPGAs have various mutually incompatible primitives,
things like DSPs and RAM blocks. It would be great, for example, to have
a MyHDL DSP structure that can be _just used_, and then switched to
support whatever hardware.

Clearly, this sort of goal fits within something like rhea, but I'm not
sure if there is an explicit drive towards it.

In many instances, the primitives can be inferred from the V*, but more
complicated designs (e.g. a JPEG encoder) can be made more efficient of
resources by time slicing primitives, something the synthesizers are not
good at [1].

FYI, I've done some work on a Xilinx DSP and RAM block.

Henry

[1] as an aside, Xilinx have a beautifully well designed FIR block in
Vivado which does exactly this - it will time slice the DSP blocks for
you based on throughput clock speed, using the fewest DSP primitives it
can get away with.

Re: [myhdl-list] GSoC'16 | JPEG Encoder

[Christopher F. <chr...@gm...>]

On 3/2/2016 4:45 AM, Martin Strubel wrote:
> Hi,
>
>> After going through the projects list, I found the JPEG Encoder
>> interesting, mainly because I know a bit of Verilog and basic
>> scripting in Python.
<snip>
>
> This is quite ambitious, really. I've gone through the fun designing
> a JPEG encoder IP, you might want to focus on a small partition of
> the entire project, like an efficient way to pack the huffman encoded
> bit stream at high pixel clocks (~150 MHz for Full HD) in MyHDL.

The students will not be starting from scratch, they will be
using existing open-source encoders [1] to "port".  But this
will not be a simple port, they will be creating a design that
is more modular, scalable, and reusable than the existing
version.  As well as having a more exhaustive set of tests.

> Unfortunately, I'm a VHDL guy, so I've taken the other road. For
> sure, you'll need the full understanding of the JPEG encoding basics
> (this can cost you a few months), and it definitely helps, if you're
> firm with the cosimulation techniques of your simulator, unless
> you're using MyHDL completely. You might find some pointers or
> inspiration here: http://www.section5.ch/vkit The docs are slightly
> outdated though, most components are now MyHDL instead VHDL. It is
> kinda tricky, to get the arithmetics right with MyHDL, but when not
> touching the DCT, you'll save yourself some hassle :-)

Since the reference design exists, I don't imagine they will
need to know the specific details of the various algorithms,
but they will need to show that the MyHDL version is functionally
the same as the reference designs.

We also plan to have two students on the JPEGEnc project, the
JPEGEnc blocks will be divided between two students.

Thanks for the comments!  It is all good information and things
the students need to be aware of.  Now it looks like they will
have access to a third reference design :)


[1] https://github.com/cfelton/test_jpeg

Re: [myhdl-list] GSoC'16 | JPEG Encoder

[Christopher F. <chr...@gm...>]

On 3/2/2016 3:26 AM, Akshit Kumar wrote:
> Hi, My name is Akshit Kumar. I am a second year undergraduate student
> in the department of Electrical Engineering in Indian Institute of
> Technology, Madras. I wish to do a project under MyHDL in GSoC'16.

Hellow Akshit,

Thanks for the interest in our project.  We have had
quite a few students inquire about MyHDL this year.
Currently, we have as many students as we can handle.

You are still welcome to create a proposal as a backup,
things do happen where the initial students might not
complete a proposal.

Regards,
Chris

Re: [myhdl-list] GSoC'16 | JPEG Encoder

[Martin S. <ha...@se...>]

Hi,

> After going through the projects list, I found the JPEG Encoder
> interesting, mainly because I know a bit of Verilog and basic scripting
> in Python. The description of the idea mentioned that familiarity with
> digital circuits - wanted to know to what extent,could someone give an
> example of the same. I am new to this, so could someone please help me
> getting started. Could someone tell me what specific pre-requisites do I
> need to have to get started with this project?
> 

This is quite ambitious, really. I've gone through the fun designing a
JPEG encoder IP, you might want to focus on a small partition of the
entire project, like an efficient way to pack the huffman encoded bit
stream at high pixel clocks (~150 MHz for Full HD) in MyHDL.
Unfortunately, I'm a VHDL guy, so I've taken the other road.
For sure, you'll need the full understanding of the JPEG encoding basics
(this can cost you a few months), and it definitely helps, if you're
firm with the cosimulation techniques of your simulator, unless you're
using MyHDL completely.
You might find some pointers or inspiration here:
http://www.section5.ch/vkit
The docs are slightly outdated though, most components are now MyHDL
instead VHDL. It is kinda tricky, to get the arithmetics right with
MyHDL, but when not touching the DCT, you'll save yourself some hassle :-)

Cheers,

- Strubi

[myhdl-list] GSoC'16 | JPEG Encoder

[Akshit K. <aks...@gm...>]

Hi,
My name is Akshit Kumar. I am a second year undergraduate student in the
department of Electrical Engineering in Indian Institute of Technology,
Madras. I wish to do a project under MyHDL in GSoC'16.

After going through the projects list, I found the JPEG Encoder
interesting, mainly because I know a bit of Verilog and basic scripting in
Python. The description of the idea mentioned that familiarity with digital
circuits - wanted to know to what extent,could someone give an example of
the same. I am new to this, so could someone please help me getting
started. Could someone tell me what specific pre-requisites do I need to
have to get started with this project?

-- 
Regards
*Akshit Kumar*
Second Year Undergraduate Student
Department of Electrical Engineering
Indian Institute of Technology, Madras
http://akshitk.com

Re: [myhdl-list] JPEG Encoder and Leros Processor core (GSoC)

[Radhika <rad...@gm...>]

Ah, no problem. Would it still be alright to ask proposal-related questions
about the Leros processor project here?

Radhika

On Tue, Mar 1, 2016 at 2:07 AM, Christopher Felton <chr...@gm...>
wrote:

> On 2/29/2016 1:41 PM, Radhika wrote:
> > Hi,
> >
> > I'm interested in contributing to MyHDL and I'm familiar with both
> > Verilog and Python. I'd love to implement either the JPEG Encoder
> > core or the Leros processor over the summer.
>
> Radhika,
>
> We have had quite a few students inquire about
> GSoC this year.  Right now we have about all the
> students we can handle.
>
> You are still welcome to create a proposal but if
> competing proposals are of similar quality preference
> will be given to the fist set of students.
>
> Regards,
> Chris
>
>
>
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Re: [myhdl-list] Thanks for MyHDL & PLL's

[Christopher F. <chr...@gm...>]

On 2/25/2016 4:46 PM, Mr C Camacho wrote:
>
> mind I have noticed some oddities for example comparing list/tuple
> intbv elements with a intbv is still defeating me... I guess I'm
> still trying to get my head round the subtleties !

It might be worthwhile reviewing the a couple of the
conversion sections - how the list-of-signals and
list-of-tuples is mapped for conversion:


http://docs.myhdl.org/en/stable/manual/conversion_examples.html#ram-inference
http://docs.myhdl.org/en/stable/manual/conversion_examples.html#rom-inference

For the ROM, often you need to get the item from
the ROM first before.  The following is a demonstration,
the first compare doesn't convert the second does
https://gist.github.com/cfelton/d9d6bf4f6ff4c4afbed2

Regards,
Chris

Re: [myhdl-list] JPEG Encoder and Leros Processor core (GSoC)

[Christopher F. <chr...@gm...>]

On 2/29/2016 1:41 PM, Radhika wrote:
> Hi,
>
> I'm interested in contributing to MyHDL and I'm familiar with both
> Verilog and Python. I'd love to implement either the JPEG Encoder
> core or the Leros processor over the summer.

Radhika,

We have had quite a few students inquire about
GSoC this year.  Right now we have about all the
students we can handle.

You are still welcome to create a proposal but if
competing proposals are of similar quality preference
will be given to the fist set of students.

Regards,
Chris

[myhdl-list] JPEG Encoder and Leros Processor core (GSoC)

[Radhika <rad...@gm...>]

Hi,

I'm interested in contributing to MyHDL and I'm familiar with both Verilog
and Python. I'd love to implement either the JPEG Encoder core or the Leros
processor over the summer. I'm not experienced with implementing relatively
large-scale designs like these, but I'm certainly willing to work hard and
have a lot of fun in the process :)

For working on the Leros processor, what sort of order of implementation
would you suggest? Also, out of the JPEG encoder and the Leros processor,
which one would you recommend as a more reasonable project for an
intermediate-leveled student to work on?

Thanks,
Radhika

Re: [myhdl-list] Test Framework for GEMAC core (GSoC)

[Christopher F. <chr...@gm...>]

On 2/28/16 12:52 AM, Utkarsh Saxena wrote:
> Hi all,
>
> Test framework for the GEMAC core( potential project for GSoC '16) is
>  missing. The link provided on Ideas Page
> <https://github.com/cfelton/minnesota/blob/master/test/test_cores/test_eth/test_gemac_lite.py>

The correct link is:
https://github.com/cfelton/test_gemac

I will get that fixed as soon as possible.

>  . I am a prospective GSoC student and the idea of implementing this
>  project(or any core) is challenging. So I need the test framework to
> understand better the requirements. Or  better, I could write the
> test framework  myself if someone could instigate and guide me
> through the process. I need to learn and understand the working of
> GEMAC(of which resources on internet area scarce, but I am trying).
> Also, I know only the bare basics of ethernet protocol.

We have had many students express interest and others
have started creating a proposal for the GEMAC.
Currently, we have the have the max number of students
that we can support.


Regards,
Chris

[myhdl-list] Test Framework for GEMAC core (GSoC)

[Utkarsh S. <sax...@gm...>]

Hi all,

Test framework for the GEMAC core( potential project for GSoC '16) is
missing. The link provided on Ideas Page
<https://github.com/cfelton/minnesota/blob/master/test/test_cores/test_eth/test_gemac_lite.py>
.
I am a prospective GSoC student and the idea of implementing this
project(or any core) is challenging.
So I need the test framework to understand better the requirements.
Or  better, I could write the test framework  myself if someone could
instigate and guide me through the process.
I need to learn and understand the working of GEMAC(of which resources on
internet area scarce, but I am trying).
Also, I know only the bare basics of ethernet protocol.

Thanks,

Utkarsh