myhdl-list — Mailing list for discussions on MyHDL

[myhdl-list] unsubscribe

[<tim...@so...>]

Re: [myhdl-list] supported operators for Signal class

[Oscar D. D. <osc...@gm...>]

El Lun 11 Abr 2016 17:36:56 David Stanford escribió:
> I'm trying some tests converting python code to MyHDL code that generates
> real hardware. As a hardware designer, I know some of these tests are going
> to be foolish first steps to make, 

First of all, beware! You're doing conversion to generate real hardware. That 
means the sythesizable operand list is very limited. In particular, you cannot 
synthesize multiplications, divisions and powers (at least with common VHDL 
and Verilog synthesizers, possibly that won't be true with HLLs or High-Level 
Logic synthesizers).

If you're doing simulation only, you would be fine.

> Which leads to the question, what operand types ARE supported for Signals?
> This feels like an obvious question, but I can't seem to find an answer
> anywhere in the documentation.

In reality, the supported operands are related to the underlying type of the 
Signal object, in your example, that would be intbv. You can create Signals 
with int, or any other python data type.

Regarding the intbv type, you can check the source file _intbv.py, and look for 
the operand methods available[1]. I saw all implemented methods for integers, 
so an intbv should behave as an int (as the documentation say). 

[1] https://docs.python.org/2/reference/datamodel.html#emulating-numeric-types

> Am I searching poorly looking for a list of operators that works between
> signals, or does such a table not exist? Should it?

Due to the syhthesizable code restriction I can say addition, subtraction, 
logic (and, or, xor, not) and shifts are probably the only operands supported 
for conversion.

> Thanks,
> 
> Dave Stanford
> 
> 
> This e-mail and its attachments are intended only for the individual or
> entity to whom it is addressed and may contain information that is
> confidential, privileged, inside information, or subject to other
> restrictions on use or disclosure. Any unauthorized use, dissemination or
> copying of this transmission or the information in it is prohibited and may
> be unlawful. If you have received this transmission in error, please notify
> the sender immediately by return e-mail, and permanently delete or destroy
> this e-mail, any attachments, and all copies (digital or paper). Unless
> expressly stated in this e-mail, nothing in this message should be
> construed as a digital or electronic signature. For additional important
> disclaimers and disclosures regarding KCG’s products and services, please
> click on the following link:
 
> http://www.kcg.com/legal/global-disclosures
> ----------------------------------------------------------------------------
> -- Find and fix application performance issues faster with Applications
> Manager Applications Manager provides deep performance insights into
> multiple tiers of your business applications. It resolves application
> problems quickly and reduces your MTTR. Get your free trial!
> http://pubads.g.doubleclick.net/
> gampad/clk?id=1444514301&iu=/ca-pub-7940484522588532
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list

-- 
Oscar Díaz
Key Fingerprint = 8D3D 5FC4 A48C 5404 24AC  F684 A42F CE7C 39C0 AC6B
gpg --keyserver subkeys.pgp.net --recv-keys A42FCE7C39C0AC6B

I recommend using OpenDocument Format
for daily use and exchange of documents.

http://www.fsf.org/campaigns/opendocument

[myhdl-list] 回复：Re: 回复：Welcome to the "myhdl-list"_mailing_list

[<chr...@si...>]

Thanks chris, I will check what's wrong wih my configuration.
And, that's great if you can check the block examples.
RegardsChriss  

On 4/8/16 3:07 PM, chr...@si... wrote:
> Dear myhdl friends,
>
>
> I'm new to myhdl, and quite interested in the amazing feature of
> python for HDL.
>
> My first step is to run the example and test code.
>
>
> I use the 1.0dev master in github. and install all icarus simulator.
>
>
> But, there are lots of test cannot pass,  is that true? or something
>  wrong with my configuration.
This shouldn't be true, travis-ci for the master
branch is passing all the tests should pass on
the master:
https://travis-ci.org/jandecaluwe/myhdl/builds/117452101
(commit ac9ad7b)
>
> Also, I'm try the "bitonic" example to test @block decorator, seems
> also failed, because it return a list of "block" object, which cannot
> be handled correctly.
>
When I get a chance I can test this out, I don't know
if anyone else attempted any of the examples on the
website with MEP114 changes yet?
Regards,
Chris
------------------------------------------------------------------------------
Find and fix application performance issues faster with Applications Manager
Applications Manager provides deep performance insights into multiple tiers of
your business applications. It resolves application problems quickly and
reduces your MTTR. Get your free trial! http://pubads.g.doubleclick.net/
gampad/clk?id=1444514301&iu=/ca-pub-7940484522588532
_______________________________________________
myhdl-list mailing list
myh...@li...
https://lists.sourceforge.net/lists/listinfo/myhdl-list

[myhdl-list] supported operators for Signal class

[David S. <dst...@kc...>]

I'm trying some tests converting python code to MyHDL code that generates real hardware. As a hardware designer, I know some of these tests are going to be foolish first steps to make, but I also know that less experienced designers might make these same mistakes. Here's a simplified code block

    x, y = [Signal(intbv(1)[64:]) for i in range(2)]
    @always_seq(clk.posedge, reset)
    def test_divide():
        y.next = y / x

    return test_divide

and here's the error message I get:

    y.next = y / x
TypeError: unsupported operand type(s) for /: '_Signal' and '_Signal'


Which leads to the question, what operand types ARE supported for Signals? This feels like an obvious question, but I can't seem to find an answer anywhere in the documentation.

When I change the code to be

y.next = y ** x

I was surprised to get a different error message:

  File "/home/dstanford/.local/lib/python2.7/site-packages/myhdl/conversion/_toVHDL.py", line 171, in __call__
    _annotateTypes(genlist)
  File "/home/dstanford/.local/lib/python2.7/site-packages/myhdl/conversion/_toVHDL.py", line 2288, in _annotateTypes
    v.visit(tree)
  File "/usr/lib/python2.7/ast.py", line 241, in visit
    return visitor(node)
  File "/usr/lib/python2.7/ast.py", line 249, in generic_visit
    self.visit(item)
  File "/usr/lib/python2.7/ast.py", line 241, in visit
    return visitor(node)
  File "/home/dstanford/.local/lib/python2.7/site-packages/myhdl/conversion/_toVHDL.py", line 2029, in visit_FunctionDef
    self.visit(stmt)
  File "/usr/lib/python2.7/ast.py", line 241, in visit
    return visitor(node)
  File "/usr/lib/python2.7/ast.py", line 251, in generic_visit
    self.visit(value)
  File "/usr/lib/python2.7/ast.py", line 241, in visit
    return visitor(node)
  File "/home/dstanford/.local/lib/python2.7/site-packages/myhdl/conversion/_toVHDL.py", line 2137, in visit_BinOp
    self.inferBinOpType(node)
  File "/home/dstanford/.local/lib/python2.7/site-packages/myhdl/conversion/_toVHDL.py", line 2175, in inferBinOpType
    raise AssertionError("unexpected op %s" % op)
AssertionError: unexpected op <_ast.Pow object at 0x7fa74b0e3350>

And finally going through a list of basic python operators I tried out

y.next = y // x

which works, and makes sense though I didn't even know it was an option until I was trying this test out.

Am I searching poorly looking for a list of operators that works between signals, or does such a table not exist? Should it?

Thanks,

Dave Stanford


This e-mail and its attachments are intended only for the individual or entity to whom it is addressed and may contain information that is confidential, privileged, inside information, or subject to other restrictions on use or disclosure. Any unauthorized use, dissemination or copying of this transmission or the information in it is prohibited and may be unlawful. If you have received this transmission in error, please notify the sender immediately by return e-mail, and permanently delete or destroy this e-mail, any attachments, and all copies (digital or paper). Unless expressly stated in this e-mail, nothing in this message should be construed as a digital or electronic signature. For additional important disclaimers and disclosures regarding KCG’s products and services, please click on the following link:

http://www.kcg.com/legal/global-disclosures

Re: [myhdl-list] 回复：Welcome to the "myhdl-list" mailing list

[Christopher F. <chr...@gm...>]

On 4/8/16 3:07 PM, chr...@si... wrote:
> Dear myhdl friends,
>
>
> I'm new to myhdl, and quite interested in the amazing feature of
> python for HDL.
>
> My first step is to run the example and test code.
>
>
> I use the 1.0dev master in github. and install all icarus simulator.
>
>
> But, there are lots of test cannot pass,  is that true? or something
>  wrong with my configuration.

This shouldn't be true, travis-ci for the master
branch is passing all the tests should pass on
the master:
https://travis-ci.org/jandecaluwe/myhdl/builds/117452101
(commit ac9ad7b)

>
> Also, I'm try the "bitonic" example to test @block decorator, seems
> also failed, because it return a list of "block" object, which cannot
> be handled correctly.
>

When I get a chance I can test this out, I don't know
if anyone else attempted any of the examples on the
website with MEP114 changes yet?

Regards,
Chris

[myhdl-list] 回复：Welcome to the "myhdl-list" mailing list

[<chr...@si...>]

Dear myhdl friends, 
I'm new to myhdl, and quite interested in the amazing feature of python for HDL.    My first step is to run the example and test code.  
I use the 1.0dev master in github. and install all icarus simulator.
But, there are lots of test cannot pass,  is that true? or something wrong with my configuration.
Also, I'm try the "bitonic" example to test @block decorator, seems also failed, because it return a list of "block" object, which cannot be handled correctly.
Looking forward and appreciate you help!
RegardsChriss

Re: [myhdl-list] Block return values (myhdl.BlockError)

[Christopher F. <chr...@gm...>]

On 3/29/16 8:54 AM, Jos Huisken wrote:
> Hi,
>
> Sometimes I'm using a block like this:
>
> def tb():
>      m, clk, rst = clkrst()
>      return m, clk, rst
>
> In which 'm' is the list of instantiator objects, and 'clk'/'rst' are
> Signals.
> So this way you can specify a block in general:
>
> def unit(inputports):
>      ...
>      return m, outputports

I have, in the past, attempted to use returns other
than the myhdl.generators but I haven't been too
successful.  I can see the utility because often
the ports are a function of the inputs.  I do not
know if it will be possible with the new implementation.

It isn't the most DRY but you could attach a function
to the ~~module~~ block:

     outputs = myblock.get_outputs(**inputs)
     inst = myblock(**inputs, **outputs)

>
> Note that this could be a preferred way of design. It just happened that I
> created few such examples.
>
> With the new block decorator this is not allowed anymore, raising a
> myhdl.BlockError.

If this is not supported with MEP114, we might want
to add alternative suggestions to the MEP/documentation
for users that have used returns which include more
than generators.

Regards,
Chris

[myhdl-list] Block return values (myhdl.BlockError)

[Jos H. <jos...@gm...>]

Hi,

Sometimes I'm using a block like this:

def tb():
    m, clk, rst = clkrst()
    return m, clk, rst

In which 'm' is the list of instantiator objects, and 'clk'/'rst' are 
Signals.
So this way you can specify a block in general:

def unit(inputports):
    ...
    return m, outputports

Note that this could be a preferred way of design. It just happened that I 
created few such examples.

With the new block decorator this is not allowed anymore, raising a 
myhdl.BlockError.

I can imagine that also other return values may be wanted by users.
Is this something which can be taken into account?
Or: should 'block's really be constrained in returning just block or 
instantiator objects?

Thanks,
Jos

Re: [myhdl-list] How to specify unused ports

[Nicolas P. <nic...@aa...>]

Le 23/03/2016 13:13, Samuele Disegna a écrit :
>
> Hi Nicolas,
>
> For reference there is already an enhancement request on this at 
> https://github.com/jandecaluwe/myhdl/issues/126
>
Ok. I did not noticed it.

Thanks
Nicolas

> Samuele Disegna
>
> Il 23/Mar/2016 12:55, "Nicolas Pinault" <nic...@aa... 
> <mailto:nic...@aa...>> ha scritto:
>
>     Hi,
>
>     With VHDL, when a port is not used on an entity/component
>     instance, I use "open" keyword.
>     How do I do the same with myHDL ?
>
>     Nicolas
>
>     -- 
>     *Nicolas PINAULT
>     R&D electronics engineer
>     *** ni...@aa... <mailto:ni...@aa...>
>
>     *AATON-Digital*
>     38000 Grenoble - France
>     Tel +33 4 7642 9550 <tel:%2B33%204%207642%209550>
>
>     http://www.aaton.com
>     http://www.transvideo.eu
>     French Technologies for Film and Digital Cinematography
>
>     Follow us on Twitter
>     @Aaton_Digital
>     @Transvideo_HD
>
>     Like us on Facebook
>     https://www.facebook.com/AatonDigital
>
>
>     ------------------------------------------------------------------------------
>     Transform Data into Opportunity.
>     Accelerate data analysis in your applications with
>     Intel Data Analytics Acceleration Library.
>     Click to learn more.
>     http://pubads.g.doubleclick.net/gampad/clk?id=278785351&iu=/4140
>     _______________________________________________
>     myhdl-list mailing list
>     myh...@li...
>     <mailto:myh...@li...>
>     https://lists.sourceforge.net/lists/listinfo/myhdl-list
>
>
>
> ------------------------------------------------------------------------------
> Transform Data into Opportunity.
> Accelerate data analysis in your applications with
> Intel Data Analytics Acceleration Library.
> Click to learn more.
> http://pubads.g.doubleclick.net/gampad/clk?id=278785351&iu=/4140
>
>
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list


-- 
*Nicolas PINAULT
R&D electronics engineer
*** ni...@aa... <mailto:ni...@aa...>

*AATON-Digital*
38000 Grenoble - France
Tel +33 4 7642 9550

http://www.aaton.com
http://www.transvideo.eu
French Technologies for Film and Digital Cinematography

Follow us on Twitter
@Aaton_Digital
@Transvideo_HD

Like us on Facebook
https://www.facebook.com/AatonDigital

Re: [myhdl-list] How to specify unused ports

[Samuele D. <sm...@gm...>]

Hi Nicolas,

For reference there is already an enhancement request on this at
https://github.com/jandecaluwe/myhdl/issues/126

Samuele Disegna
Il 23/Mar/2016 12:55, "Nicolas Pinault" <nic...@aa...> ha scritto:

> Hi,
>
> With VHDL, when a port is not used on an entity/component instance, I use
> "open" keyword.
> How do I do the same with myHDL ?
>
> Nicolas
>
> --
>
>
> * Nicolas PINAULT R&D electronics engineer * ni...@aa...
>
> *AATON-Digital*
> 38000 Grenoble - France
> Tel +33 4 7642 9550
>
> http://www.aaton.com
> http://www.transvideo.eu
> French Technologies for Film and Digital Cinematography
>
> Follow us on Twitter
> @Aaton_Digital
> @Transvideo_HD
>
> Like us on Facebook
> https://www.facebook.com/AatonDigital
>
>
>
> ------------------------------------------------------------------------------
> Transform Data into Opportunity.
> Accelerate data analysis in your applications with
> Intel Data Analytics Acceleration Library.
> Click to learn more.
> http://pubads.g.doubleclick.net/gampad/clk?id=278785351&iu=/4140
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>
>

[myhdl-list] How to specify unused ports

[Nicolas P. <nic...@aa...>]

Hi,

With VHDL, when a port is not used on an entity/component instance, I 
use "open" keyword.
How do I do the same with myHDL ?

Nicolas

-- 
*Nicolas PINAULT
R&D electronics engineer
*** ni...@aa... <mailto:ni...@aa...>

*AATON-Digital*
38000 Grenoble - France
Tel +33 4 7642 9550

http://www.aaton.com
http://www.transvideo.eu
French Technologies for Film and Digital Cinematography

Follow us on Twitter
@Aaton_Digital
@Transvideo_HD

Like us on Facebook
https://www.facebook.com/AatonDigital

Re: [myhdl-list] verilog to MyHDL conversion

[David B. <dav...@ya...>]

I was wondering if MyHDL /  Python supports functional oriented programming and development for FPGAs ??  


Thanks,
David Blubaugh
 

    On Monday, March 21, 2016 8:36 PM, Edward Vidal <dev...@sb...> wrote:
 

 Chris,I used a module top_level which uses a dd dummy method to include the verilog code using a 
dd.verilog_code = \ statement.
python jtagser.py --convert.
see https://gist.github.com/609d03b3296dd3610343.git
This now includes BSCAN_SPARTAN6 like the file jtagser.v
 Thanks,
Edward Vidal Jr. e-mail dev...@sb... 915-595-1613 

   

 On Sunday, March 20, 2016 5:09 PM, Edward Vidal <dev...@sb...> wrote:
 

 Chris,The following o_rx_data.next = { ck_tdi, o_rx_data[7:1] } converts to 
o_rx_data <= ck_tdio_rx_data[7-1:1]; should be o_rx_data <= { ck_tdi, o_rx_data[7:1] };
What is this statement doing? 
Still must be missing something? Not getting anything in the .v file created.Is this what you wanted me to do?
    capture = Signal(bool(0))
    drck = Signal(bool(0))
    reset = Signal(bool(0))
    RUNTEST = Signal(bool(0))
    SEL = Signal(bool(0))
    SHIFT = Signal(bool(0))
    TCK = Signal(bool(0))
    TDI = Signal(bool(0))
    TMS = Signal(bool(0))
    UPDATE = Signal(bool(0))
    TDO = Signal(bool(0))

    def bscan_spartan6(capture,drck,reset,RUNTEST,SEL,SHIFT,TCK,TDI,TMS,UPDATE,TDO):
        '''
        mark the outputs with sig.driven = True
        maybe put some logic to stub out minimal behavior
        '''
        capture.driven = True
        drck.driven = True
        reset.driven = True
        RUNTEST.driven = True
        SEL.driven = True
        SHIFT.driven = True
        TCK.driven = True
        TDI.driven = True
        TMS.driven = True
        UPDATE.driven = True
        TDO.driven = True
Thanks,
 Edward Vidal Jr. e-mail dev...@sb... 915-595-1613 

    On Sunday, March 20, 2016 12:11 PM, Christopher Felton <chr...@gm...> wrote:
 

 On 3/20/16 10:59 AM, Edward Vidal wrote:
> See the verilog file and my attempt to convert at
> https://gist.github.com/95d06caf184fc1976d65.git
> Are verilog && in myhdl written as & this?  I was getting

You would use "and" in Python/MyHDL.


> The code that starts with BSCAN_SPARTAN6, I believe came
> from a template.  I was hoping on user jtag.verilog_code = \
> to include it, in my the generated verilog file.  When I move
> line 72 """ to line 74 of jtagser.py I get the quoted text but not
> the other instance that I am trying to convert.

For this you want to create a separate block (module)
and override the contents of the block:

    def bscan_spartan6(capture, drck, reset, ...)
        # mark the outputs with sig.driven = True
        # maybe put some logic to stub out minimal behavior

    bscan_spartan6.verilog_code = \
    """
    BSCAN_SPARTN6
        #(.JTAG_CHAIN(1)))
    BSCANE2_inst(
        .CAPTURE($capture),
        .DRCK($drck),
        ...


Hope that helps,
Chris



------------------------------------------------------------------------------
Transform Data into Opportunity.
Accelerate data analysis in your applications with
Intel Data Analytics Acceleration Library.
Click to learn more.
http://pubads.g.doubleclick.net/gampad/clk?id=278785231&iu=/4140
_______________________________________________
myhdl-list mailing list
myh...@li...
https://lists.sourceforge.net/lists/listinfo/myhdl-list


   
------------------------------------------------------------------------------
Transform Data into Opportunity.
Accelerate data analysis in your applications with
Intel Data Analytics Acceleration Library.
Click to learn more.
http://pubads.g.doubleclick.net/gampad/clk?id=278785231&iu=/4140
_______________________________________________
myhdl-list mailing list
myh...@li...
https://lists.sourceforge.net/lists/listinfo/myhdl-list


   
------------------------------------------------------------------------------
Transform Data into Opportunity.
Accelerate data analysis in your applications with
Intel Data Analytics Acceleration Library.
Click to learn more.
http://pubads.g.doubleclick.net/gampad/clk?id=278785351&iu=/4140
_______________________________________________
myhdl-list mailing list
myh...@li...
https://lists.sourceforge.net/lists/listinfo/myhdl-list


  

Re: [myhdl-list] verilog to MyHDL conversion

[Edward V. <dev...@sb...>]

Chris,I used a module top_level which uses a dd dummy method to include the verilog code using a 
dd.verilog_code = \ statement.
python jtagser.py --convert.
see https://gist.github.com/609d03b3296dd3610343.git
This now includes BSCAN_SPARTAN6 like the file jtagser.v
 Thanks,
Edward Vidal Jr. e-mail dev...@sb... 915-595-1613 

   

 On Sunday, March 20, 2016 5:09 PM, Edward Vidal <dev...@sb...> wrote:
 

 Chris,The following o_rx_data.next = { ck_tdi, o_rx_data[7:1] } converts to 
o_rx_data <= ck_tdio_rx_data[7-1:1]; should be o_rx_data <= { ck_tdi, o_rx_data[7:1] };
What is this statement doing? 
Still must be missing something? Not getting anything in the .v file created.Is this what you wanted me to do?
    capture = Signal(bool(0))
    drck = Signal(bool(0))
    reset = Signal(bool(0))
    RUNTEST = Signal(bool(0))
    SEL = Signal(bool(0))
    SHIFT = Signal(bool(0))
    TCK = Signal(bool(0))
    TDI = Signal(bool(0))
    TMS = Signal(bool(0))
    UPDATE = Signal(bool(0))
    TDO = Signal(bool(0))

    def bscan_spartan6(capture,drck,reset,RUNTEST,SEL,SHIFT,TCK,TDI,TMS,UPDATE,TDO):
        '''
        mark the outputs with sig.driven = True
        maybe put some logic to stub out minimal behavior
        '''
        capture.driven = True
        drck.driven = True
        reset.driven = True
        RUNTEST.driven = True
        SEL.driven = True
        SHIFT.driven = True
        TCK.driven = True
        TDI.driven = True
        TMS.driven = True
        UPDATE.driven = True
        TDO.driven = True
Thanks,
 Edward Vidal Jr. e-mail dev...@sb... 915-595-1613 

    On Sunday, March 20, 2016 12:11 PM, Christopher Felton <chr...@gm...> wrote:
 

 On 3/20/16 10:59 AM, Edward Vidal wrote:
> See the verilog file and my attempt to convert at
> https://gist.github.com/95d06caf184fc1976d65.git
> Are verilog && in myhdl written as & this?  I was getting

You would use "and" in Python/MyHDL.


> The code that starts with BSCAN_SPARTAN6, I believe came
> from a template.  I was hoping on user jtag.verilog_code = \
> to include it, in my the generated verilog file.  When I move
> line 72 """ to line 74 of jtagser.py I get the quoted text but not
> the other instance that I am trying to convert.

For this you want to create a separate block (module)
and override the contents of the block:

    def bscan_spartan6(capture, drck, reset, ...)
        # mark the outputs with sig.driven = True
        # maybe put some logic to stub out minimal behavior

    bscan_spartan6.verilog_code = \
    """
    BSCAN_SPARTN6
        #(.JTAG_CHAIN(1)))
    BSCANE2_inst(
        .CAPTURE($capture),
        .DRCK($drck),
        ...


Hope that helps,
Chris



------------------------------------------------------------------------------
Transform Data into Opportunity.
Accelerate data analysis in your applications with
Intel Data Analytics Acceleration Library.
Click to learn more.
http://pubads.g.doubleclick.net/gampad/clk?id=278785231&iu=/4140
_______________________________________________
myhdl-list mailing list
myh...@li...
https://lists.sourceforge.net/lists/listinfo/myhdl-list


   
------------------------------------------------------------------------------
Transform Data into Opportunity.
Accelerate data analysis in your applications with
Intel Data Analytics Acceleration Library.
Click to learn more.
http://pubads.g.doubleclick.net/gampad/clk?id=278785231&iu=/4140
_______________________________________________
myhdl-list mailing list
myh...@li...
https://lists.sourceforge.net/lists/listinfo/myhdl-list


  

Re: [myhdl-list] verilog to MyHDL conversion

[Edward V. <dev...@sb...>]

Chris,The following o_rx_data.next = { ck_tdi, o_rx_data[7:1] } converts to 
o_rx_data <= ck_tdio_rx_data[7-1:1]; should be o_rx_data <= { ck_tdi, o_rx_data[7:1] };
What is this statement doing? 
Still must be missing something? Not getting anything in the .v file created.Is this what you wanted me to do?
    capture = Signal(bool(0))
    drck = Signal(bool(0))
    reset = Signal(bool(0))
    RUNTEST = Signal(bool(0))
    SEL = Signal(bool(0))
    SHIFT = Signal(bool(0))
    TCK = Signal(bool(0))
    TDI = Signal(bool(0))
    TMS = Signal(bool(0))
    UPDATE = Signal(bool(0))
    TDO = Signal(bool(0))

    def bscan_spartan6(capture,drck,reset,RUNTEST,SEL,SHIFT,TCK,TDI,TMS,UPDATE,TDO):
        '''
        mark the outputs with sig.driven = True
        maybe put some logic to stub out minimal behavior
        '''
        capture.driven = True
        drck.driven = True
        reset.driven = True
        RUNTEST.driven = True
        SEL.driven = True
        SHIFT.driven = True
        TCK.driven = True
        TDI.driven = True
        TMS.driven = True
        UPDATE.driven = True
        TDO.driven = True
Thanks,
 Edward Vidal Jr. e-mail dev...@sb... 915-595-1613 

    On Sunday, March 20, 2016 12:11 PM, Christopher Felton <chr...@gm...> wrote:
 

 On 3/20/16 10:59 AM, Edward Vidal wrote:
> See the verilog file and my attempt to convert at
> https://gist.github.com/95d06caf184fc1976d65.git
> Are verilog && in myhdl written as & this?  I was getting

You would use "and" in Python/MyHDL.


> The code that starts with BSCAN_SPARTAN6, I believe came
> from a template.  I was hoping on user jtag.verilog_code = \
> to include it, in my the generated verilog file.  When I move
> line 72 """ to line 74 of jtagser.py I get the quoted text but not
> the other instance that I am trying to convert.

For this you want to create a separate block (module)
and override the contents of the block:

    def bscan_spartan6(capture, drck, reset, ...)
        # mark the outputs with sig.driven = True
        # maybe put some logic to stub out minimal behavior

    bscan_spartan6.verilog_code = \
    """
    BSCAN_SPARTN6
        #(.JTAG_CHAIN(1)))
    BSCANE2_inst(
        .CAPTURE($capture),
        .DRCK($drck),
        ...


Hope that helps,
Chris



------------------------------------------------------------------------------
Transform Data into Opportunity.
Accelerate data analysis in your applications with
Intel Data Analytics Acceleration Library.
Click to learn more.
http://pubads.g.doubleclick.net/gampad/clk?id=278785231&iu=/4140
_______________________________________________
myhdl-list mailing list
myh...@li...
https://lists.sourceforge.net/lists/listinfo/myhdl-list


  

Re: [myhdl-list] verilog to MyHDL conversion

[Christopher F. <chr...@gm...>]

On 3/20/16 10:59 AM, Edward Vidal wrote:
> See the verilog file and my attempt to convert at
> https://gist.github.com/95d06caf184fc1976d65.git
> Are verilog && in myhdl written as & this?  I was getting

You would use "and" in Python/MyHDL.


> The code that starts with BSCAN_SPARTAN6, I believe came
> from a template.  I was hoping on user jtag.verilog_code = \
> to include it, in my the generated verilog file.  When I move
> line 72 """ to line 74 of jtagser.py I get the quoted text but not
> the other instance that I am trying to convert.

For this you want to create a separate block (module)
and override the contents of the block:

     def bscan_spartan6(capture, drck, reset, ...)
         # mark the outputs with sig.driven = True
         # maybe put some logic to stub out minimal behavior

    bscan_spartan6.verilog_code = \
    """
    BSCAN_SPARTN6
        #(.JTAG_CHAIN(1)))
    BSCANE2_inst(
        .CAPTURE($capture),
        .DRCK($drck),
        ...


Hope that helps,
Chris

[myhdl-list] verilog to MyHDL conversion

[Edward V. <dev...@sb...>]

Hello All,

I am trying to convert exiting verilog code to MyHDL.

This is in hopes of getting a person interested in MyHDL.

See the verilog file and my attempt to convert at

https://gist.github.com/95d06caf184fc1976d65.git

Are verilog && in myhdl written as & this?  I was getting 

errors when using &&.

The code that starts with BSCAN_SPARTAN6, I believe came 

from a template.  I was hoping on user jtag.verilog_code = \

to include it, in my the generated verilog file.  When I move 

line 72 """ to line 74 of jtagser.py I get the quoted text but not the 

other instance that I am trying to convert.


This line in verilog o_rx_data <= { ck_tdi, o_rx_data[7:1] }; converted 

o_rx_data <= ck_tdio_rx_data[7-1:1]; did I write this python 

correctly?

Thanks in advance.

All help is appreciated. Edward Vidal Jr. e-mail dev...@sb... 915-595-1613

Re: [myhdl-list] Project proposal for GSoC

[Merkourios K. <mer...@gm...>]

Hello Chris,

I checked this project idea and I find it really interesting. Also it
is a one-student project. What's your opinion?

Regards,
Merkourios

On Sat, Mar 19, 2016 at 10:53 PM, Oscar Daniel Diaz <osc...@gm...> wrote:
> Hello,
>
> Following the proposal done by Keerthan, I also proposed a new project for
> GSoC:
>
>
> ### Crypto core
>
> This project is the design and test of a cryptographic core. This core should
> be designed to be modular, to implement various cryptographic algorithms and
> operation modes, support symmetric and asymmetric encryption, and it should be
> easy to extend. Recommended algorithms to implement are AES, 3DES and RSA, and
> operation modes to implement are ECB, CBC, CFB, OFB and CTR.
>
> Additional aspects to cover with this project are:
>    * Performance comparison against software implementation.
>    * A modular test mechanism.
>    * Study on possible implementation vulnerabilities.
>
> A reference implementation for this project is openSSL library, although there
> are some hardware implementations in VHDL and Verilog.
>
> ###
>
> I already did a pull request to GSoC page, so it should be published soon. If
> anyone is interested in this project, don't hesitate to tell me about it.
>
> Best regards, Oscar.
> --
> Oscar Díaz
> Key Fingerprint = 8D3D 5FC4 A48C 5404 24AC  F684 A42F CE7C 39C0 AC6B
> gpg --keyserver subkeys.pgp.net --recv-keys A42FCE7C39C0AC6B
>
> I recommend using OpenDocument Format
> for daily use and exchange of documents.
>
> http://www.fsf.org/campaigns/opendocument
>
> ------------------------------------------------------------------------------
> Transform Data into Opportunity.
> Accelerate data analysis in your applications with
> Intel Data Analytics Acceleration Library.
> Click to learn more.
> http://pubads.g.doubleclick.net/gampad/clk?id=278785231&iu=/4140
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>

[myhdl-list] Customer Evaluation- Participate & Get Paid!

[Opinion O. <gy...@cr...>]

 - This mail is in HTML. Some elements may be ommited in plain text. -

We currently have a customer evaluation assignment

available in your area and we would like you to participate.
Get Paid $200.00 for every Assignment Completed.
Click Here

to read more and Sign Up if interested.
Thank you for participating.
Opinion Outpost?

6 Research Drive
Shelton, CT 06484. U.S.A
Attn: Robert Walsh

[myhdl-list] Project proposal for GSoC

[Oscar D. D. <osc...@gm...>]

Hello, 

Following the proposal done by Keerthan, I also proposed a new project for 
GSoC: 

 
### Crypto core

This project is the design and test of a cryptographic core. This core should 
be designed to be modular, to implement various cryptographic algorithms and 
operation modes, support symmetric and asymmetric encryption, and it should be 
easy to extend. Recommended algorithms to implement are AES, 3DES and RSA, and 
operation modes to implement are ECB, CBC, CFB, OFB and CTR. 

Additional aspects to cover with this project are:
   * Performance comparison against software implementation.
   * A modular test mechanism.
   * Study on possible implementation vulnerabilities.

A reference implementation for this project is openSSL library, although there 
are some hardware implementations in VHDL and Verilog.

###

I already did a pull request to GSoC page, so it should be published soon. If 
anyone is interested in this project, don't hesitate to tell me about it. 

Best regards, Oscar.
-- 
Oscar Díaz
Key Fingerprint = 8D3D 5FC4 A48C 5404 24AC  F684 A42F CE7C 39C0 AC6B
gpg --keyserver subkeys.pgp.net --recv-keys A42FCE7C39C0AC6B

I recommend using OpenDocument Format
for daily use and exchange of documents.

http://www.fsf.org/campaigns/opendocument

[myhdl-list] GSoC: RISC-V idea

[Keerthan JC <jck...@gm...>]

I have just added a section about RISC-V to the GSoC ideas page.
http://dev.myhdl.org/gsoc/gsoc_2016.html#risc-v-cpu-and-tools

Feel free to contact me if you have any questions.

-- 
have a nice day
-jck

[myhdl-list] GSOC-2016 DDR3 Controller Project

[Manpreet S. <kha...@gm...>]

  Hello everyone

   I am Manpreet Singh pursuing my M.tech in Power Engineering. I did
my B.tech in Electrical Engineering but I am very much interested in
electronics and computer related projects. I worked on 8051
architecture based micro-controllers and Arduino using embedded C
language. I used python  to make GUI's and to interface Arduino with
computer using python libraries. I am very much familiar with digital
electronics, C ,C++ and have basic knowledge of VHDL. I know about the
external memories. So I want to work on DDR3 controller project. I
hope I will learn a lot of things during this project. If you can give
me more information about this project it will be very helpfull for
me.

--
Manpreet Singh(M$K)
http://khalsamps.blogspot.in<div
id="DDB4FAA8-2DD7-40BB-A1B8-4E2AA1F9FDF2"><br />
<table style="border-top: 1px solid #aaabb6;">
	<tr>
		<td style="width: 470px; padding-top: 20px; color: #41424e;
font-size: 13px; font-family: Arial, Helvetica, sans-serif;
line-height: 18px;">This email has been sent from a virus-free
computer protected by Avast. <br /><a
href="https://www.avast.com/sig-email?utm_medium=email&utm_source=link&utm_campaign=sig-email&utm_content=webmail"
target="_blank" style="color: #4453ea;">www.avast.com</a>
		</td>
	</tr>
</table><a href="#DDB4FAA8-2DD7-40BB-A1B8-4E2AA1F9FDF2" width="1"
height="1"></a></div>

Re: [myhdl-list] GSoC 2016 - Gigabit Ethernet MAC project

[Christopher F. <chr...@gm...>]

On 3/8/16 8:48 PM, Harshani Perera wrote:
> Hi all, Â  Â  Â  Â  I a third year Integrated Computer Engineering
> undergraduate at University of Moratuwa Sri Lanka.         I
> would like to start on Gigabit Ethernet MAC project for GSoC 2016 as
> this project seems really interesting, mainly because I'm quite
> familiar with digital circuits, Verilog, Python, Ethernet standards
> and protocols.         If you could provide me more details on
> this project, then it would be help full for me to getting started
> with this project.Â

Harshani,

Thank you for the inquiry, more information about the
project can be found here:
http://dev.myhdl.org/gsoc/gsoc_2016.html#gigabit-ethernet-mac

Note, we have had many students inquire about GSoC this
year.  We already have a student preparing an application
for the GEMAC.  You are welcome to also prepare an application
but precedence will be given on a first contact.

Regards,
Chris

[myhdl-list] GSoC 2016 - Gigabit Ethernet MAC project

[Harshani P. <ire...@cs...>]

Hi all,
        I a third year Integrated Computer Engineering undergraduate at
University of Moratuwa Sri Lanka.
        I would like to start on Gigabit Ethernet MAC project for GSoC 2016
as this project seems really interesting, mainly because I'm quite familiar
with digital circuits, Verilog, Python, Ethernet standards and protocols.
        If you could provide me more details on this project, then it would
be help full for me to getting started with this project.

Thank you.

Best Regards
-- 
*Iresha Perera*
Department of Integrated Computer Engineering
University of Moratuwa
Mobile : +94777863874
<https://lk.linkedin.com/in/ireshaharshani>

[myhdl-list] [GSoc 16] Regarding JPEG Encoder

[Vikram P. <vik...@st...>]

Hi,
I would love to work on JPEG Encoder as a part of GSoC. 

I have previous experience of Verilog, VHDL. I have synthesised 2D-DCT 
module (an implementation of Chenn's Algorithm), Quantiser and FIFO 
working modules along with their test bench in Verilog.I have a decent 
experience with python and have a good experience with designing VLSI 
architectures and Digital circuits.

I would love to know more about the project and how to get started.

Thanks,
Vikram
Electronics and Communication Engineering
IIIT Hyderabad

Re: [myhdl-list] GSoC'16 | JPEG Encoder

[Christopher F. <chr...@gm...>]

On 3/3/2016 1:37 AM, Nicolas Pinault wrote:
> Hi, Le 02/03/2016 15:09, Henry Gomersall a écrit :
>> On 02/03/16 13:59, Henry Gomersall wrote:
>>> E.g. when the DSP has to be pipelined to maximize throughput,
>>> it's no longer just a multiplier and the code has to reflect
>>> that. You could create a multiplier block with pipeline stages
>>> incorporated, but then you're more or less doing as I suggest
>>> (and still with no guarantees the synthesizer will do the right
>>> thing).
>> I wrote an inline complex multiplier based around a single DSP
>> which really gets into the guts of the DSP core. It's hard to see
>> how one would do this in plain VHDL with a hope that it would be
>> inferred correctly (the difficulty is in things like flicking
>> control registers mid pipeline from multiply-add to
>> multiply-accumulate to multiply-deccumulate).

> I have discovered MyHDL recently and considering using it. I have
> followed your discussion and get questions : - How is it possible to
> "switch" the underlying resources  ("inner primitive blocks can be
> switched") ? - Why do you say you can do things with MyHDL but not
> VHDL (your complex multiplier) ?
>
> Nicolas

In Python (and myhdl) it is easier to manage all this
complex information.  If you want to write a module
that is a portable across technologies as possible
but in most cases requires using a specific primitive
in Python/myhdl you could right something like:

     def my_module(portmap, techinfo):
         ven, dev = techinfo.vendor, techinfo.device
         if ven in modprim and dev in modprim[ven]:
             prim_inst = modprim[ven][dev](prim_intf)
         else:
             prim_inst = prim_beh(prim_intf)


You might be able to do this in VHDL but it would be
more cumbersome and not as many tools and features to
help manage.  The difficult part is coming up with a
generic interface that can map to all the various prims,
if not then you need a specific module that uses each
specific primitive and select on the modules not the
primitives.

That is assuming you want to explicitly instantiate
a primitive that you have wrapper with user-defined
code.  As the other comments have discussed, using
similar approaches you can drive the organization base
on a the parameters.

Regards,
Chris