myhdl-list — Mailing list for discussions on MyHDL

Re: [myhdl-list] All inputs no output with generated Verilog and VHDL

[Edward V. <dev...@sb...>]

Hello Josy,
I thought that items on left were outputs and items on the right were inputs.  I was trying to follow an example  posted  Raman Muthukishnan.
I just wanted signals that  were arrays.   Since these are, I assuming shadow signals that is why I am not getting any output.  This is a new topic for me and I have not worked with shadow signals before.  What must I do to get the res_out_x or res_out_x_i to be and output?   This must be a really bad question.  I do appreciate all the help.


Edward Vidal Jr.
e-mail dev...@sb...
915-595-1613


On Sunday, February 8, 2015 7:44 AM, Josy Boelen <jos...@gm...> wrote:
 


Edward Vidal <develone <at> sbcglobal.net> writes:

> 
> 
> Hello All,I am using the following python code to generate my Verilog 
and VHDL fileshttps://github.com/develone/jpeg-2000-
test/blob/master/jpeg2k/parallel_jpeg/array_jpeg.pyThe files get created 
which are the following two fileshttps://github.com/develone/jpeg-2000-
test/blob/master/jpeg2k/parallel_jpeg/jp_process.vhdand 
https://github.com/develone/jpeg-2000-
test/blob/master/jpeg2k/parallel_jpeg/jp_process.vThe V
>  HDL file when I try to synthesize I get the error"Use <= to assign to 
signal res_out_x".  Changing the 4 lines where ":=:" appears to
>  "<="res_out_x((LVL0 - 1)) := (sam_s((LVL0 - 1)) - 
(shift_right(left_s((LVL0 - 1)), 1) + shift_right(right_s((LVL0 - 1)), 
1)));Process "Synthesize - XST" completed successfullyMentity jp_process 
is    port (        sig_in_x_i: in unsigned(15 downto 0);        
res_out_x_i: in unsigned(15 downto 0);        left_s_i: in unsigned(15 
downto 0);        sam_s_i: in unsigned(15 downto 0);        right_s_i: 
in unsigned(15 downto 0);        flgs_s_i:
>  in unsigned(9 downto 0)    );end entity jp_process;The Verilog file 
has no problem with the Synthesize.  I generated a Test 
Bedhttps://github.com/develone/jpeg-2000-
test/blob/master/jpeg2k/parallel_jpeg/TBjp_process.vI am not able to see 
get the output signalhttps://github.com/develone/jpeg-2000-
test/blob/master/jpeg2k/parallel_jpeg/nooutput.GIFAny and all help is 
appreciated.Thanks
>  <snip>
>My entity are all inputs. How do you access the output?

What'd you expect? If you don't declare outputs, you just don't have 
any. MyHDL gets mixed up between variables and signals, but I wouldn't 
blame MyHDL for that. That the Verilog converted code synthesizes is 
just a fluke (I guess to do with blocking and non-blocking?). If you let 
ISE go all the way, you very probably end up with  everything optimised 
away.
Our BDFL would say, simulate first then convert ... After all, one of 
the greatest features of MyHDL is in Simulation

Regards,

Josy



------------------------------------------------------------------------------
Dive into the World of Parallel Programming. The Go Parallel Website,
sponsored by Intel and developed in partnership with Slashdot Media, is your
hub for all things parallel software development, from weekly thought
leadership blogs to news, videos, case studies, tutorials and more. Take a
look and join the conversation now. http://goparallel.sourceforge.net/
_______________________________________________
myhdl-list mailing list
myh...@li...
https://lists.sourceforge.net/lists/listinfo/myhdl-list

Re: [myhdl-list] All inputs no output with generated Verilog and VHDL

[Josy B. <jos...@gm...>]

Edward Vidal <develone <at> sbcglobal.net> writes:

> 
> 
> Hello All,I am using the following python code to generate my Verilog 
and VHDL fileshttps://github.com/develone/jpeg-2000-
test/blob/master/jpeg2k/parallel_jpeg/array_jpeg.pyThe files get created 
which are the following two fileshttps://github.com/develone/jpeg-2000-
test/blob/master/jpeg2k/parallel_jpeg/jp_process.vhdand 
https://github.com/develone/jpeg-2000-
test/blob/master/jpeg2k/parallel_jpeg/jp_process.vThe V
>  HDL file when I try to synthesize I get the error"Use <= to assign to 
signal res_out_x".  Changing the 4 lines where ":=:" appears to
>  "<="res_out_x((LVL0 - 1)) := (sam_s((LVL0 - 1)) - 
(shift_right(left_s((LVL0 - 1)), 1) + shift_right(right_s((LVL0 - 1)), 
1)));Process "Synthesize - XST" completed successfullyMentity jp_process 
is    port (        sig_in_x_i: in unsigned(15 downto 0);        
res_out_x_i: in unsigned(15 downto 0);        left_s_i: in unsigned(15 
downto 0);        sam_s_i: in unsigned(15 downto 0);        right_s_i: 
in unsigned(15 downto 0);        flgs_s_i:
>  in unsigned(9 downto 0)    );end entity jp_process;The Verilog file 
has no problem with the Synthesize.  I generated a Test 
Bedhttps://github.com/develone/jpeg-2000-
test/blob/master/jpeg2k/parallel_jpeg/TBjp_process.vI am not able to see 
get the output signalhttps://github.com/develone/jpeg-2000-
test/blob/master/jpeg2k/parallel_jpeg/nooutput.GIFAny and all help is 
appreciated.Thanks
>  <snip>
>My entity are all inputs. How do you access the output?

What'd you expect? If you don't declare outputs, you just don't have 
any. MyHDL gets mixed up between variables and signals, but I wouldn't 
blame MyHDL for that. That the Verilog converted code synthesizes is 
just a fluke (I guess to do with blocking and non-blocking?). If you let 
ISE go all the way, you very probably end up with  everything optimised 
away.
Our BDFL would say, simulate first then convert ... After all, one of 
the greatest features of MyHDL is in Simulation

Regards,

Josy

[myhdl-list] All inputs no output with generated Verilog and VHDL

[Edward V. <dev...@sb...>]

Hello All,

I am using the following python code to generate my Verilog and VHDL files
https://github.com/develone/jpeg-2000-test/blob/master/jpeg2k/parallel_jpeg/array_jpeg.py
The files get created which are the following two files
https://github.com/develone/jpeg-2000-test/blob/master/jpeg2k/parallel_jpeg/jp_process.vhd
and https://github.com/develone/jpeg-2000-test/blob/master/jpeg2k/parallel_jpeg/jp_process.v

The VHDL file when I try to synthesize I get the error
"Use <= to assign to signal res_out_x".  Changing the 4 lines where ":=:" appears to "<="
res_out_x((LVL0 - 1)) := (sam_s((LVL0 - 1)) - (shift_right(left_s((LVL0 - 1)), 1) + shift_right(right_s((LVL0 - 1)), 1)));
Process "Synthesize - XST" completed successfully
My entity are all inputs. How do you access the output?
entity jp_process is
    port (
        sig_in_x_i: in unsigned(15 downto 0);
        res_out_x_i: in unsigned(15 downto 0);
        left_s_i: in unsigned(15 downto 0);
        sam_s_i: in unsigned(15 downto 0);
        right_s_i: in unsigned(15 downto 0);
        flgs_s_i: in unsigned(9 downto 0)
    );
end entity jp_process;

The Verilog file has no problem with the Synthesize.  I generated a Test Bed
https://github.com/develone/jpeg-2000-test/blob/master/jpeg2k/parallel_jpeg/TBjp_process.v
I am not able to see get the output signal
https://github.com/develone/jpeg-2000-test/blob/master/jpeg2k/parallel_jpeg/nooutput.GIF
Any and all help is appreciated.
Thanks


 
Edward Vidal Jr.
e-mail dev...@sb...
915-595-1613

Re: [myhdl-list] shadow signal signals signed instead of unsigned

[Christopher F. <chr...@gm...>]

<snip>
> After seeing the posting by Raman Muthukishnan
>   On shadow signals how would you modify the code to have an array of signed signals rather than unsigned.
<snip>

In [35]: x = Signal(intbv(-7, min=-32, max=32))

# bit access
In [36]: x[4:0]
Out[36]: intbv(9L)

In [37]: x[4:0].signed()
Out[37]: -7L


# shadow signal
In [39]: x(4,0)
Out[39]: Signal(intbv(9L))
In [40]: x(4,0).signed()
Out[40]: -7L

Note, you would want to make the shadow signal:

    slc = x(4,0)

and then when assigning get the signed vers

    #...
    y = slc.signed()

Hope that helps,
Chris

[myhdl-list] shadow signal signals signed instead of unsigned

[Edward V. <dev...@sb...>]

    

    ⌂ Home
    👤 Edward
    ⚙ Help

Press ? for keyboard shortcuts.















































































shadow signals signed instead of unsigned
me
To
myh...@li...
Today at 7:26 AM
Hello all,
As Raman posted
Thank you very much for MyHDL. I do not know where I would be in my learning process of VHDL without MyHDL.

After seeing the posting by Raman Muthukishnan
 On shadow signals how would you modify the code to have an array of signed signals rather than unsigned.
For signed I normally use
This format res15_s = Signal(intbv(0, min = -JPEG_DATA_WIDTH, max = JPEG_DATA_WIDTH)).
This is the example posted by Raman below

from myhdl import *
def iso_pricing_check(ask_price_levels_i,price_o,WIDTH=24,NUM_LEVELS=4):
  # this line of code of slicing the signal and generating list of shadow signals is
  # not getting translated into verilog.
  ask_price_levels = [ask_price_levels_i((i+1)*WIDTH, i*WIDTH) for i in range(0, NUM_LEVELS)]
  @always_comb
  def ask_price_logic():
    # just giving the last level price as output
    price_o = ask_price_levels[NUM_LEVELS-1]
  return instances()
def convert():
    WIDTH = 32
    NUM_LEVELS = 16
    ask_price_levels_i = Signal(intbv(0)[NUM_LEVELS*24:])
    price_o = Signal(intbv(0)[WIDTH:])
    dut = toVHDL(iso_pricing_check,ask_price_levels_i,price_o,
               WIDTH=WIDTH,NUM_LEVELS=NUM_LEVELS)
convert()
I appreciate any and all help.

 
Edward Vidal Jr.
e-mail dev...@sb...
915-595-1613

Re: [myhdl-list] assert and synthesizable code

[Henry G. <he...@ca...>]

On 03/02/15 20:40, Christopher Felton wrote:
> On 1/29/2015 11:38 AM, Henry Gomersall wrote:
>> >Not being terribly au fait with what is and is not synthesizable Verilog
>> >or VHDL, are python asserts converted into something that is
>> >synthesizable (or at least, will pass through the synthesis stage)?
>> >
>> >Is the better way to put the assert in a `if __debug__:` clause if I
>> >don't want it synthesized?
>> >
> Asserts with convert to something that is ignored
> by most synthesis tools.  I forget are you mainly
> targeting Verilog or VHDL?

Good question! Mainly VHDL, but with Verilog as a bonus :)

Henry

Re: [myhdl-list] Shadow signal

[Christopher F. <chr...@gm...>]

On 2/3/2015 3:55 PM, Raman Muthukrishnan wrote:
> Hi Chris,
> Thank you for your email.
> This is the line of code that is not getting translated.     ask_price_levels = [ask_price_levels_i((i+1)*WIDTH, i*WIDTH) for i in range(0, NUM_LEVELS)]

Yes, definitely.  That line exists outside of
the MyHDL generator (the code in the function
decorated by an @alway*).  This is what we call
the elaboration code, this code will not be
converted.

This line is creating a bunch of references to
the bits in ask_price_levels_i, two different
structures to represent (access) the same thing.

Yes, you should be able to use this to split
the input bus (as readers only) but it all
depends on how you use ask_price_levels after
creating all the shadows.

Hope that helps,
Chris

Re: [myhdl-list] Shadow signal

[Raman M. <rmu...@ho...>]

Hi Chris,
Thank you for your email.
This is the line of code that is not getting translated.     ask_price_levels = [ask_price_levels_i((i+1)*WIDTH, i*WIDTH) for i in range(0, NUM_LEVELS)]
What I am trying to achieve here is to split the 96-bit input bus  into four 24-bit signals.
In verilog we can see the declaration,  "wire ask_price_levels [0:4-1];", but there is no assignment to it.I was expecting  assignments like:   assign ask_price_levels[0] = ask_price_levels_i[23:0]   assign ask_price_levels[1] = ask_price_levels_i[46:23]

I did not write a test case for it as I was checking if I can write in such a way to split the input bus.
Thank you,Raman

> To: myh...@li...
> From: chr...@gm...
> Date: Tue, 3 Feb 2015 14:49:41 -0600
> Subject: Re: [myhdl-list] Shadow signal
> 
> On 1/27/2015 1:13 PM, Raman Muthukrishnan wrote:
> > Hi All,
> >
> > Thank you very much for MyHDL. We have been able to use it successfully for our projects.
> > I am facing one issue, and here my understanding is weak.The line of code that  creates a list of shadow signals from the input bus is not getting translated to verilog.I do not know what I am doing wrong or am missing. If you have any suggestion, it will be very helpful for me.
> 
> I don't think I understand your question or the
> code example doesn't demonstrate the error.
> 
> With 0.9dev the code appears to convert to what
> is described?  Does your testbench indicate the
> module works?
> 
> Regards,
> Chris
> 
> ~~~[Example converted code for the example]~~~
> module iso_pricing_check (
>      ask_price_levels_i,
>      price_o
> );
> 
> 
> input [95:0] ask_price_levels_i;
> output [23:0] price_o;
> wire [23:0] price_o;
> 
> 
> wire [23:0] ask_price_levels [0:4-1];
> 
> 
> 
> 
> 
> assign price_o = ask_price_levels[(4 - 1)];
> 
> endmodule
> 
> 
> 
> 
> ------------------------------------------------------------------------------
> Dive into the World of Parallel Programming. The Go Parallel Website,
> sponsored by Intel and developed in partnership with Slashdot Media, is your
> hub for all things parallel software development, from weekly thought
> leadership blogs to news, videos, case studies, tutorials and more. Take a
> look and join the conversation now. http://goparallel.sourceforge.net/
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
 		 	   		  

Re: [myhdl-list] Shadow signal

[Christopher F. <chr...@gm...>]

On 1/27/2015 1:13 PM, Raman Muthukrishnan wrote:
> Hi All,
>
> Thank you very much for MyHDL. We have been able to use it successfully for our projects.
> I am facing one issue, and here my understanding is weak.The line of code that  creates a list of shadow signals from the input bus is not getting translated to verilog.I do not know what I am doing wrong or am missing. If you have any suggestion, it will be very helpful for me.

I don't think I understand your question or the
code example doesn't demonstrate the error.

With 0.9dev the code appears to convert to what
is described?  Does your testbench indicate the
module works?

Regards,
Chris

~~~[Example converted code for the example]~~~
module iso_pricing_check (
     ask_price_levels_i,
     price_o
);


input [95:0] ask_price_levels_i;
output [23:0] price_o;
wire [23:0] price_o;


wire [23:0] ask_price_levels [0:4-1];





assign price_o = ask_price_levels[(4 - 1)];

endmodule

Re: [myhdl-list] assert and synthesizable code

[Christopher F. <chr...@gm...>]

On 1/29/2015 11:38 AM, Henry Gomersall wrote:
> Not being terribly au fait with what is and is not synthesizable Verilog
> or VHDL, are python asserts converted into something that is
> synthesizable (or at least, will pass through the synthesis stage)?
>
> Is the better way to put the assert in a `if __debug__:` clause if I
> don't want it synthesized?
>

Asserts with convert to something that is ignored
by most synthesis tools.  I forget are you mainly
targeting Verilog or VHDL?

Regards,
Chris


~~~[Example]~~~
     def m_assert(clock, reset, inc, load, x, y):
         @always_seq(clock.posedge, reset=reset)
         def rtl():
             assert inc != load
             if inc:
                 y.next = y + 1
             elif load:
                 y.next = x
         return rtl


     clock = Signal(bool(0))
     reset = ResetSignal(0, active=0, async=True)
     inc,load = [Signal(bool(0)) for _ in range(2)]
     x,y = [Signal(intbv(0)[16:0]) for _ in range(2)]
     toVerilog(m_assert, clock, reset, inc, load, x, y)

~~~
     // snip of the converted verilog
     always @(posedge clock, negedge reset) begin: M_ASSERT_RTL
         if (reset == 0) begin
             y <= 0;
         end
         else begin
             if ((inc != load) !== 1) begin
                 $display("*** AssertionError ***");
             end
             if (inc) begin
                 y <= (y + 1);
             end
             else if (load) begin
                 y <= x;
             end
         end
     end

Re: [myhdl-list] Is it time for 0.9 release?

[Christopher F. <chr...@gm...>]

On 2/1/2015 2:57 PM, Jan Decaluwe wrote:
<snip>
>> I think 0.9 could be released, thoughts?
>
> I agree, but I have not been able to use the new features
> myself yet.
>
> First, do all the tests run? I thought there were still
> some issues.
>

I had forgotten there was a failing test, as @jck mentioned
he has a fix for it.  Once he creates a PR we will be
good to go with regression tests (I believe).

> Most importantly - documentation? There should be something
> in the manual. And also a whatsnew document so that people
> know the purpose of the release.

With the original PR there is a small start to
the documentation in the "What's new" section [1],
but it needs more!  I will look to @jck to
provide some details in the conversion section.

The interfaces need to be added to the manual as well.
Should it have its own section?  Or should it be
sprinkled throughout the manual, e.g. a mention in the
"signal, ports, and concurrency" section [2] and ...?

It sounds like we all agree, we can start working
towards a release.  That is, preparing documentation
and smoothing any rough corners.  The main feature
in this release is *interfaces* MEP107.

Regards,
Chris

[1] 
https://bitbucket.org/jandecaluwe/myhdl/src/f7a6b2ef05bbf418349d8b0021d81b4fc83b8ce0/doc/source/whatsnew/0.9.rst?at=0.9-dev
[2] 
http://docs.myhdl.org/en/latest/manual/intro.html#signals-ports-and-concurrency

Re: [myhdl-list] Is it time for 0.9 release?

[Keerthan JC <jck...@gm...>]

All the core and verilog tests are passing on my branch. Some VHDL
conversion tests are failing on both stable and dev versions.
I still need to fine tune the top level ports naming scheme. I think we
will be ready for releasing after that.

On Sun, Feb 1, 2015 at 3:57 PM, Jan Decaluwe <ja...@ja...> wrote:

> On 12/30/2014 03:42 PM, Christopher Felton wrote:
> > I think it is time for the 0.9 release, the major
> > feature in 0.9 is the interfaces.  Some have been
> > using the interfaces for awhile and there are no
> > obvious issues.
> >
> > I think 0.9 could be released, thoughts?
>
> I agree, but I have not been able to use the new features
> myself yet.
>
> First, do all the tests run? I thought there were still
> some issues.
>
> Most importantly - documentation? There should be something
> in the manual. And also a whatsnew document so that people
> know the purpose of the release.
>
> I think there is one really major feature and that we
> should set the spotlight on it to get attention. It's a
> good example of how we can support functionality which
> is not necessarily present in the target languages.
>
> Jan
>
> --
> Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
>      Python as a HDL: http://www.myhdl.org
>      VHDL development, the modern way: http://www.sigasi.com
>      World-class digital design: http://www.easics.com
>
>
>
> ------------------------------------------------------------------------------
> Dive into the World of Parallel Programming. The Go Parallel Website,
> sponsored by Intel and developed in partnership with Slashdot Media, is
> your
> hub for all things parallel software development, from weekly thought
> leadership blogs to news, videos, case studies, tutorials and more. Take a
> look and join the conversation now. http://goparallel.sourceforge.net/
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>



-- 
have a nice day
-jck

Re: [myhdl-list] Is it time for 0.9 release?

[Jan D. <ja...@ja...>]

On 12/30/2014 03:42 PM, Christopher Felton wrote:
> I think it is time for the 0.9 release, the major
> feature in 0.9 is the interfaces.  Some have been
> using the interfaces for awhile and there are no
> obvious issues.
>
> I think 0.9 could be released, thoughts?

I agree, but I have not been able to use the new features
myself yet.

First, do all the tests run? I thought there were still
some issues.

Most importantly - documentation? There should be something
in the manual. And also a whatsnew document so that people
know the purpose of the release.

I think there is one really major feature and that we
should set the spotlight on it to get attention. It's a
good example of how we can support functionality which
is not necessarily present in the target languages.

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     World-class digital design: http://www.easics.com

[myhdl-list] assert and synthesizable code

[Henry G. <he...@ca...>]

Not being terribly au fait with what is and is not synthesizable Verilog 
or VHDL, are python asserts converted into something that is 
synthesizable (or at least, will pass through the synthesis stage)?

Is the better way to put the assert in a `if __debug__:` clause if I 
don't want it synthesized?

Cheers,

Henry

Re: [myhdl-list] Shadow signal

[Raman M. <rmu...@ho...>]

One mistake in the sample code: 
The output assignment should be:
price_o.next = ask_price_levels[NUM_LEVELS-1]

 		 	   		  

[myhdl-list] Shadow signal

[Raman M. <rmu...@ho...>]

Hi All,

Thank you very much for MyHDL. We have been able to use it successfully for our projects.
I am facing one issue, and here my understanding is weak.The line of code that  creates a list of shadow signals from the input bus is not getting translated to verilog.I do not know what I am doing wrong or am missing. If you have any suggestion, it will be very helpful for me.
Below is the sample code:
from myhdl import *
def iso_pricing_check(                        ask_price_levels_i,                        price_o,
                        WIDTH=24,                        NUM_LEVELS=4                     ):

  # this line of code of slicing the signal and generating list of shadow signals is  # not getting translated into verilog.  ask_price_levels = [ask_price_levels_i((i+1)*WIDTH, i*WIDTH) for i in range(0, NUM_LEVELS)]
  @always_comb  def ask_price_logic():    # just giving the last level price as output    price_o = ask_price_levels[NUM_LEVELS-1]
  return instances()
def convert():    WIDTH = 24    NUM_LEVELS = 4
    ask_price_levels_i = Signal(intbv(0)[NUM_LEVELS*24:])    price_o = Signal(intbv(0)[WIDTH:])

    dut = toVerilog(    iso_pricing_check,                        ask_price_levels_i,                        price_o,
                        WIDTH=WIDTH,                        NUM_LEVELS=NUM_LEVELS,                     )
if __name__ == "__main__":  convert()

Thank you very much,Raman 		 	   		  

Re: [myhdl-list] Top level method conversion

[Henry G. <he...@ca...>]

On 24/01/15 00:06, Christopher Felton wrote:
> On 1/23/15, 4:08 PM, Henry Gomersall wrote:
>> >MEP 108 describes the conversion of top-level methods.
>> >
>> >Please forgive me for being stupid here, but I have a few questions:
>> >
>> >"top-level" in the nomenclature means the outer most collection of
>> >instances, is this correct? It is the most broad view of the design.
>> >Given the hierarchy is flattened, is this simply a conceptual
>> >convenience, or is there more to it than that? (i.e. could one manually
>> >flatten the hierarchy and end up with much the same thing, so top level
>> >would be just "all the instances"?).
> Kinda, you still need to define the top-level ports,
> somehow.
>
>   > Or does it only convey meaning in
>   > the conversion process - It is the outer most factory function?
>
> Yes, the top-level ports.

And presumably, if this was your project top-level, there would be no 
ports (as everything would be a sub-entity?).

>> >Is there a clear use case example of when the mep 108 work would be
>> >useful? In my mind, the main benefit of classes is they retain and
>> >modify state at run-time, which seems to be of little value when
>> >creating instances (at least in the convertible case), but perhaps I'm
>> >missing something?
> If you embed a top-level in a class definition then
> the top-level can be converted without a separate
> function wrapper or not including the HDL in the
> object (i.e. passing the object properties to the
> function module parameters).
>
> I have used this approach with filters.  I can have
> a filter class that I pass high level parameters,
> extract frequency response etc. and include the
> HDL in the "filter" object.  Then if I want I can
> convert (as a top-level) the HDL method in the object.
>

Ok, that makes sense. It's a pythonic convenience to manipulate 
top-level objects.

Thanks for that!

Henry

Re: [myhdl-list] Top level method conversion

[Christopher F. <chr...@gm...>]

On 1/23/15, 4:08 PM, Henry Gomersall wrote:
> MEP 108 describes the conversion of top-level methods.
>
> Please forgive me for being stupid here, but I have a few questions:
>
> "top-level" in the nomenclature means the outer most collection of
> instances, is this correct? It is the most broad view of the design.
> Given the hierarchy is flattened, is this simply a conceptual
> convenience, or is there more to it than that? (i.e. could one manually
> flatten the hierarchy and end up with much the same thing, so top level
> would be just "all the instances"?).

Kinda, you still need to define the top-level ports,
somehow.

 > Or does it only convey meaning in
 > the conversion process - It is the outer most factory function?

Yes, the top-level ports.

> Is there a clear use case example of when the mep 108 work would be
> useful? In my mind, the main benefit of classes is they retain and
> modify state at run-time, which seems to be of little value when
> creating instances (at least in the convertible case), but perhaps I'm
> missing something?

If you embed a top-level in a class definition then
the top-level can be converted without a separate
function wrapper or not including the HDL in the
object (i.e. passing the object properties to the
function module parameters).

I have used this approach with filters.  I can have
a filter class that I pass high level parameters,
extract frequency response etc. and include the
HDL in the "filter" object.  Then if I want I can
convert (as a top-level) the HDL method in the object.

>
> As I understand it, for convertible code one should not really be
> modifying attributes on self inside an instance (and given all my
> previous comments, I imagine accessing attributes on self would cause
> conversion problems).

No it should not cause conversion problems with
MEP 107 implemented (if I understand the question,
correctly).

Regards,
Chris

[myhdl-list] Top level method conversion

[Henry G. <he...@ca...>]

MEP 108 describes the conversion of top-level methods.

Please forgive me for being stupid here, but I have a few questions:

"top-level" in the nomenclature means the outer most collection of 
instances, is this correct? It is the most broad view of the design. 
Given the hierarchy is flattened, is this simply a conceptual 
convenience, or is there more to it than that? (i.e. could one manually 
flatten the hierarchy and end up with much the same thing, so top level 
would be just "all the instances"?). Or does it only convey meaning in 
the conversion process - It is the outer most factory function?

Is there a clear use case example of when the mep 108 work would be 
useful? In my mind, the main benefit of classes is they retain and 
modify state at run-time, which seems to be of little value when 
creating instances (at least in the convertible case), but perhaps I'm 
missing something?

As I understand it, for convertible code one should not really be 
modifying attributes on self inside an instance (and given all my 
previous comments, I imagine accessing attributes on self would cause 
conversion problems).

Cheers,

Henry

Re: [myhdl-list] Is there something in MyHDL equivalent to Verilog's OOMR?

[Robert P. <bpe...@xt...>]

Thank you for responding, Christopher.
Bob P

-----Original Message-----
From: Christopher Felton [mailto:chr...@gm...] 
Sent: Friday, January 23, 2015 10:19 AM
To: myh...@li...
Subject: Re: [myhdl-list] Is there something in MyHDL equivalent to
Verilog's OOMR?

On 1/23/2015 8:03 AM, Robert Peruzzi wrote:
> Jan,
>
> That clarifies the terminology.  Is there a way to read a variable in 
> one circuit block from a different circuit block?
>

The answers have been yes but not in an OOMR fashion.  I imagine you are
looking for some examples.  I am willing to provide some but it will be many
days before I can do so.

The topic being discusses is really Python scope and Python scope
accessibility.

I think it is worth considering if OOMR is the correct approach.  I am sure
the Python communities, while working with whitebox/clearbox testings, have
discussed this type of access (i.e. easily accessing internals).

A tweak on the approach Jan suggested would be to create a global dict where
you can drop the signals you want to access:

     #project_globals.py file
     GlobalSignals = {}

     # design file 1
     from project_globals import GlobalSignals

     def model_subcircuit(*ports, name='subckt1'):
        sig1 = ...
        sig2 = ...

        GlobalSignals[name] = dict(sig1=sig1, sig2=seg2)

     # test file 1
     from project_globals import GlobalSignals

     def test():
         ...
         sig1 = GlobalSignals['subckt1']['sig1']

(note the above is example/pseudo code with many shortcuts taken)

If you really prefer hierarchical access with "." vs dictionary key names
you can convert a dict to a GlobalSignal class ...

The above is one option but has the downside of limited scalability and some
extra coding / maintenance (e.g. providing a name).

Regards,
Chris

>
>
> From: ja...@ja... [mailto:ja...@ja...]
> Sent: Thursday, January 22, 2015 6:05 PM
> To: General discussions on MyHDL
> Subject: Re: [myhdl-list] Is there something in MyHDL equivalent to 
> Verilog's OOMR?
>
>
>
>
> I was talking about Python modules and importing them, e.g. to access 
> Signal objects in them.
>
> Sent from Yahoo Mail on Android
> <https://overview.mail.yahoo.com/mobile/?.src=Android>
>
>
> From:"Robert Peruzzi" <bpe...@xt... 
> <mailto:bpe...@xt...> > Date:Thu, Jan 22, 2015 at 22:16
> Subject:Re: [myhdl-list] Is there something in MyHDL equivalent to 
> Verilog's OOMR?
>
> Jan,
> Thank you for your reply.  I don't want to confuse how I use the word 
> module.  A circuit module, like an op-amp or A/D converter is also 
> known as a circuit block.  Let me refer to it in this discussion as a
circuit block.
> So we write a MyHDL model of an Op-Amp circuit block, and that model 
> contains a module for its digital controls (like PowerDown) and 
> separate modules for its bias, power supply and signal inputs?
> Bob P.
>
>
> -----Original Message-----
> From: Jan Decaluwe [mailto:ja...@ja... <javascript:return> ]
> Sent: Thursday, January 22, 2015 4:08 PM
> To: myh...@li... <javascript:return>
> Subject: Re: [myhdl-list] Is there something in MyHDL equivalent to 
> Verilog's OOMR?
>
> On 01/21/2015 11:45 PM, Robert Peruzzi wrote:
>
>> MyHDL is the tool of choice of my new client - for digital design and 
>> verification.  My task is to use MyHDL for modeling analog and 
>> mixed-signal blocks, and tie them into a full chip and its testbench.
>> To do so, I need to find the MyHDL equivalent of Verilog's "out of 
>> module reference" (OOMR).  After a few hours searching, I have not 
>> found it.
>
> Assuming the signals are special so that you can plan for them, you 
> could put them in a separate module, and import that module wherever 
> you need those signals.
>
> Jan
>
> --
> Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
>      Python as a HDL: http://www.myhdl.org
>      VHDL development, the modern way: http://www.sigasi.com
>      World-class digital design: http://www.easics.com
>
>
> ----------------------------------------------------------------------
> ------
> --
> New Year. New Location. New Benefits. New Data Center in Ashburn, VA.
> GigeNET is offering a free month of service with a new server in Ashburn.
> Choose from 2 high performing configs, both with 100TB of bandwidth.
> Higher redundancy.Lower latency.Increased capacity.Completely compliant.
> http://p.sf.net/sfu/gigenet
> _______________________________________________
> myhdl-list mailing list
> myh...@li... <javascript:return> 
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>
>
>
>
> ----------------------------------------------------------------------
> ------
> --
> New Year. New Location. New Benefits. New Data Center in Ashburn, VA.
> GigeNET is offering a free month of service with a new server in Ashburn.
> Choose from 2 high performing configs, both with 100TB of bandwidth.
> Higher redundancy.Lower latency.Increased capacity.Completely compliant.
> http://p.sf.net/sfu/gigenet
> _______________________________________________
> myhdl-list mailing list
> myh...@li... <javascript:return> 
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>
>
>
>
>
>
> ----------------------------------------------------------------------
> -------- New Year. New Location. New Benefits. New Data Center in 
> Ashburn, VA.
> GigeNET is offering a free month of service with a new server in Ashburn.
> Choose from 2 high performing configs, both with 100TB of bandwidth.
> Higher redundancy.Lower latency.Increased capacity.Completely compliant.
> http://p.sf.net/sfu/gigenet
>
>
>
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>



----------------------------------------------------------------------------
--
New Year. New Location. New Benefits. New Data Center in Ashburn, VA.
GigeNET is offering a free month of service with a new server in Ashburn.
Choose from 2 high performing configs, both with 100TB of bandwidth.
Higher redundancy.Lower latency.Increased capacity.Completely compliant.
http://p.sf.net/sfu/gigenet
_______________________________________________
myhdl-list mailing list
myh...@li...
https://lists.sourceforge.net/lists/listinfo/myhdl-list

Re: [myhdl-list] reusable blocks with different interfaces

[Josy B. <jos...@gm...>]

Christopher Felton <chris.felton <at> gmail.com> writes:


>  <at> Josy, the VHDL code you posted on github is
> the hand generated version, correct?  Where in
> the code is the example/situation being discussed?
> 
> Read a quote from Conway the other day: "to be
> a great Mathematician one should be thinking
> about six (at least) things at a time" (summarized).
> 
> Not so sure about that, because I should benefit
> more from my lack of attention to any one thing :)
> 
> Regard,
> Chris
><snip>

The posted code is indeed the hand-crafted one. I re-started on the 
MyHDL translation, but I got stuck on one VHDL construct I cannot 
emulate in MyHDL, so I had to rethink the strategy.
I've added the 'unpolished' MyHDL version to Github.
One note already: I made a few conversion functions, and MyHDL 
duplicates one of them 8 times for every cell, making for a very large 
VHDL IR (18000 lines for a 16 by 9 cell array).
Second note: this is an excellent example to show Henry Gomersall's 
concern for expanding the *enum* functionality. The *pygol* code will 
not convert because: to convert the following
    def to_gol_states( l ):
        if l:
            return  gol_states.ALIVE
        else:
           return gol_states.DEAD

MyHDl has to write:
    function to_gol_states( l : stdLogic ) return **gol_states** is
        ...
but breaks away with:
    AttributeError: 'vhd_enum' object has no attribute 'toStr'

Compare the VHDL and the MyHDL source, and tell me what you think?

Best regards,

Josy

Re: [myhdl-list] reusable blocks with different interfaces

[Christopher F. <chr...@gm...>]

<snip>
>
> I'll post code on Github, later ...

@Josy, the VHDL code you posted on github is
the hand generated version, correct?  Where in
the code is the example/situation being discussed?

Read a quote from Conway the other day: "to be
a great Mathematician one should be thinking
about six (at least) things at a time" (summarized).

Not so sure about that, because I should benefit
more from my lack of attention to any one thing :)

Regard,
Chris

Re: [myhdl-list] Is there something in MyHDL equivalent to Verilog's OOMR?

[Christopher F. <chr...@gm...>]

On 1/23/2015 8:03 AM, Robert Peruzzi wrote:
> Jan,
>
> That clarifies the terminology.  Is there a way to read a variable in one
> circuit block from a different circuit block?
>

The answers have been yes but not in an OOMR
fashion.  I imagine you are looking for some
examples.  I am willing to provide some but
it will be many days before I can do so.

The topic being discusses is really Python
scope and Python scope accessibility.

I think it is worth considering if OOMR is the
correct approach.  I am sure the Python communities,
while working with whitebox/clearbox testings,
have discussed this type of access (i.e. easily
accessing internals).

A tweak on the approach Jan suggested would be
to create a global dict where you can drop the
signals you want to access:

     #project_globals.py file
     GlobalSignals = {}

     # design file 1
     from project_globals import GlobalSignals

     def model_subcircuit(*ports, name='subckt1'):
        sig1 = ...
        sig2 = ...

        GlobalSignals[name] = dict(sig1=sig1, sig2=seg2)

     # test file 1
     from project_globals import GlobalSignals

     def test():
         ...
         sig1 = GlobalSignals['subckt1']['sig1']

(note the above is example/pseudo code with many
shortcuts taken)

If you really prefer hierarchical access with "." vs
dictionary key names you can convert a dict to a
GlobalSignal class ...

The above is one option but has the downside of
limited scalability and some extra coding / maintenance
(e.g. providing a name).

Regards,
Chris

>
>
> From: ja...@ja... [mailto:ja...@ja...]
> Sent: Thursday, January 22, 2015 6:05 PM
> To: General discussions on MyHDL
> Subject: Re: [myhdl-list] Is there something in MyHDL equivalent to
> Verilog's OOMR?
>
>
>
>
> I was talking about Python modules and importing them, e.g. to access Signal
> objects in them.
>
> Sent from Yahoo Mail on Android
> <https://overview.mail.yahoo.com/mobile/?.src=Android>
>
>
> From:"Robert Peruzzi" <bpe...@xt...
> <mailto:bpe...@xt...> >
> Date:Thu, Jan 22, 2015 at 22:16
> Subject:Re: [myhdl-list] Is there something in MyHDL equivalent to Verilog's
> OOMR?
>
> Jan,
> Thank you for your reply.  I don't want to confuse how I use the word
> module.  A circuit module, like an op-amp or A/D converter is also known as
> a circuit block.  Let me refer to it in this discussion as a circuit block.
> So we write a MyHDL model of an Op-Amp circuit block, and that model
> contains a module for its digital controls (like PowerDown) and separate
> modules for its bias, power supply and signal inputs?
> Bob P.
>
>
> -----Original Message-----
> From: Jan Decaluwe [mailto:ja...@ja... <javascript:return> ]
> Sent: Thursday, January 22, 2015 4:08 PM
> To: myh...@li... <javascript:return>
> Subject: Re: [myhdl-list] Is there something in MyHDL equivalent to
> Verilog's OOMR?
>
> On 01/21/2015 11:45 PM, Robert Peruzzi wrote:
>
>> MyHDL is the tool of choice of my new client - for digital design and
>> verification.  My task is to use MyHDL for modeling analog and
>> mixed-signal blocks, and tie them into a full chip and its testbench.
>> To do so, I need to find the MyHDL equivalent of Verilog's "out of
>> module reference" (OOMR).  After a few hours searching, I have not
>> found it.
>
> Assuming the signals are special so that you can plan for them, you could
> put them in a separate module, and import that module wherever you need
> those signals.
>
> Jan
>
> --
> Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
>      Python as a HDL: http://www.myhdl.org
>      VHDL development, the modern way: http://www.sigasi.com
>      World-class digital design: http://www.easics.com
>
>
> ----------------------------------------------------------------------------
> --
> New Year. New Location. New Benefits. New Data Center in Ashburn, VA.
> GigeNET is offering a free month of service with a new server in Ashburn.
> Choose from 2 high performing configs, both with 100TB of bandwidth.
> Higher redundancy.Lower latency.Increased capacity.Completely compliant.
> http://p.sf.net/sfu/gigenet
> _______________________________________________
> myhdl-list mailing list
> myh...@li... <javascript:return>
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>
>
>
>
> ----------------------------------------------------------------------------
> --
> New Year. New Location. New Benefits. New Data Center in Ashburn, VA.
> GigeNET is offering a free month of service with a new server in Ashburn.
> Choose from 2 high performing configs, both with 100TB of bandwidth.
> Higher redundancy.Lower latency.Increased capacity.Completely compliant.
> http://p.sf.net/sfu/gigenet
> _______________________________________________
> myhdl-list mailing list
> myh...@li... <javascript:return>
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>
>
>
>
>
>
> ------------------------------------------------------------------------------
> New Year. New Location. New Benefits. New Data Center in Ashburn, VA.
> GigeNET is offering a free month of service with a new server in Ashburn.
> Choose from 2 high performing configs, both with 100TB of bandwidth.
> Higher redundancy.Lower latency.Increased capacity.Completely compliant.
> http://p.sf.net/sfu/gigenet
>
>
>
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>

Re: [myhdl-list] Is there something in MyHDL equivalent to Verilog's OOMR?

[Robert P. <bpe...@xt...>]

Jan,

That clarifies the terminology.  Is there a way to read a variable in one
circuit block from a different circuit block?

Thank you,

Bob P.

 

 

From: ja...@ja... [mailto:ja...@ja...] 
Sent: Thursday, January 22, 2015 6:05 PM
To: General discussions on MyHDL
Subject: Re: [myhdl-list] Is there something in MyHDL equivalent to
Verilog's OOMR?

 


I was talking about Python modules and importing them, e.g. to access Signal
objects in them.

Sent from Yahoo Mail on Android
<https://overview.mail.yahoo.com/mobile/?.src=Android> 


From:"Robert Peruzzi" <bpe...@xt...
<mailto:bpe...@xt...> >
Date:Thu, Jan 22, 2015 at 22:16
Subject:Re: [myhdl-list] Is there something in MyHDL equivalent to Verilog's
OOMR?

Jan,
Thank you for your reply.  I don't want to confuse how I use the word
module.  A circuit module, like an op-amp or A/D converter is also known as
a circuit block.  Let me refer to it in this discussion as a circuit block.
So we write a MyHDL model of an Op-Amp circuit block, and that model
contains a module for its digital controls (like PowerDown) and separate
modules for its bias, power supply and signal inputs?
Bob P.


-----Original Message-----
From: Jan Decaluwe [mailto:ja...@ja... <javascript:return> ] 
Sent: Thursday, January 22, 2015 4:08 PM
To: myh...@li... <javascript:return> 
Subject: Re: [myhdl-list] Is there something in MyHDL equivalent to
Verilog's OOMR?

On 01/21/2015 11:45 PM, Robert Peruzzi wrote:

> MyHDL is the tool of choice of my new client - for digital design and 
> verification.  My task is to use MyHDL for modeling analog and 
> mixed-signal blocks, and tie them into a full chip and its testbench.
> To do so, I need to find the MyHDL equivalent of Verilog's "out of 
> module reference" (OOMR).  After a few hours searching, I have not 
> found it.

Assuming the signals are special so that you can plan for them, you could
put them in a separate module, and import that module wherever you need
those signals.

Jan

--
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
    Python as a HDL: http://www.myhdl.org
    VHDL development, the modern way: http://www.sigasi.com
    World-class digital design: http://www.easics.com


----------------------------------------------------------------------------
--
New Year. New Location. New Benefits. New Data Center in Ashburn, VA.
GigeNET is offering a free month of service with a new server in Ashburn.
Choose from 2 high performing configs, both with 100TB of bandwidth.
Higher redundancy.Lower latency.Increased capacity.Completely compliant.
http://p.sf.net/sfu/gigenet
_______________________________________________
myhdl-list mailing list
myh...@li... <javascript:return> 
https://lists.sourceforge.net/lists/listinfo/myhdl-list




----------------------------------------------------------------------------
--
New Year. New Location. New Benefits. New Data Center in Ashburn, VA.
GigeNET is offering a free month of service with a new server in Ashburn.
Choose from 2 high performing configs, both with 100TB of bandwidth.
Higher redundancy.Lower latency.Increased capacity.Completely compliant.
http://p.sf.net/sfu/gigenet
_______________________________________________
myhdl-list mailing list
myh...@li... <javascript:return> 
https://lists.sourceforge.net/lists/listinfo/myhdl-list

 

Re: [myhdl-list] Is there something in MyHDL equivalent to Verilog's OOMR?

[<ja...@ja...>]

I was talking about Python modules and importing them, e.g. to access Signal objects in them.

Sent from Yahoo Mail on Android