myhdl-list — Mailing list for discussions on MyHDL

Re: [myhdl-list] enums and non-local

[Jose M. G. C. <ch...@gm...>]

This is a piece of code that does not work. I think it is more or less equivalent to yours.


from myhdl import *

def test(clk, reset, a, b):
    t_state = enum("WAIT", "CALC")
    state = Signal(t_state.WAIT)
    @always_seq(clk.posedge, reset)
    def fsm():
        if state == t_state.WAIT:
            b.next = 0
            state.next = t_state.CALC
        elif state == t_state.CALC:
            a.next = b
            state = t_state.WAIT
    return fsm

clk = Signal(intbv(0)[1:])
reset = ResetSignal(1, active=1, async=False)
a = Signal(intbv(0)[1:])
b = Signal(intbv(0)[1:])

toVHDL(test, clk, reset, a, b)

The error is:

Local variable may be referenced before assignment: state

Thanks for your help,

	Jose M.


> El 11/2/2015, a las 14:45, Christopher Felton <chr...@gm...> escribió:
> 
> On 2/11/2015 1:11 AM, JOSE MARIA GOMEZ CAMA wrote:
>> Hello all,
>> 
>> I am trying to use an enumeration to define the states of a finite state machine. There are examples where it seems to work, but I am not able to do that. Moreover, I have gone through the code and in the _analyze.py module it seems that only intbv are allowed to be seen as non-locals. I assume there is a reason for this filtering, but there is no information. Can anyone provide a hint?
> 
> Do you have an example of the enumeration not working?  I
> have used it many times, you can peruse this example if
> you like:
> https://github.com/schoeberl/comphdl/blob/master/myhdl/vending/vending.py#L31
> 
> Also the examples on the MyHDL website:
> http://www.myhdl.org/examples/sinecomp/#design
> 
> The nonlocals are a little more complicated and will be
> enhanced (!) when porting to Py3k is completed.  In general
> using /intbv/ is the safest approach.
> 
> 
>     def m_some_module(*portmap):
> 
>         myvar = intbv(0, min=-8, max=8)
> 
>         @always...
>         def rtl():
>            myvar[:] = x + 1
>            ...
> 
> 
> Hope that helps,
> Chris
> 
> 
> 
> ------------------------------------------------------------------------------
> Dive into the World of Parallel Programming. The Go Parallel Website,
> sponsored by Intel and developed in partnership with Slashdot Media, is your
> hub for all things parallel software development, from weekly thought
> leadership blogs to news, videos, case studies, tutorials and more. Take a
> look and join the conversation now. http://goparallel.sourceforge.net/
> _______________________________________________
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Re: [myhdl-list] myhdl.AlwaysCombError: signal (startmpy) used as inout in always_comb function argument

[Henry G. <he...@ca...>]

On 11/02/15 15:41, Josy Boelen wrote:
> In a module I have two state machines: one doing overall control and the
> second doing a serial multiply. I (almost always) write two-process
> state machine. As a result I have one @always_comb where the the first
> state machine issues a startpulse to the second and then waits for a
> donepulse from the second to continue. Both state machine have some
> (combinatorial or asynchronous) output signals in common so they have to
> reside in the same (VHDL) process.
<snip>

Do you have some example code?

Henry

[myhdl-list] myhdl.AlwaysCombError: signal (startmpy) used as inout in always_comb function argument

[Josy B. <jos...@gm...>]

In a module I have two state machines: one doing overall control and the 
second doing a serial multiply. I (almost always) write two-process 
state machine. As a result I have one @always_comb where the the first 
state machine issues a startpulse to the second and then waits for a 
donepulse from the second to continue. Both state machine have some 
(combinatorial or asynchronous) output signals in common so they have to 
reside in the same (VHDL) process.

MyHDL then complains that inouts in always_comb are not allowed.

If I comment out some code in _always_comb.py, as shown:
   def visit_Module(self, node):
#         inputs = self.inputs
#         outputs = self.outputs
        for n in node.body:
            self.visit(n)
#         for n in inputs:
#             if n in outputs:
#                 raise AlwaysCombError(_error.SignalAsInout % n)

everything goes fine, the simulation is OK and the VHDL code looks 
plausible as the 'offending' signals are well in the sensitivity list:
  KALMANFILTER_SMCOMB: process (D, smmpyp, yn, CoeffB, CoeffA, shiftc_Q, 
add_Q, mpycount, xnb, StrobeIn, shifta_Q, startmpy, mpydone, smkfp) is


The verilog conversion doesn't complain either and (as far as my Verilog 
knowledge goes) produces a plausible sensitivity list too:
  always @(D, smmpyp, yn, CoeffB, CoeffA, shiftc_Q, add_Q, mpycount, 
xnb, StrobeIn, shifta_Q, startmpy, mpydone, smkfp) begin: 
KALMANFILTER_SMCOMB

Obviously the VHDL will compile fine, I don't know about Verilog. Have I 
broken something?

Regards,

Josy

Re: [myhdl-list] enums and non-local

[Christopher F. <chr...@gm...>]

On 2/11/2015 1:11 AM, JOSE MARIA GOMEZ CAMA wrote:
> Hello all,
>
> I am trying to use an enumeration to define the states of a finite state machine. There are examples where it seems to work, but I am not able to do that. Moreover, I have gone through the code and in the _analyze.py module it seems that only intbv are allowed to be seen as non-locals. I assume there is a reason for this filtering, but there is no information. Can anyone provide a hint?

Do you have an example of the enumeration not working?  I
have used it many times, you can peruse this example if
you like:
https://github.com/schoeberl/comphdl/blob/master/myhdl/vending/vending.py#L31

Also the examples on the MyHDL website:
http://www.myhdl.org/examples/sinecomp/#design

The nonlocals are a little more complicated and will be
enhanced (!) when porting to Py3k is completed.  In general
using /intbv/ is the safest approach.


     def m_some_module(*portmap):

         myvar = intbv(0, min=-8, max=8)

         @always...
         def rtl():
            myvar[:] = x + 1
            ...


Hope that helps,
Chris

Re: [myhdl-list] delays misconverted in VHDL conversion

[Christopher F. <chr...@gm...>]

<snip>
>> Actually the converted code is wrong, the statements like:
>>       constant lowTime: integer := 10;
>>       wait for lowTime ns;
>>
>> are incorrect, they should either be:
>>       constant lowTime: integer := 10;
>>       wait for lowTime * 1.0 ns;
>>
>> or:
>>       constant lowTime: time := 10.0 ns;
>>       wait for lowTime ;
>>
>> Should be easy to fix in the MyHDL code.
>
> Can anyone else comment on whether this wants to be fixed? Happy to
> raise a PR with some form of a fix. I feel this could easily go into 0.9.
>
> My reading of the spec suggests the ns is an integral part of the time
> type, not some general numerical attribute, so I think the failure is
> expected.

It sounds like something that should be fixed, I don't recall
(without taking the time to look it up) the exact VHDL policy
but Joys' and your explanation sounds correct.

I would create an issue [1] and include the complete example (the
small conversion snippet) and include the warning.  With Modelsim
a similar error is thrown.

     $ vcom pck_myhdl_09.vhd clock_driver.vhd
     Model Technology ModelSim ALTERA vcom 10.1e
     Compiler 2013.06 Jun 12 2013
     -- Loading package STANDARD
     -- Loading package TEXTIO
     -- Loading package std_logic_1164
     -- Loading package NUMERIC_STD
     -- Compiling package pck_myhdl_09
     -- Compiling package body pck_myhdl_09
     -- Loading package pck_myhdl_09
     -- Loading package pck_myhdl_09
     -- Compiling entity clock_driver
     -- Compiling architecture MyHDL of clock_driver
     ** Error: clock_driver.vhd(38): near "ns": expecting ';'
     ** Error: clock_driver.vhd(44): VHDL Compiler exiting


After the issue has been created, if you have a fix, created a PR
and someone will decide if it should be part of 0.9 or a later
bug fix release.

And note, Jan has created a nice outline how to contribute to the
project [2].

Regards,
Chris

[1] https://bitbucket.org/jandecaluwe/myhdl/issues?status=new&status=open
[2] http://dev.myhdl.org/guide.html

Re: [myhdl-list] delays misconverted in VHDL conversion

[Henry G. <he...@ca...>]

On 08/02/15 22:22, Josy Boelen wrote:
> Henry Gomersall <heng <at> cantab.net> writes:
>
>> >
>> >I'm trying to do a poor man's RTL co-simulation by creating the files
>> >needed for simulation and the relevant stimulus files (from the MyHDL
>> >simulation), then writing the outputs from the Xilinx simulation to
> file
>> >for post-simulation comparison. For this I need a clock.
>> >
>> >Consider:
>> >
>> >def ClkDriver(clk, period=20):
>> >
>> >      lowTime = int(period/2)
>> >      highTime = period - lowTime
>> >
>> >       <at> instance
>> >      def driveClk():
>> >          while True:
>> >              yield delay(lowTime)
>> >              clk.next = 1
>> >              yield delay(highTime)
>> >              clk.next = 0
>> >
>> >      return driveClk
>> >
>> >This is converted to the following (pertinent) VHDL:
>> >
>> >architecture MyHDL of ClkDriver is
>> >
>> >constant lowTime: integer := 10;
>> >constant highTime: integer := 10;
>> >
>> >begin
>> >
>> >CLKDRIVER_DRIVECLK: process is
>> >begin
>> >      while True loop
>> >          wait for lowTime ns;
>> >          clk <= '1';
>> >          wait for highTime ns;
>> >          clk <= '0';
>> >      end loop;
>> >      wait;
>> >end process CLKDRIVER_DRIVECLK;
>> >
>> >end architecture MyHDL;
>> >
>> >Xilinx Vivado complains this is a syntax error. It doesn't like the
> use
>> >of a constant in the "wait for lowTime ns", though it's easily fixed
>> >with e.g. "wait for 10 ns".
>> >
>> >Is this Vivado being crap, or is this expected behaviour? I could
> always
>> >create my own custom VHDL template, but it would be neater to have
> MyHDL
>> >do it for me.
>> >
>> ><snip>
> Actually the converted code is wrong, the statements like:
>      constant lowTime: integer := 10;
>      wait for lowTime ns;
>
> are incorrect, they should either be:
>      constant lowTime: integer := 10;
>      wait for lowTime * 1.0 ns;
>
> or:
>      constant lowTime: time := 10.0 ns;
>      wait for lowTime ;
>
> Should be easy to fix in the MyHDL code.

Can anyone else comment on whether this wants to be fixed? Happy to 
raise a PR with some form of a fix. I feel this could easily go into 0.9.

My reading of the spec suggests the ns is an integral part of the time 
type, not some general numerical attribute, so I think the failure is 
expected.

Cheers,

Henry

[myhdl-list] enums and non-local

[JOSE M. G. C. <jm....@ub...>]

Hello all,

I am trying to use an enumeration to define the states of a finite state machine. There are examples where it seems to work, but I am not able to do that. Moreover, I have gone through the code and in the _analyze.py module it seems that only intbv are allowed to be seen as non-locals. I assume there is a reason for this filtering, but there is no information. Can anyone provide a hint?

        Thanks in advance,

                Jose M.



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Re: [myhdl-list] Is it time for 0.9 release?

[Christopher F. <chr...@gm...>]

On 2/10/15 12:03 AM, Keerthan JC wrote:
> There are failing VHDL tests: https://travis-ci.org/jck/myhdl/jobs/47472029
>
> Are we planning to fix there before 0.9?
>

That is a good question, I am not sure.  Typically I
would say of course but these tests also fail on 8.1
(see below).

We could mark it as something todo maybe for a 9.1
release.  At this point I don't know why they are
failing or what it might take to fix them.  This would
seem reasonable to me (postpone the fix).

Regards,
Chris


>>> import myhdl
>>> myhdl.__version__
  '0.8.1'

>> ghdl --version
  GHDL 0.29 (20100109) [Sokcho edition]
   Compiled with GNAT Version: 4.6
   GCC back-end code generator
  Written by Tristan Gingold.

>> py.test GHDL.py test_*.py
  ============================= test session starts 
==============================
  platform linux2 -- Python 2.7.5 -- pytest-2.3.5
  collected 83 items

  test_adapter.py .
  test_AssignSignal.py .
  test_bin2gray.py ..
  test_case.py ....
  test_constants.py .
  test_dec.py ....
  test_errors.py ...
  test_fsm.py .
  test_hec.py .
  test_inc.py .....
  test_intbv_signed.py ...
  test_listofsigs.py ............
  test_loops.py ...............
  test_method.py ...
  test_nonlocal.py .
  test_numass.py .
  test_print.py ......
  test_ram.py .....
  test_rom.py ....
  test_ShadowSignal.py .F..
  test_ternary.py F.
  test_toplevel_method.py ....

  =================================== FAILURES 
===================================
  ______________________________ test_ConcatSignal 
_______________________________

      def test_ConcatSignal():
>       assert conversion.verify(bench_ConcatSignal) == 0
  E       assert 1 == 0
  E        +  where 1 = <myhdl.conversion._verify._VerificationClass 
object at 0x2e2ba50>(bench_ConcatSignal)
  E        +    where <myhdl.conversion._verify._VerificationClass 
object at 0x2e2ba50> = conversion.verify

  test_ShadowSignal.py:60: AssertionError
  ------------------------------- Captured stderr 
--------------------------------
  bench_ConcatSignal.vhd:45:19: constant "i" is not visible here
  bench_ConcatSignal.vhd:46:23: constant "j" is not visible here
  bench_ConcatSignal.vhd:47:27: constant "k" is not visible here
  bench_ConcatSignal.vhd:48:31: constant "m" is not visible here
  bench_ConcatSignal.vhd:49:37: prefix is neither a function name nor 
can it be sliced or indexed
  bench_ConcatSignal.vhd:50:30: prefix is neither a function name nor 
can it be sliced or indexed
  bench_ConcatSignal.vhd:51:37: prefix is neither a function name nor 
can it be sliced or indexed
  bench_ConcatSignal.vhd:52:37: prefix is neither a function name nor 
can it be sliced or indexed
  /usr/lib/ghdl/bin/ghdl: compilation error
  Analysis failed
  ________________________________ test_ternary1 
_________________________________

      def test_ternary1():
>       assert conversion.verify(TernaryBench, ternary1) == 0
  E       assert 1 == 0
  E        +  where 1 = <myhdl.conversion._verify._VerificationClass 
object at 0x2e2ba50>(TernaryBench, ternary1)
  E        +    where <myhdl.conversion._verify._VerificationClass 
object at 0x2e2ba50> = conversion.verify

  test_ternary.py:69: AssertionError
  ------------------------------- Captured stderr 
--------------------------------
  TernaryBench.vhd:63:28: ';' is expected instead of 'when'
  /usr/lib/ghdl/bin/ghdl: compilation error
  Analysis failed
  ===================== 2 failed, 81 passed in 57.23 seconds 
=====================

Re: [myhdl-list] Is it time for 0.9 release?

[Keerthan JC <jck...@gm...>]

There are failing VHDL tests: https://travis-ci.org/jck/myhdl/jobs/47472029

Are we planning to fix there before 0.9?

On Mon, Feb 9, 2015 at 6:31 PM, Angel Ezquerra <ang...@gm...>
wrote:

> On Mon, Feb 9, 2015 at 1:32 PM, Henry Gomersall <he...@ca...> wrote:
> > On 09/02/15 12:29, Angel Ezquerra wrote:
> >> I find that the BitBucket UI is not as flashy as
> >> github's but is IMHO easier to use and mercurial is oh so much simpler
> >> than git!
> >
> > I find precisely the opposite. Perhaps it's to do with what tools one is
> > used to.
>
> It was not my intention to start a mercurial vs git flamewar (hence
> the "IMHO" qualifier on my statement above).
>
> Out of curiosity, which part do you disagree with, the github vs
> bitbucket part, the git vs mercurial part or both?
> I'd be inclined to agree with you in that it is a matter of the tool
> you are used to on the first part. On the second one (git vs
> mercurial) not so much :P
>
> Cheers!
>
> Angel
>
>
> ------------------------------------------------------------------------------
> Dive into the World of Parallel Programming. The Go Parallel Website,
> sponsored by Intel and developed in partnership with Slashdot Media, is
> your
> hub for all things parallel software development, from weekly thought
> leadership blogs to news, videos, case studies, tutorials and more. Take a
> look and join the conversation now. http://goparallel.sourceforge.net/
> _______________________________________________
> myhdl-list mailing list
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> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>



-- 
have a nice day
-jck

Re: [myhdl-list] Is it time for 0.9 release?

[Angel E. <ang...@gm...>]

On Mon, Feb 9, 2015 at 1:32 PM, Henry Gomersall <he...@ca...> wrote:
> On 09/02/15 12:29, Angel Ezquerra wrote:
>> I find that the BitBucket UI is not as flashy as
>> github's but is IMHO easier to use and mercurial is oh so much simpler
>> than git!
>
> I find precisely the opposite. Perhaps it's to do with what tools one is
> used to.

It was not my intention to start a mercurial vs git flamewar (hence
the "IMHO" qualifier on my statement above).

Out of curiosity, which part do you disagree with, the github vs
bitbucket part, the git vs mercurial part or both?
I'd be inclined to agree with you in that it is a matter of the tool
you are used to on the first part. On the second one (git vs
mercurial) not so much :P

Cheers!

Angel

[myhdl-list] MyHDL within a kick-starter project ????

[David B. <dav...@ya...>]

I was wondering if anyone out there would be interested in receiving a white paper from me regarding my attempts at developing a kick-starter project (kickstarter.com) for the MyHDL environment ???    Is anyone interested ???  


Thanks,


David Blubaugh

Re: [myhdl-list] Is it time for 0.9 release?

[Jan D. <ja...@ja...>]

On 02/09/2015 01:16 PM, Christopher Felton wrote:
>>> I think 0.9 could be released, thoughts?
>
> There has been some intermingled chatter in other
> threads on different topics and issues.  Below is
> a subset summary per the relevant topics.
>
>
> 0.9 Release
> -----------
> It sounds like there are no blockades for a 0.9
> release and we are moving forward with a 0.9 release.
> Things that need to been completed:
>
>      1. PR from @jck to resolve the failing interface
>         tests.
>      2. Documentation for interfaces.
>      3. Normal release stuff.

Correct.

> The Move
> --------
> There also has been talk about moving to git/github.  I
> assume this will happen after the 0.9 release, correct?

For a variety of reasons, I have basically decided to git
eventually, probably sooner than later. I have not decided
when exactly, I am working with @jck to sort that out.

Note that git is also more prominent than mercurial on
bitbucket, people who prefer that interface can use still
use it for their primary repo's.

@Chris - if you have documentation for 0.9 in your recent
fork, I will gladly pull it in of course.

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     World-class digital design: http://www.easics.com

Re: [myhdl-list] All inputs no output with generated Verilog and VHDL

[Christopher F. <chr...@gm...>]

<snip>
>
> and later add an always_comb function to assemble the output vector
> @always_comb
> def assignouts():
>      for i in range(Y):
>          res_out_x.next[ (i+1)*xx:i*xx] = lres_out_x[i]
>
>
> It would be nice if we can extend MyHDL to do these mappings/assignments
> with less typing.
>

This has come up in a couple threads (not this exact
topic but similar LoS/array things).  I think someone
will need to take some time and think through LoS/arrays.

We have a tricky task, we want to be able to do what the
current HDLs do but we don't want to use the current HDLs
as the benchmark :)  Meaning, we don't want to simply do
something because V* does it.  Things like multi-dimension
array/LoS could use some thought.  What is supported, what
is not, what are the limitations, is it only conversion,
etc.  When we did this exercise with interfaces we discovered
some nice tricks that you could do outside the myhdl
generators.

Regards,
Chris

Re: [myhdl-list] All inputs no output with generated Verilog and VHDL

[Christopher F. <chr...@gm...>]

On 2/9/2015 10:50 AM, Edward Vidal wrote:
> Hello all,
> Thanks to Josy Boelen for getting me this far.
>
> When using arrays,  the output signal or signals, need to be created before the calling the method that creates the arrays and  @always_comb.
> How would you pass a list of signed signals? Or do they need to be signed base on the information provided by Chris Felton.?
>

Let's back up a little bit.  List of Signals (array) is
often used to represent RAM/ROM but it is also used to
logically organize signals [1][2].  If you happen to have
a very large bus you might want to break it down into
smaller logical components.  I am going to call the arrays
list-of-signals (LoS) here.

Couple things to note, LoS cannot be used as final port
interface.  In other words, you cannot convert a LoS as
a top-level port.  In a design LoS can be passed between
modules because the design is flattened.  For an actual
design it is rare that you will have a very large bus
off-chip, in the cases that you do you will need to create
mapping (like Joys example) to flatten the bus.

At this point I don't know what you are trying to achieve,
it is often difficult (i.e. takes time) to figure out your
code just from the source.  As mentioned before, simple
examples of what you are trying to achieve would help.

Here is a simple example.  I want to take a LoS (array)
of some arbitrary size and subtract some constant value
and assign it to a new LoS as the same size of the LoS
passed.

     x = [Signal(intbv(0, min=-88, max=88)
          for _ in range(N)]
     y = [Signal(intbv(0, min=-88, max=88)
          for _ in range(N)]

     def m_los_subtractor(x, y, A=7):
         N = len(x)
         @always_comb
         def rtl():
             for ii in range(N):
                 y[ii].next = x - A
         return rtl

If the above module is used in a design it should work
(disclaimer I didn't debug, there could be a typo).  An
LoS is passed that will hold the values and an LoS that
is passed will be filled with the result.  Also note,
this example is incomplete because it assumes *x* will
always be min+A.

If you are trying to convert module by module and using
LoS as ports, this will be difficult because you will have
to constantly be translating between the large flat bus
and an LoS.

I don't know if ShadowSignals are what you really want,
I would do like Joys example (I think that is what he was
doing) and map between a wide bus and an LoS and not use
ShadowSignals.

Hope this helps,
Chris

[1] 
http://docs.myhdl.org/en/latest/whatsnew/0.6.html#conversion-of-lists-of-signals
[2] 
http://docs.myhdl.org/en/latest/manual/conversion_examples.html#ram-inference 

Re: [myhdl-list] All inputs no output with generated Verilog and VHDL

[Edward V. <dev...@sb...>]

Hello all,
Thanks to Josy Boelen for getting me this far.

When using arrays,  the output signal or signals, need to be created before the calling the method that creates the arrays and  @always_comb.
How would you pass a list of signed signals? Or do they need to be signed base on the information provided by Chris Felton.?

My code  is located at

https://github.com/develone/jpeg-2000-test/tree/master/jpeg2k/parallel_jpeg

array_jpeg.py, jpeg_constants.py, jp_process.v, and jp_process.vhd.
These 4 arrays are going to be on the order of 8192 bits wide for 3 arrays and 1 of 5120 bits wide. 

What method would you recommend for setting the values of these arrays 4 ram or 4 fifo instances?  

How do you determine which takes more resources?
Thanks, I do appreciate all the help.
  


 
Edward Vidal Jr.
e-mail dev...@sb...
915-595-1613


On Sunday, February 8, 2015 2:12 PM, Josy Boelen <jos...@gm...> wrote:
 


Edward Vidal <develone <at> sbcglobal.net> writes:

> 
> 
> Hello Josy,
> 
> I thought that items on left were outputs and items on the right were 
inputs.  I was trying to follow an example  posted  Raman Muthukishnan.
> 
> I just wanted signals that  were arrays.   Since these are, I assuming 
shadow signals that is why I am not getting any output.  This is a new 
topic
 for me and I have not worked with shadow signals before.  What 
must I do to get the res_out_x or res_out_x_i to be and output?   This 
must be a really bad question.  I do appreciate all the help.
> 
> <snip>

Edward,

I think that most of your intentions, arrays and shadow signals worked 
OK. 
You have to specifically name  the output signals in the function 
declaration:
  def jp_process(sig_in_x_i, left_s_i, sam_s_i, right_s_i,flgs_s_i, 
*res_out_x*, W0=3, LVL0=4, W1=3, LVL1=4, W2=3, LVL2=4,  W3=3, LVL3=4 ):

and declare *res_out_x* before calling the function. I did remove the 
unused input signal *res_out_x_i*.

Now you are 'slicing' 1D input vectors into 1D*1D vectors (which works 
fine, it seems). So if the res_out_x is also a 1D vector, you still have 
to declare an internal 1D*1D signal and concatenate this one to a 1D 
output vector. Something like:
lres_out_x = [Signal(intbv()[xx:]) for _ in range(Y)]

and later add an always_comb function to assemble the output vector
@always_comb
def assignouts():
    for i in range(Y):
        res_out_x.next[ (i+1)*xx:i*xx] = lres_out_x[i]


It would be nice if we can extend MyHDL to do these mappings/assignments 
with less typing. 

Re-using the *res_out_x_i* as an output would be a possibility, but will 
the become an 'inout' signals, which is a very bad idea (except for the 
truly bidirectional top-level pins of the FPGA)

Regards,

JOsy
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Re: [myhdl-list] Is it time for 0.9 release?

[Christopher F. <chr...@gm...>]

On 2/9/2015 6:29 AM, Angel Ezquerra wrote:
<snip>
>>
>> The Move
>> --------
>> There also has been talk about moving to git/github.  I
>> assume this will happen after the 0.9 release, correct?
>
> Has the move to git/github been decided?

There is definite momentum in that direction, I believe
it is inevitable.

> It may be a good move in order to get more exposure for the
> project.

I don't believe that is the current rationale.

> However, having used git
> and github recently for some open source contributions I find that the
> experience is terrible compared to using mercurial (and BitBucket). I
> don't get why people like github so much (other than because it is
> very popular).

Unfortunately, these conversations are muddle because two
things are simultaneously discussed: the version control
tool and the web platform.

I am unaware of the technical arguments at this point, but
if the main developers have a strong preference for git
it is hard to argue against it.  As a community we want to
make development as easy as possible.  From my perspective,
this means: first, supporting the main developers; second,
outlining the process for new developers (both of these
occur in MyHDL).

If the pro-hg'ers were the highest contributors then there
might be precedence for discussion but that is not the
current situation.

 > I find that the BitBucket UI is not as flashy as
 > github's but is IMHO easier to use and mercurial is oh so much simpler
 > than git!

I agree and I am dreading having to invest the time to
figure out some of the more cryptic commands.

But since so many projects use git, this investment is not
a waste.  Hopefully I can avoid past major faux pas with
git :)  The biggest discomfort for me is not being able
to clone to a dropbox folder (or at least not easily).

In addition, one of arguments is the use of CI.  Since MyHDL
has good collection of tests and follows a test-driven mantra,
having an integrated CI is nice.  I know drone.io exists for
bitbucket but someone would need to show a working CI on
bitbucket the same as some have done for travis-ci.

In the end, as often stated, one of the best ways to support
MyHDL is to develop projects with it.  Each developer can
always choose which platform to host the project.

I am sure there will be more on this topic in the future.

Regards,
Chris

Re: [myhdl-list] Is it time for 0.9 release?

[Henry G. <he...@ca...>]

On 09/02/15 12:29, Angel Ezquerra wrote:
> I find that the BitBucket UI is not as flashy as
> github's but is IMHO easier to use and mercurial is oh so much simpler
> than git!

I find precisely the opposite. Perhaps it's to do with what tools one is 
used to.

Henry

Re: [myhdl-list] Is it time for 0.9 release?

[Angel E. <ang...@gm...>]

On Mon, Feb 9, 2015 at 1:16 PM, Christopher Felton
<chr...@gm...> wrote:
>>> I think 0.9 could be released, thoughts?
>
> There has been some intermingled chatter in other
> threads on different topics and issues.  Below is
> a subset summary per the relevant topics.
>
>
> 0.9 Release
> -----------
> It sounds like there are no blockades for a 0.9
> release and we are moving forward with a 0.9 release.
> Things that need to been completed:
>
>     1. PR from @jck to resolve the failing interface
>        tests.
>     2. Documentation for interfaces.
>     3. Normal release stuff.
>
>
> The Move
> --------
> There also has been talk about moving to git/github.  I
> assume this will happen after the 0.9 release, correct?

Has the move to git/github been decided? It may be a good move in
order to get more exposure for the project. However, having used git
and github recently for some open source contributions I find that the
experience is terrible compared to using mercurial (and BitBucket). I
don't get why people like github so much (other than because it is
very popular). I find that the BitBucket UI is not as flashy as
github's but is IMHO easier to use and mercurial is oh so much simpler
than git!

Angel

Re: [myhdl-list] Is it time for 0.9 release?

[Christopher F. <chr...@gm...>]

>> I think 0.9 could be released, thoughts?

There has been some intermingled chatter in other
threads on different topics and issues.  Below is
a subset summary per the relevant topics.


0.9 Release
-----------
It sounds like there are no blockades for a 0.9
release and we are moving forward with a 0.9 release.
Things that need to been completed:

    1. PR from @jck to resolve the failing interface
       tests.
    2. Documentation for interfaces.
    3. Normal release stuff.


The Move
--------
There also has been talk about moving to git/github.  I
assume this will happen after the 0.9 release, correct?


Regards,
Chris

Re: [myhdl-list] delays in VHDL conversion

[Henry G. <he...@ca...>]

On 09/02/15 08:38, Josy Boelen wrote:
<snip>
> I'm not aware if
> there is a cast to convert something (int or real) into a time-type. Of
> course we could write the function(s) to do this and add these to the
> MyHDL package and modify the MyHDL code:
>   elif f is delay:
>              self.write( "to_VHDLtime( ")
>              self.visit(node.args[0])  # this will end up in visit_Num()
> and produce an integer or a real (I suppose)
>              self.write(" )")
>              return

That's quite a neat method. It has the advantage of being explicit and 
clear in the resultant VHDL.

Are the constants new in 0.9? Presumably there should be a test for this...

Henry

Re: [myhdl-list] delays in VHDL conversion

[Josy B. <jos...@gm...>]

Henry Gomersall <heng <at> cantab.net> writes:

> 
> On 08/02/15 22:22, Josy Boelen wrote:
> <snip>
> > Actually the converted code is wrong, the statements like:
> >      constant lowTime: integer := 10;
> >      wait for lowTime ns;
> >
> > are incorrect, they should either be:
> >      constant lowTime: integer := 10;
> >      wait for lowTime * 1.0 ns;
> >
> > or:
> >      constant lowTime: time := 10.0 ns;
> >      wait for lowTime ;
> >
> > Should be easy to fix in the MyHDL code.
> 
> You mean in the conversion routines? The easiest way I can think of is 
> to replace the "ns" string with "* 1.0 ns"
> here:
> 
https://bitbucket.org/jandecaluwe/myhdl/src/b07b52398020b3bd737d0b4f1574
f0d94eefccb5/myhdl/conversion/_toVHDL.py?at=default#cl-970
> 
> No doubt that will break other things though? Is there a reason why 
> there can't always be a multiplier (other than code neatness)?
> <snip>

I meant exactly that, and the '* 1.0 ns' would be my preferred too, and 
is definitely the easiest. I don't think this will break any other code.

Specifically setting the 'times' using real numbers, e.g.:
  def ClkDriver(clk, period=20.0):

     lowTime = period / 2
     highTime = period - lowTime
     ...
     wait for lowTime ns;

will not help either, as VHDL expects a time-type value and the 'ns' is 
part of that and can not be used as a units specifier. I'm not aware if 
there is a cast to convert something (int or real) into a time-type. Of 
course we could write the function(s) to do this and add these to the 
MyHDL package and modify the MyHDL code:
 elif f is delay:
            self.write( "to_VHDLtime( ")
            self.visit(node.args[0])  # this will end up in visit_Num() 
and produce an integer or a real (I suppose)
            self.write(" )")
            return

Regards,

Josy

Re: [myhdl-list] delays in VHDL conversion

[Henry G. <he...@ca...>]

On 08/02/15 22:22, Josy Boelen wrote:
<snip>
> Actually the converted code is wrong, the statements like:
>      constant lowTime: integer := 10;
>      wait for lowTime ns;
>
> are incorrect, they should either be:
>      constant lowTime: integer := 10;
>      wait for lowTime * 1.0 ns;
>
> or:
>      constant lowTime: time := 10.0 ns;
>      wait for lowTime ;
>
> Should be easy to fix in the MyHDL code.

You mean in the conversion routines? The easiest way I can think of is 
to replace the "ns" string with "* 1.0 ns"
here:
https://bitbucket.org/jandecaluwe/myhdl/src/b07b52398020b3bd737d0b4f1574f0d94eefccb5/myhdl/conversion/_toVHDL.py?at=default#cl-970

No doubt that will break other things though? Is there a reason why 
there can't always be a multiplier (other than code neatness)?

Henry

Re: [myhdl-list] delays in VHDL conversion

[Josy B. <jos...@gm...>]

Henry Gomersall <heng <at> cantab.net> writes:

> 
> I'm trying to do a poor man's RTL co-simulation by creating the files 
> needed for simulation and the relevant stimulus files (from the MyHDL 
> simulation), then writing the outputs from the Xilinx simulation to 
file 
> for post-simulation comparison. For this I need a clock.
> 
> Consider:
> 
> def ClkDriver(clk, period=20):
> 
>      lowTime = int(period/2)
>      highTime = period - lowTime
> 
>       <at> instance
>      def driveClk():
>          while True:
>              yield delay(lowTime)
>              clk.next = 1
>              yield delay(highTime)
>              clk.next = 0
> 
>      return driveClk
> 
> This is converted to the following (pertinent) VHDL:
> 
> architecture MyHDL of ClkDriver is
> 
> constant lowTime: integer := 10;
> constant highTime: integer := 10;
> 
> begin
> 
> CLKDRIVER_DRIVECLK: process is
> begin
>      while True loop
>          wait for lowTime ns;
>          clk <= '1';
>          wait for highTime ns;
>          clk <= '0';
>      end loop;
>      wait;
> end process CLKDRIVER_DRIVECLK;
> 
> end architecture MyHDL;
> 
> Xilinx Vivado complains this is a syntax error. It doesn't like the 
use 
> of a constant in the "wait for lowTime ns", though it's easily fixed 
> with e.g. "wait for 10 ns".
> 
> Is this Vivado being crap, or is this expected behaviour? I could 
always 
> create my own custom VHDL template, but it would be neater to have 
MyHDL 
> do it for me.
> 
> <snip>

Actually the converted code is wrong, the statements like:
    constant lowTime: integer := 10;
    wait for lowTime ns;

are incorrect, they should either be:
    constant lowTime: integer := 10;
    wait for lowTime * 1.0 ns;

or:
    constant lowTime: time := 10.0 ns;
    wait for lowTime ;

Should be easy to fix in the MyHDL code.

Regards,

Josy
 

Re: [myhdl-list] All inputs no output with generated Verilog and VHDL

[Josy B. <jos...@gm...>]

Edward Vidal <develone <at> sbcglobal.net> writes:

> 
> 
> Hello Josy,
> 
> I thought that items on left were outputs and items on the right were 
inputs.  I was trying to follow an example  posted  Raman Muthukishnan.
> 
> I just wanted signals that  were arrays.   Since these are, I assuming 
shadow signals that is why I am not getting any output.  This is a new 
topic for me and I have not worked with shadow signals before.  What 
must I do to get the res_out_x or res_out_x_i to be and output?   This 
must be a really bad question.  I do appreciate all the help.
> 
> <snip>

Edward,

I think that most of your intentions, arrays and shadow signals worked 
OK. 
You have to specifically name  the output signals in the function 
declaration:
  def jp_process(sig_in_x_i, left_s_i, sam_s_i, right_s_i,flgs_s_i, 
*res_out_x*, W0=3, LVL0=4, W1=3, LVL1=4, W2=3, LVL2=4,  W3=3, LVL3=4 ):

and declare *res_out_x* before calling the function. I did remove the 
unused input signal *res_out_x_i*.

Now you are 'slicing' 1D input vectors into 1D*1D vectors (which works 
fine, it seems). So if the res_out_x is also a 1D vector, you still have 
to declare an internal 1D*1D signal and concatenate this one to a 1D 
output vector. Something like:
 lres_out_x = [Signal(intbv()[xx:]) for _ in range(Y)]

and later add an always_comb function to assemble the output vector
@always_comb
def assignouts():
    for i in range(Y):
        res_out_x.next[ (i+1)*xx:i*xx] = lres_out_x[i]


It would be nice if we can extend MyHDL to do these mappings/assignments 
with less typing. 

Re-using the *res_out_x_i* as an output would be a possibility, but will 
the become an 'inout' signals, which is a very bad idea (except for the 
truly bidirectional top-level pins of the FPGA)

Regards,

JOsy

[myhdl-list] delays in VHDL conversion

[Henry G. <he...@ca...>]

I'm trying to do a poor man's RTL co-simulation by creating the files 
needed for simulation and the relevant stimulus files (from the MyHDL 
simulation), then writing the outputs from the Xilinx simulation to file 
for post-simulation comparison. For this I need a clock.

Consider:

def ClkDriver(clk, period=20):

     lowTime = int(period/2)
     highTime = period - lowTime

     @instance
     def driveClk():
         while True:
             yield delay(lowTime)
             clk.next = 1
             yield delay(highTime)
             clk.next = 0

     return driveClk

This is converted to the following (pertinent) VHDL:

architecture MyHDL of ClkDriver is

constant lowTime: integer := 10;
constant highTime: integer := 10;

begin

CLKDRIVER_DRIVECLK: process is
begin
     while True loop
         wait for lowTime ns;
         clk <= '1';
         wait for highTime ns;
         clk <= '0';
     end loop;
     wait;
end process CLKDRIVER_DRIVECLK;

end architecture MyHDL;

Xilinx Vivado complains this is a syntax error. It doesn't like the use 
of a constant in the "wait for lowTime ns", though it's easily fixed 
with e.g. "wait for 10 ns".

Is this Vivado being crap, or is this expected behaviour? I could always 
create my own custom VHDL template, but it would be neater to have MyHDL 
do it for me.

Many thanks,

Henry