myhdl-list — Mailing list for discussions on MyHDL

[myhdl-list] upgrading from 0.4

[George P. <ge...@ga...>]

Hi all,

    To upgrade, can I just install myHDL 0.5 over my current 
installation of 0.4? (I'm using 0.4 on cygwin)

Thanks,
George

Re: [myhdl-list] Re: MyHDL website not accessible in China

[nicran <ni...@gm...>]

I guess the best solution in the current stage is using proxy to view
this website in China :(

2005/10/22, Jan Decaluwe <ja...@ja...>:
> Jan Decaluwe wrote:
> > G=FCnter Dannoritzer wrote:
>
> >> http://hrw.org/english/docs/2005/09/28/china11798.htm
> >>
> >> Maybe asked your Yahoo contact person for the page about that issue.
> >
> >
> > Mm, that could take a long time :-) But also here I can't imagine that
> > this would be at yahoo's side. I read a report on the internet about
> > someone with a similar issue. The block was at the Chinese side, and
> > yahoo reported that "they couldn't do anything about it". I guess
> > we would get the same answer.
>
> Mm, I shouldn't judge too soon. In fact it was easy to get quite
> a reasonable (and judging from the language errors, apparently
> dedicated :-)) answer from Yahoo. I am including their response here
> in full.
>
> I have already written an e-mail to the organization they indicated.
> We'll see.
>
> The Yahoo response:
>
> > Hello Jan,
> >
> > Thank you for writing to Yahoo! Web Hosting. I hope this email answers
> > your question.
> >
> > Based on your email, I understand your concerns regarding your website
> > not viewable in China.
> >
> > We have tested and found that your domain is resolving. Unfortunately,
> > we have discovered that the Chinese government has a sophisticated
> > firewall set up and it will not be possible to view certain websites
> > while in this country.
> >
> > Your site is in fact blocked in China, but not because it contains any
> > "banned" content, rather, its a collateral block. Your site is hosted o=
n
> > a Yahoo! server along with hundreds, perhaps thousands, of other domain=
s
> > which are viewable in other countries.
> >
> > This move is China's efforts to police the Internet and follow stringen=
t
> > efforts. Some features, can't be accessed from China's controlled
> > internet without using proxy software.
> >
> > Thus, I would recommend you to contact the Government-Connected
> > "Internet Society of China" and concerned ISP's for further assistance,
> > to get your website registered.
> >
> >    www.isc.org.cn/English/
> >
> > Please do not hesitate to reply if you need further assistance.
> >
> > Regards,
> >
> > Edith
> >
> > Yahoo! Customer Care
> >
> > For assistance with all Yahoo! services please visit:
> >
> >    http://help.yahoo.com/
> >
> >
> >
> > Original Message Follows:
> > -------------------------
> >
> > Yahoo! ID: jandecaluwe
> > First Name: Jan
> > Last Name: Decaluwe
> > Email Address: ja...@ja...
> > Comments: I have learned that my web site is not accessible in China.
> >
> > Why is this so? Can you do something about that?
> > Subject: General troubleshooting[ Attachment 1.2      Type: text/html]
> > [ Attachment 1.3      Type: text/xml]
>
>
> --
> Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
> Losbergenlaan 16, B-3010 Leuven, Belgium
>     Electronic design with Python:
>     http://myhdl.jandecaluwe.com
>
>
>
> -------------------------------------------------------
> This SF.Net email is sponsored by:
> Power Architecture Resource Center: Free content, downloads, discussions,
> and more. http://solutions.newsforge.com/ibmarch.tmpl
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>

[myhdl-list] Re: MyHDL website not accessible in China

[Jan D. <ja...@ja...>]

Jan Decaluwe wrote:
> Günter Dannoritzer wrote:

>> http://hrw.org/english/docs/2005/09/28/china11798.htm
>>
>> Maybe asked your Yahoo contact person for the page about that issue.
> 
> 
> Mm, that could take a long time :-) But also here I can't imagine that
> this would be at yahoo's side. I read a report on the internet about
> someone with a similar issue. The block was at the Chinese side, and
> yahoo reported that "they couldn't do anything about it". I guess
> we would get the same answer.

Mm, I shouldn't judge too soon. In fact it was easy to get quite
a reasonable (and judging from the language errors, apparently
dedicated :-)) answer from Yahoo. I am including their response here
in full.

I have already written an e-mail to the organization they indicated.
We'll see.

The Yahoo response:

> Hello Jan,
> 
> Thank you for writing to Yahoo! Web Hosting. I hope this email answers 
> your question. 
> 
> Based on your email, I understand your concerns regarding your website 
> not viewable in China. 
> 
> We have tested and found that your domain is resolving. Unfortunately, 
> we have discovered that the Chinese government has a sophisticated 
> firewall set up and it will not be possible to view certain websites 
> while in this country. 
> 
> Your site is in fact blocked in China, but not because it contains any 
> "banned" content, rather, its a collateral block. Your site is hosted on
> a Yahoo! server along with hundreds, perhaps thousands, of other domains
> which are viewable in other countries.
> 
> This move is China's efforts to police the Internet and follow stringent
> efforts. Some features, can't be accessed from China's controlled 
> internet without using proxy software. 
> 
> Thus, I would recommend you to contact the Government-Connected 
> "Internet Society of China" and concerned ISP's for further assistance, 
> to get your website registered. 
> 
>    www.isc.org.cn/English/ 
> 
> Please do not hesitate to reply if you need further assistance.
> 
> Regards,
> 
> Edith
> 
> Yahoo! Customer Care
> 
> For assistance with all Yahoo! services please visit:
>    
>    http://help.yahoo.com/
> 
> 
> 
> Original Message Follows:
> -------------------------
> 
> Yahoo! ID: jandecaluwe
> First Name: Jan
> Last Name: Decaluwe
> Email Address: ja...@ja...
> Comments: I have learned that my web site is not accessible in China.
> 
> Why is this so? Can you do something about that?
> Subject: General troubleshooting[ Attachment 1.2	Type: text/html]
> [ Attachment 1.3	Type: text/xml]


-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
     Electronic design with Python:
     http://myhdl.jandecaluwe.com

Re: [myhdl-list] Feedback request on decorators in MyHDL

[Haitao Z. <ha...@gm...>]

Jan,

I remeber reading an interesting thread on decorators in
comp.lang.python. Some consider the decorator feature a hack on the
polymorphic function, because it can not replace true polymorphism
which is hard. So there is question whether this feature should stay
with future Pythons. A main issue is that there were no truely good
examples of usage pattern (polymorphic dispatch usage does not
simplify the user interface since python function already supports
arbitrary argument types) and often the dispatch through decorator is
more confusing than explicit control statements. However I think your
usage pattern in myhdl holds as a true example of how it can be used
to the advantage on the user side. I don't think decorator will go
away and this myhdl usage pattern strongly supports keeping
decorators. It will be nice to make it more well known to the Python
community.

Very nice and pythonic discovery indeed.

Haitao

On 10/21/05, Jan Decaluwe <ja...@ja...> wrote:
> Hi all:
>
> The past 2 weeks have been intensive and fun, as I have
> worked on an exciting new feature for 0.5: decorators.
>
> I am about to introduce this in MyHDL, and it has the
> potential of being quite significant (but backwards-compatible,
> don't worry) - for the better.
>
> I want to avoid making mistakes in all the excitement, so
> here is your chance to provide feedback. I have written a
> MyHDL Enhancement Proposal (MEP) that documents the feature:
>
>      http://myhdl.jandecaluwe.com/doku.php/meps:mep-100
>
> For those interested, a first implementation is available
> in snapshot 0.5dev2, available on the web site.
>
> I will now turn my attention to other MyHDL issues until
> the beginning of November, so you busy people have some time
> before I make the final decision to go ahead.
> All kind of feedback is welcome, but especially if there
> is something that you don't like.
>
> Regards,
>
> Jan
>
> --
> Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
> Losbergenlaan 16, B-3010 Leuven, Belgium
>      Electronic design with Python:
>      http://myhdl.jandecaluwe.com
>
>
>
> -------------------------------------------------------
> This SF.Net email is sponsored by:
> Power Architecture Resource Center: Free content, downloads, discussions,
> and more. http://solutions.newsforge.com/ibmarch.tmpl
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>

Re: [myhdl-list] Feedback request on decorators in MyHDL

[bedros <be...@ya...>]

great work Jan, I've not touched Myhdl in over a year,
and I'm very impressed with how you use decorators in
MyHDL. it makes Myhdl very similar to a real RTL.

ease of use is very important to attract developers,
and it seems you're going in the right direction.

what's holding me back from using it is the fact that
I  can't integrate it with VHDL code. What's the
status of VHPI interface?


Any updates on simulators for myhdl?

Regards,

-Bedros
--- Jan Decaluwe <ja...@ja...> wrote:

> Hi all:
> 
> The past 2 weeks have been intensive and fun, as I
> have
> worked on an exciting new feature for 0.5:
> decorators.
> 
> I am about to introduce this in MyHDL, and it has
> the
> potential of being quite significant (but
> backwards-compatible,
> don't worry) - for the better.
> 
> I want to avoid making mistakes in all the
> excitement, so
> here is your chance to provide feedback. I have
> written a
> MyHDL Enhancement Proposal (MEP) that documents the
> feature:
> 
>     
> http://myhdl.jandecaluwe.com/doku.php/meps:mep-100
> 
> For those interested, a first implementation is
> available
> in snapshot 0.5dev2, available on the web site.
> 
> I will now turn my attention to other MyHDL issues
> until
> the beginning of November, so you busy people have
> some time
> before I make the final decision to go ahead.
> All kind of feedback is welcome, but especially if
> there
> is something that you don't like.
> 
> Regards,
> 
> Jan
> 
> -- 
> Jan Decaluwe - Resources bvba -
> http://www.jandecaluwe.com
> Losbergenlaan 16, B-3010 Leuven, Belgium
>      Electronic design with Python:
>      http://myhdl.jandecaluwe.com
> 
> 
> 
>
-------------------------------------------------------
> This SF.Net email is sponsored by:
> Power Architecture Resource Center: Free content,
> downloads, discussions,
> and more.
> http://solutions.newsforge.com/ibmarch.tmpl
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
>
https://lists.sourceforge.net/lists/listinfo/myhdl-list
> 

[myhdl-list] Feedback request on decorators in MyHDL

[Jan D. <ja...@ja...>]

Hi all:

The past 2 weeks have been intensive and fun, as I have
worked on an exciting new feature for 0.5: decorators.

I am about to introduce this in MyHDL, and it has the
potential of being quite significant (but backwards-compatible,
don't worry) - for the better.

I want to avoid making mistakes in all the excitement, so
here is your chance to provide feedback. I have written a
MyHDL Enhancement Proposal (MEP) that documents the feature:

     http://myhdl.jandecaluwe.com/doku.php/meps:mep-100

For those interested, a first implementation is available
in snapshot 0.5dev2, available on the web site.

I will now turn my attention to other MyHDL issues until
the beginning of November, so you busy people have some time
before I make the final decision to go ahead.
All kind of feedback is welcome, but especially if there
is something that you don't like.

Regards,

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
     Electronic design with Python:
     http://myhdl.jandecaluwe.com

[myhdl-list] Re: MyHDL website not accessible in China

[Jan D. <ja...@ja...>]

Günter Dannoritzer wrote:
> Jan,
> 
> Jan Decaluwe wrote:
> 
>>
>> idea why mine are blocked (yahoo is a big name and I pay for
>> the service.)
> 
> 
> Recently it went through the press that Yahoo is supporting the 
> censorship done by the Chinese government to the Internet. I wonder 
> whether it is actually Yahoo that is not allowing the page being 
> accessed from within China?

In that case I would expect that the web sites would not turn up
in a search on the chinese yahoo search engine. (cn.yahoo.com).
But they do. This in contrast to baidu.com ...

I can't imagine it has anything to do with MyHDL. (Although one
should never underestimate the Verilog lobby :-)). I assume we
are the victim of some general brute-force rule.

> For an article about censorship in China see the following link:
> 
> http://hrw.org/english/docs/2005/09/28/china11798.htm
> 
> Maybe asked your Yahoo contact person for the page about that issue.

Mm, that could take a long time :-) But also here I can't imagine that
this would be at yahoo's side. I read a report on the internet about
someone with a similar issue. The block was at the Chinese side, and
yahoo reported that "they couldn't do anything about it". I guess
we would get the same answer.

> It would be interesting to know whether the page was accessible before 
> you changed it to be an wiki? I wonder whether someone is afraid that 
> user from within China would use it to post critical content?

As nicran said, my web site could not be accessed even before the
new wik-based MyHDL subdomain was launched. So it seems a more
general and earlier problem.

In the mean time, I double-checked with another Chinese MyHDL user. He
confirmed that the web site is not accessible.

Regards, Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
     Electronic design with Python:
     http://myhdl.jandecaluwe.com

Re: [myhdl-list] Re: MyHDL website not accessible in China

[nicran <ni...@gm...>]

I can't access this page before Jan add the wiki application.

2005/10/20, G=FCnter Dannoritzer <dan...@we...>:
> Jan,
>
> Jan Decaluwe wrote:
> >
> > idea why mine are blocked (yahoo is a big name and I pay for
> > the service.)
>
> Recently it went through the press that Yahoo is supporting the
> censorship done by the Chinese government to the Internet. I wonder
> whether it is actually Yahoo that is not allowing the page being
> accessed from within China?
>
> For an article about censorship in China see the following link:
>
> http://hrw.org/english/docs/2005/09/28/china11798.htm
>
> Maybe asked your Yahoo contact person for the page about that issue.
>
> It would be interesting to know whether the page was accessible before
> you changed it to be an wiki? I wonder whether someone is afraid that
> user from within China would use it to post critical content?
>
> Cheers,
>
> Guenter
>
>
>
> -------------------------------------------------------
> This SF.Net email is sponsored by:
> Power Architecture Resource Center: Free content, downloads, discussions,
> and more. http://solutions.newsforge.com/ibmarch.tmpl
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>

Re: [myhdl-list] Re: MyHDL website not accessible in China

[<dan...@we...>]

Jan,

Jan Decaluwe wrote:
> 
> idea why mine are blocked (yahoo is a big name and I pay for
> the service.)

Recently it went through the press that Yahoo is supporting the 
censorship done by the Chinese government to the Internet. I wonder 
whether it is actually Yahoo that is not allowing the page being 
accessed from within China?

For an article about censorship in China see the following link:

http://hrw.org/english/docs/2005/09/28/china11798.htm

Maybe asked your Yahoo contact person for the page about that issue.

It would be interesting to know whether the page was accessible before 
you changed it to be an wiki? I wonder whether someone is afraid that 
user from within China would use it to post critical content?

Cheers,

Guenter

Re: [myhdl-list] Re: MyHDL website not accessible in China

[Tom D. <td...@di...>]

Jan,

We do get inquiries from China through our web site, but I can't be sure
it won't be blocked in the future.

At least if you did get blocked you wouldn't be paying for the service.

Tom


Jan Decaluwe wrote:

> Tom Dillon wrote:
>
>> Jan,
>>
>> I don't know anything about that but as I have been looking for ways 
>> to contribute to MyHDL, we would be willing to host it on our 
>> servers. How about www.myhdl.org?
>>
>> Let me know, I will reserve the name and get it ready if you are 
>> interested.
>
>
> Thanks for the offer. But - can we be sure that your
> servers are unlikely to be blocked? I've in fact no
> idea why mine are blocked (yahoo is a big name and I pay for
> the service.)
>
> Regards, Jan
>

Re: [myhdl-list] Re: MyHDL website not accessible in China

[Tom D. <td...@di...>]

Jan,

We do get inquiries from China through our web site, but I can't be sure 
it won't be blocked in the future.

At least if you did get blocked you wouldn't be paying for the service. :-)

Tom


Jan Decaluwe wrote:

> Tom Dillon wrote:
>
>> Jan,
>>
>> I don't know anything about that but as I have been looking for ways 
>> to contribute to MyHDL, we would be willing to host it on our 
>> servers. How about www.myhdl.org?
>>
>> Let me know, I will reserve the name and get it ready if you are 
>> interested.
>
>
> Thanks for the offer. But - can we be sure that your
> servers are unlikely to be blocked? I've in fact no
> idea why mine are blocked (yahoo is a big name and I pay for
> the service.)
>
> Regards, Jan
>

[myhdl-list] Re: MyHDL website not accessible in China

[Jan D. <ja...@ja...>]

Tom Dillon wrote:
> Jan,
> 
> I don't know anything about that but as I have been looking for ways to 
> contribute to MyHDL, we would be willing to host it on our servers. How 
> about www.myhdl.org?
> 
> Let me know, I will reserve the name and get it ready if you are 
> interested.

Thanks for the offer. But - can we be sure that your
servers are unlikely to be blocked? I've in fact no
idea why mine are blocked (yahoo is a big name and I pay for
the service.)

Regards, Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
     Electronic design with Python:
     http://myhdl.jandecaluwe.com

Re: [myhdl-list] MyHDL website not accessible in China

[Tom D. <td...@di...>]

Jan,

I don't know anything about that but as I have been looking for ways to 
contribute to MyHDL, we would be willing to host it on our servers. How 
about www.myhdl.org?

Let me know, I will reserve the name and get it ready if you are interested.

Tom




Jan Decaluwe wrote:

> Hi all:
>
> I have just learned that for some reason my website and
> the MyHDL website are not accessible in China.
>
> This kind of situation is new to me. Is there anyone
> with experience and/or suggestions on what could be done?
>
> My website is hosted on yahoo under a paid subscription plan.
>
> Regards,
>
> Jan
>

[myhdl-list] MyHDL website not accessible in China

[Jan D. <ja...@ja...>]

Hi all:

I have just learned that for some reason my website and
the MyHDL website are not accessible in China.

This kind of situation is new to me. Is there anyone
with experience and/or suggestions on what could be done?

My website is hosted on yahoo under a paid subscription plan.

Regards,

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
     Electronic design with Python:
     http://myhdl.jandecaluwe.com

[myhdl-list] Re: Xilinx ISE error: unexpected token: '='

[Jan D. <ja...@ja...>]

George Pantazopoulos wrote:

>> Good to hear! At some point, please consider adding some info about
>> your project at the MyHDL web site (or ask me to do it.)
> 
> 
> Will do, as soon as it takes a little more form :) You've done a great 
> thing by developing myHDL. Do you have any help with it?

The best kind of help I'm getting is feedback from users - both academic
and instustrial - doing real projects with MyHDL.

For example, a significant number of new features, and my trigger to
work on 0.5, comes from user feedback.

I hope to increase the number of users in the future. MyHDL 0.5 will
(for the first time) be announced in comp.lang.fpga, I think the time
is ripe for it. I also hope users will start contributing to the
MyHDL web site, e.g. by describing details about their projects
and MyHDL usage on the web site. The infrastructure is ready for that -
it's just a matter of registering to add/modify info.

Regards,

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
     Electronic design with Python:
     http://myhdl.jandecaluwe.com

[myhdl-list] Re: Xilinx ISE error: unexpected token: '='

[George P. <ge...@ga...>]

> 
> It's a mismatch between MyHDL and the point where I hoped that
> mainstream Verilog tools would be by now :-) Initial value assignments
> were introduced in Verilog 2001 but several tools don't seem to support
> them. I included them to try to avoid simulation mismatches at
> startup time with the MyHDL model.
> 
> However, it seems clear that I will have to take them out. It's probably
> not such a big deal provided initialiation is done properly by other
> means. I have done so in my current development toward 0.5.
> 
> You have 2 options: the first is to just go into the code (I assume
> you use 0.4.1) of toVerilog/_convert.py, and take out the initial value 
> assignments in function _writeSigDecls and method writeDeclaration.
> 
> Or, you can use the 0.5 development snapshot from
> 
>    http://myhdl.jandecaluwe.com/doku.php/snapshots
>

> The advantage here is that there are some new features that may
> especially be interesting for people doing FPGAs, such as support for
> RAM and ROM inferencing.

Thanks for the tip, and this RAM and ROM inferencing looks like it will 
be very handy! I will be checking out 0.5dev1 shortly.

>> FWIW, I'm a newbie both to python and myHDL, but with myHDL I have 
>> been able to get further in my project than I dreamed possible (I'm 
>> making a digital music synthesizer, and within two days I was up and 
>> running and playing with sounds coming out of my FPGA board!) I tired 
>> verilog, vhdl, and even confluence,  but myHDL is, for me, by far the 
>> best way to go!
> 
> 
> Good to hear! At some point, please consider adding some info about
> your project at the MyHDL web site (or ask me to do it.)

Will do, as soon as it takes a little more form :) You've done a great 
thing by developing myHDL. Do you have any help with it?

George

[myhdl-list] Re: Xilinx ISE error: unexpected token: '='

[Jan D. <ja...@ja...>]

George Pantazopoulos wrote:
> 
> 
> Hi all,
>    When I use a 'for' loop in one of my components, it produces verilog 
> code that doesn't compile as-is.
> Specifically, it produces in verilog "integer i = 0;", which causes an 
> error in Xilinx ISE (7.1.04i):
> 
> Xilinx ISE error
> -----------------
> Compiling verilog file "../../SYNTH_0.v"
> ERROR:HDLCompilers:26 - "../../SYNTH_0.v" line 41 unexpected token: '='
> 
> I can get it to compile and the circuit works fine if I manually edit 
> "integer i = 0;" to "integer i;". However, this is quite inconvenient. 
> Is the problem something I am doing? In myHDL? In Xilinx ISE? See below 
> for my myHDL code and the corresponding verilog output.

It's a mismatch between MyHDL and the point where I hoped that
mainstream Verilog tools would be by now :-) Initial value assignments
were introduced in Verilog 2001 but several tools don't seem to support
them. I included them to try to avoid simulation mismatches at
startup time with the MyHDL model.

However, it seems clear that I will have to take them out. It's probably
not such a big deal provided initialiation is done properly by other
means. I have done so in my current development toward 0.5.

You have 2 options: the first is to just go into the code (I assume
you use 0.4.1) of toVerilog/_convert.py, and take out the initial value 
assignments in function _writeSigDecls and method writeDeclaration.

Or, you can use the 0.5 development snapshot from

    http://myhdl.jandecaluwe.com/doku.php/snapshots

The advantage here is that there are some new features that may
especially be interesting for people doing FPGAs, such as support for
RAM and ROM inferencing.

> FWIW, I'm a newbie both to python and myHDL, but with myHDL I have been 
> able to get further in my project than I dreamed possible (I'm making a 
> digital music synthesizer, and within two days I was up and running and 
> playing with sounds coming out of my FPGA board!) I tired verilog, vhdl, 
> and even confluence,  but myHDL is, for me, by far the best way to go!

Good to hear! At some point, please consider adding some info about
your project at the MyHDL web site (or ask me to do it.)

Regards,

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
     Electronic design with Python:
     http://myhdl.jandecaluwe.com

[myhdl-list] New MyHDL site

[Jan D. <ja...@ja...>]

Hello all:

The new MyHDL site is operational:

    http://myhdl.jandecaluwe.com

It uses a wiki tool called dokuwiki as a content management
tool. This has been done for several reasons:
* it will be much easier for me to quickly add and modify content
* anyone who wishes can now contribute (after registering)

This has taken somewhat longer than I hoped, because wiki technology
is relatively new. So I got involved to make it do what I wanted,
in particular with respect to navigation. For more info
about this work, see:

    http://www.jandecaluwe.com/testwiki

With the new site, I intend to accelerate the release cycle
as well, by opening a page with development snapshots. To
whet your appetite, the first development snapshot towards
release 0.5 is already available. I will also use the site
to develop the documentation, which should increase visibility
into the development process.

Best regards,

Jan

--
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
     Electronic design with Python:
     http://myhdl.jandecaluwe.com

[myhdl-list] Xilinx ISE error: unexpected token: '='

[George P. <ge...@ga...>]

Hi all,
    When I use a 'for' loop in one of my components, it produces verilog 
code that doesn't compile as-is.
Specifically, it produces in verilog "integer i = 0;", which causes an 
error in Xilinx ISE (7.1.04i):

Xilinx ISE error
-----------------
Compiling verilog file "../../SYNTH_0.v"
ERROR:HDLCompilers:26 - "../../SYNTH_0.v" line 41 unexpected token: '='

I can get it to compile and the circuit works fine if I manually edit 
"integer i = 0;" to "integer i;". However, this is quite inconvenient. 
Is the problem something I am doing? In myHDL? In Xilinx ISE? See below 
for my myHDL code and the corresponding verilog output.

FWIW, I'm a newbie both to python and myHDL, but with myHDL I have been 
able to get further in my project than I dreamed possible (I'm making a 
digital music synthesizer, and within two days I was up and running and 
playing with sounds coming out of my FPGA board!) I tired verilog, vhdl, 
and even confluence,  but myHDL is, for me, by far the best way to go!

Thanks!
George
http://www.gammaburst.net

offending myHDL input
------------------------

# Alternately makes all bits in wave_out 0, then 1
def Pulser(clock, reset, enable, count_in, duty_cycle, wave_out):

    OUTPUT_BITS = len(wave_out)
   
    def PulserProcess():
        while 1:
            yield posedge(clock)

            for i in range(OUTPUT_BITS):

                if count_in == 0:
                    wave_out.next[i] = 1
                elif count_in == duty_cycle:
                    wave_out.next[i] = 0
       
    return PulserProcess()


Xilinx ISE output
-----------------

always @(posedge clock) begin: _MYHDL4_BLOCK
    integer i = 0;
    for (i=0; i<12; i=i+1) begin
        if ((_WAVE_0_accum_out == 0)) begin
            wave0_out[i] <= 1;
        end
        else if ((_WAVE_0_accum_out == sweep0_out)) begin
            wave0_out[i] <= 0;
        end
    end
end

Re: [myhdl-list] Re: Some thoughts on toVerilog, toVHDL, etc.

[<dan...@we...>]

Hi Jan,

Jan Decaluwe wrote:
>> Now I was wondering when the 
>> netlist format is the key to that flexibility, whether MyHDL could 
>> take favor of developments already done in that area?
> 
> 
> I don't think so.
> 
> MyHDL directly converts from RTL/behavior to (perhaps somewhat lower
> level) RTL/behavior in the target language.
> 
> If toVerilog converted to netlist, it would be a synthesis tool.
> But that's a much bigger effort, and once in Verilog/VHDL, several
> decent synthesis tools are available. Moreover, despite appearances,
> toVerilog can also be used to convert non-synthesizable code, and that
> can be very useful also.
> 
> Alternatively, if toVerilog restricted the MyHDL input to a netlist-type 
> of format, the restrictions would be so high as to render the whole
> thing not very interesting.
> 

Thanks for you comment. I mixed things up. My idea was to have some HDL 
language independent interface that is documented. Then to build 
conversion tools to Verilog and VHDL starting from there. However, 
toVerilog is already implemented and the question is what such a 
interface would provide over the now used Abstract Syntax Tree way from 
Python.

My mix came in when I thought a netlist would be able to provide a way 
to define such an interface. I better take some time to study the 
Abstract Syntax Tree of Python to understand how to use it.

> Let me add that I fail to see the point of Confluence itself. It's
> one more attempt in a long tradition of non-procedural HDL languages.
> The reasoning is that as hardware is parallel, the HDL should *only*
> have parallel contructs too. In my opinion, this reasoning is flawed.
> The evidence of sucessful HDLs supports my views on this.
> 
> It is easy to claim, as Confluence does, that you need much fewer
> lines of code for a specific type of block, if you include it as a
> primitive in your language. The real point is that there are many
> kinds of useful hardware descriptions, including synthesizable ones,
> that need procedural constructs, and that therefore simply cannot be
> descibed elegantly in a non-procedural language like Confluence.
> 

Very well said!

Cheers,

Guenter

[myhdl-list] Re: Some thoughts on toVerilog, toVHDL, etc.

[Jan D. <ja...@ja...>]

Günter Dannoritzer wrote:
> Hi,
> 
> When browsing for netlists I ran across this page about a free netlist 
> format:
> 
>     http://www.confluent.org/wiki/doku.php?id=fnf:index
> 
> This gave me an idea and I was wondering how feasible this really is? 
> How difficult would it be in MyHDL instead of creating individual 
> toVerilog, toVHDL, etc. modules, to go through a neutral netlist and 
> from there create HDL code?
> 
> I think this netlist format steamed from the confluence language, which 
> I am not really familiar with. However, I read that it is possible to 
> convert confluence in all types of other languages, like Verilog, VHDL, 
> but also programming language like C. This is also pictured in the web 
> link I gave above. Now I was wondering when the netlist format is the 
> key to that flexibility, whether MyHDL could take favor of developments 
> already done in that area?

I don't think so.

MyHDL directly converts from RTL/behavior to (perhaps somewhat lower
level) RTL/behavior in the target language.

If toVerilog converted to netlist, it would be a synthesis tool.
But that's a much bigger effort, and once in Verilog/VHDL, several
decent synthesis tools are available. Moreover, despite appearances,
toVerilog can also be used to convert non-synthesizable code, and that
can be very useful also.

Alternatively, if toVerilog restricted the MyHDL input to a netlist-type 
of format, the restrictions would be so high as to render the whole
thing not very interesting.

Let me add that I fail to see the point of Confluence itself. It's
one more attempt in a long tradition of non-procedural HDL languages.
The reasoning is that as hardware is parallel, the HDL should *only*
have parallel contructs too. In my opinion, this reasoning is flawed.
The evidence of sucessful HDLs supports my views on this.

It is easy to claim, as Confluence does, that you need much fewer
lines of code for a specific type of block, if you include it as a
primitive in your language. The real point is that there are many
kinds of useful hardware descriptions, including synthesizable ones,
that need procedural constructs, and that therefore simply cannot be
descibed elegantly in a non-procedural language like Confluence.

Regards,

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
     Electronic design with Python:
     http://myhdl.jandecaluwe.com

[myhdl-list] Some thoughts on toVerilog, toVHDL, etc.

[<dan...@we...>]

Hi,

When browsing for netlists I ran across this page about a free netlist 
format:

	http://www.confluent.org/wiki/doku.php?id=fnf:index

This gave me an idea and I was wondering how feasible this really is? 
How difficult would it be in MyHDL instead of creating individual 
toVerilog, toVHDL, etc. modules, to go through a neutral netlist and 
from there create HDL code?

I think this netlist format steamed from the confluence language, which 
I am not really familiar with. However, I read that it is possible to 
convert confluence in all types of other languages, like Verilog, VHDL, 
but also programming language like C. This is also pictured in the web 
link I gave above. Now I was wondering when the netlist format is the 
key to that flexibility, whether MyHDL could take favor of developments 
already done in that area?


Cheers,

Guenter

[myhdl-list] Re: Hi, every one

[Jan D. <ja...@ja...>]

Zhang Yong wrote:
> Dear all,
> 
> I am a newbie of myhdl. Thank you all for designing the very simple,
> smart and powerful tool.

Welcome.

> I download version 0.41 from web, which was released last year. I just
> want to know: is it still in active developing now? when release the new
> version? and is there a roadmap?

With release 0.4, I had more or less implemented the features that I
could define "stand-alone" (perhaps with the exception of vhdl support.)
Since then, development depends much more on user input. If you browse
this mailing list, you will find examples of active development of
features based on suggestions and discussions with users, including
snapshots that implement those features.

In the mean time, enough new features have been implemented or defined
to warrant a new release. Still a lot to do (documentation), so it's
not immediate, but still this year.

> BTW, if i want to do some help for the develop, how?

Pick your feature: something that should be possible and that you really
need, and you can't do now. Start a discussion in this mailing list
and we'll take it from there. (Clearly specifying a feature is often
more work than implementing it.)

You can also help by doing real projects and telling the world
about it, BTW.

Jan

-- 
Jan Decaluwe - Resources bvba - http://jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
     Using Python as a hardware description language:
     http://jandecaluwe.com/Tools/MyHDL/Overview.html

[myhdl-list] Hi, every one

[Zhang Y. <yz...@ce...>]

Dear all,

I am a newbie of myhdl. Thank you all for designing the very simple,
smart and powerful tool.

I download version 0.41 from web, which was released last year. I just
want to know: is it still in active developing now? when release the new
version? and is there a roadmap?

BTW, if i want to do some help for the develop, how?

BR,
Zhang Yong

[myhdl-list] Re: Tristate logic (newbie question)

[Jan D. <ja...@ja...>]

I appreciate detailed work on patches very much, but would it
be possible to add some explanation on the patch also? I understand
it deals with tristate support but would like to know in some
sentences what the patch does and how it was verified.

Regards, Jan


José Pedro Matos wrote:
> #################################################################
> # brouter.py EXAMPLE code
> #################################################################
> from __future__ import generators
> from myhdl import Signal, Simulation, delay, traceSignals, intbv,
> toVerilog
> 
> 
> def brouter( clk, clk2m, mclk, cs_z, liu_thz, rd_z, dados, teste,
> rs232_tx, rs232_rx, addr):
>         """ brouter
>             um exemplo simples em myhdl
> 
>             input clk; CLK_CPU
>             input clk2m; CLK_2048MHz
>             output mclk; CLK_LIU_MCLK
>             input cs_z; CS_FPGA_Z
>             output liu_thz; LIU_TH_Z
>             input rd_z; RD_Z
>             inout [7:0] dados; DADOS
>             output teste; pino de test
>             output rs232_rx; RX uC porta serie 2
>             input rs232_tx; TX uC porta serie 2
>             input [19:0] addr; ADDR
>             
>         """
> #       teste.next = clk.val
> #       mclk.next = clk2m.val
> #       liu_thz.next = intbv(0)[1:]
> #       rs232_rx.next = rs232_tx.val
> 
>         def brouterProcess():
>                 while 1:
>                         yield cs_z, rd_z
>                         if (cs_z == 0) and (rd_z == 0):
>                                 dados.next = intbv(0xA5)[8:]
>                         else:
>                                 dados.next = intbv(None)[8:] #high
> impedance assign
> 
>         return brouterProcess()
> 
> 
> clk= Signal(bool(0))
> clk2m= Signal(bool(1))
> mclk = Signal(bool(0))
> cs_z = Signal(bool(1))
> liu_thz = Signal(bool(1))
> rd_z = Signal(bool(1))
> dados = Signal(intbv(0)[8:])
> teste = Signal(bool(0))
> rs232_tx = Signal(bool(1))
> rs232_rx = Signal(bool(0))
> addr = Signal(intbv(0)[20:])
> 
> dados.next = intbv(val=None,_nrbits=8)
> dados.next = intbv(None)[8:]
> 
> if dados.val._nrbits == 0:
>         print "len: 0\n"
> else:   
>         print "len: %d \n" % (dados.val._nrbits)
> 
> br_inst= toVerilog(brouter, clk, clk2m, mclk, cs_z, liu_thz, rd_z,
> dados, teste, rs232_tx, rs232_rx, addr)
> 
> #################################################################
> # GENERATED CODE
> #################################################################
> 
> module br_inst (
>     clk,
>     clk2m,
>     mclk,
>     cs_z,
>     liu_thz,
>     rd_z,
>     dados,
>     teste,
>     rs232_tx,
>     rs232_rx,
>     addr
> );
> 
> input clk;
> input clk2m;
> input mclk;
> input cs_z;
> input liu_thz;
> input rd_z;
> output [7:0] dados;
> reg [7:0] dados;
> input teste;
> input rs232_tx;
> input rs232_rx;
> input [19:0] addr;
> 
> 
> 
> always @(cs_z or rd_z) begin: _MYHDL1_BLOCK
>     if (((cs_z == 0) && (rd_z == 0))) begin
>         dados <= 8'ha5;
>     end
>     else begin
>         dados <= 8'hZ;
>     end
> end
> 
> endmodule
> 
> 
> ############################ CUT ME #############################
> # _intbv.py.patch
> ############################ CUT ME #############################
> jmatos - ~/work/hdl/myhdl-0.4.1/myhdl $ diff -u --new-file
> _intbv.py /usr/lib/python2.3/site-packages/myhdl/_intbv.py
> --- _intbv.py   2004-12-29 13:37:59.000000000 +0000
> +++ /usr/lib/python2.3/site-packages/myhdl/_intbv.py    2005-08-31
> 13:54:36.000000000 +0000
> @@ -71,14 +71,13 @@
>      min = property(_get_min, None)
>  
>      def _checkBounds(self):
> -        if self._max is not None:
> -            if self._val >= self._max:
> -                raise ValueError("intbv value %s >= maximum %s" %
> -                                 (self._val, self._max))
> -        if self._min is not None:
> -            if self._val < self._min:
> -                raise ValueError("intbv value %s < minimum %s" %
> -                                 (self._val, self._min))
> +       if self._val is not None:
> +               if self._max is not None:
> +                       if self._val >= self._max:
> +                               raise ValueError("intbv value %s >=
> maximum %s" % (self._val, self._max))
> +                       if self._min is not None:
> +                       if self._val < self._min:
> +                               raise ValueError("intbv value %s <
> minimum %s" % (self._val, self._min))
>  
>  
>      # hash
> @@ -113,7 +112,10 @@
>      def __getitem__(self, key):
>          if isinstance(key, int):
>              i = key
> -            res = intbv((self._val >> i) & 0x1, _nrbits=1)
> +           if self._val is None:
> +               res= intbv(None,_nrbits=1)
> +           else:
> +               res = intbv((self._val >> i) & 0x1, _nrbits=1)
>              return res
>          elif isinstance(key, slice):
>              i, j = key.start, key.stop
> @@ -127,7 +129,10 @@
>              if i <= j:
>                  raise ValueError, "intbv[i:j] requires i > j\n" \
>                        "            i, j == %s, %s" % (i, j)
> -            res = intbv((self._val & (1L << i)-1) >> j, _nrbits=i-j)
> +           if self._val is None:
> +               res= intbv(None,_nrbits=i-j)
> +           else:
> +                res = intbv((self._val & (1L << i)-1) >> j,
> _nrbits=i-j)
>              return res
>          else:
>              raise TypeError("intbv item/slice indices should be
> integers")
> ############ CUT ME ###############################################
> 
> 
> ############ CUT ME ###############################################
> #  _convert.py.patch
> ############ CUT ME ###############################################
> jmatos - ~/work/hdl/myhdl-0.4.1/myhdl $ diff -u
> _toVerilog/_convert.py /usr/lib/python2.3/site-packages/myhdl/_toVerilog/_convert.py
> --- _toVerilog/_convert.py      2004-12-24 13:35:02.000000000 +0000
> +++ /usr/lib/python2.3/site-packages/myhdl/_toVerilog/_convert.py
> 2005-08-31 13:58:31.000000000 +0000
> @@ -654,7 +654,10 @@
>             node.expr.node.obj is intbv:
>              c = self.getVal(node)
>              self.write("%s'h" % c._nrbits)
> -            self.write("%x" % c._val)
> +            if c._val is not None:
> +               self.write("%x" % c._val)
> +           else:
> +               self.write("Z") 
>              return
>          self.visit(node.expr)
>          self.write("[")
> ############ CUT ME ###############################################
> 
> 
> 
> -------------------------------------------------------
> SF.Net email is Sponsored by the Better Software Conference & EXPO
> September 19-22, 2005 * San Francisco, CA * Development Lifecycle Practices
> Agile & Plan-Driven Development * Managing Projects & Teams * Testing & QA
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-- 
Jan Decaluwe - Resources bvba - http://jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
     Using Python as a hardware description language:
     http://jandecaluwe.com/Tools/MyHDL/Overview.html