myhdl-list — Mailing list for discussions on MyHDL

Re: [myhdl-list] Re: wiki login problems

[George P. <ge...@ga...>]

> themaxx? (I can remove the entry if you want).
>
> You can just create a new login. The password is generated
> automatically and mailed to you (I would keep the mail instead
> of trying to remember it ;-)). I suggest to let your browser
> remember name and password in the future (firefox does this,
> don't know about other browsers.)
>

Yes, you can go ahead and remove that entry. Thanks again :)


-- 
George Pantazopoulos
http://www.gammaburst.net

[myhdl-list] Re: Feedback request on decorators in MyHDL

[Jan D. <ja...@ja...>]

bedros wrote:
> great work Jan, I've not touched Myhdl in over a year,
> and I'm very impressed with how you use decorators in
> MyHDL. it makes Myhdl very similar to a real RTL.
> 
> ease of use is very important to attract developers,
> and it seems you're going in the right direction.
> 
> what's holding me back from using it is the fact that
> I  can't integrate it with VHDL code. What's the
> status of VHPI interface?

Not even thought about it :-)

Is VHPI actually used? By which simulator?

At some point I considered to do a modelsim interface
in their proprietary interface, because I thought that
was the most popular C-interface. But for various reasons
(such as changing MyHDL priorities), I haven't started this.
Also, I fear there might be legal issues if I develop
something in a proprietary API without even owning
a modelsim license.

In Verilog, I have at least 2 options to develop a vpi
interface with an open source simulator. I still don't know about
an open-source VHDL solution with a vpi-like support.
Without that, it's going to be hard. Moreover, one could
argue that this means that the need is just not there.

> Any updates on simulators for myhdl?

I used cver and Icarus, and I know people are using
Modelsim Verilog also.

Regards, Jan


-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
     Electronic design with Python:
     http://myhdl.jandecaluwe.com

[myhdl-list] Re: wiki login problems

[Jan D. <ja...@ja...>]

George Pantazopoulos wrote:
> Hi Jan,
> 
>    Clicking "Login" in the wiki this morning produced "Internal Server
> Error 500". 

I see that occasionally - don't know why. Just try again,
the wiki is still there.

 > In addition, I've forgotten my password (and maybe even my
> exact login) and I don't see a way to retrive either.

themaxx? (I can remove the entry if you want).

You can just create a new login. The password is generated
automatically and mailed to you (I would keep the mail instead
of trying to remember it ;-)). I suggest to let your browser
remember name and password in the future (firefox does this,
don't know about other browsers.)

Note that I am using this system so that I am sure that
registration is done with a valid e-mail address. It's the
default in dokuwiki and I hope it's effective against
wikispam.

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
     Electronic design with Python:
     http://myhdl.jandecaluwe.com

[myhdl-list] wiki login problems

[George P. <ge...@ga...>]

Hi Jan,

   Clicking "Login" in the wiki this morning produced "Internal Server
Error 500". In addition, I've forgotten my password (and maybe even my
exact login) and I don't see a way to retrive either.

Thanks,

-- 
George Pantazopoulos
http://www.gammaburst.net

[myhdl-list] Re: return instances(), processes()

[Jan D. <ja...@ja...>]

George Pantazopoulos wrote:
> Hi all,
> 
>     I have some functions that contain both instances and processes. I'd 
> like to be able to return all of them simply by doing "return 
> instances(), processes()". However, this doesn't work, and I have to 
> return all the elements manually. Is there some other way to accomplish 
> this?

Please post a (small) example that doesn't work. It should.

Note that I'm about to deprecate the processes() function however.
(See the document on decorators in MyHDL 0.5). I think it's too
confusing. In the future, create an instance for everything (possibly
automatically using decorators). Function instances() is here to stay,
however.

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
     Electronic design with Python:
     http://myhdl.jandecaluwe.com

[myhdl-list] Re: myHDL success: synthesized a UAR(T)

[Jan D. <ja...@ja...>]

George Pantazopoulos wrote:

>      I used the Verilog UART design on fpga4fun.com as a reference, and 
> some posts from comp.arch.fpga, and sci.electronics.design for further 
> guidance. With this knowledge, I recreated the asynchronous receiver in 
> myHDL. It took some time and effort, because I wanted to do things right 
> and understand the concepts involved, not just blindly port code. A 
> significant thing that ate up time was the almost impossible to 
> understand error messages when something was wrong in the code. Is that 
> something you could improve?

Probably, but only if you let me know the full details. The goal is that
the error messages should be crystal-clear, and currently I think
they are :-)

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
     Electronic design with Python:
     http://myhdl.jandecaluwe.com

[myhdl-list] return instances(), processes()

[George P. <ge...@ga...>]

Hi all,

     I have some functions that contain both instances and processes. 
I'd like to be able to return all of them simply by doing "return 
instances(), processes()". However, this doesn't work, and I have to 
return all the elements manually. Is there some other way to accomplish 
this?

Thanks,
George

[myhdl-list] myHDL success: synthesized a UAR(T)

[George P. <ge...@ga...>]

Jan,

     The combination of python, myHDL, and GTKWave is powerful. With 
these tools, I succeeded in synthesizing a UART, and late last night I 
watched with joy as the LED's on my FPGA board lit up to represent the 
value of the bytes sent (at 57600 baud) from my PC!

      I used the Verilog UART design on fpga4fun.com as a reference, and 
some posts from comp.arch.fpga, and sci.electronics.design for further 
guidance. With this knowledge, I recreated the asynchronous receiver in 
myHDL. It took some time and effort, because I wanted to do things right 
and understand the concepts involved, not just blindly port code. A 
significant thing that ate up time was the almost impossible to 
understand error messages when something was wrong in the code. Is that 
something you could improve?

I learned a great deal, and am more comfortable with myHDL and hardware 
design than ever now. Now to tackle the transmit side of the UART! Keep 
up the great work on myHDL. It is clearly a success.

George

[myhdl-list] signed arithmetic

[Jan D. <ja...@ja...>]

Hi all:

I have added support for Verilog conversion of signed arithmetic to the
development version. You can read about it here:

http://myhdl.jandecaluwe.com/doku.php/whatsnew:0.5#support_for_signed_arithmetic

All those interested are encouraged to read this and provide feedback.

A development snapshot is available (0.5dev3).

In the mean time, my development attention will again go to other
things :-) One feature to go for 0.5 ... (custom Verilog code).

Regards,

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
     Electronic design with Python:
     http://myhdl.jandecaluwe.com

[myhdl-list] omiting .next should cause an error

[George P. <ge...@ga...>]

Hi Jan,

    I've often run into the situation where I forget to use .next for a 
variable, and it produces subtle errors that are hard to detect.

(eg. doing "count = (count + 1) % 2**COUNTER_WIDTH", rather than doing 
"count.next = (count + 1) % 2**COUNTER_WIDTH)". I often slip up because 
I'm very used to programming in C/C++ at work. I feel that myHDL should 
flag this as an obvious error.

Thanks,
George

Re: [myhdl-list] Interfacing to existing Verilog/VHDL

[Tom D. <td...@di...>]

George,

I think what you are looking for is support for user defined Verilog 
code, slated for next release.

http://myhdl.jandecaluwe.com/doku.php/whatsnew:0.5

Tom


George Pantazopoulos wrote:

> Hi all,
>     Is it possible for me to connect (at the python level) my 
> myHDL-generated Verilog with some pre-existing Verilog/VHDL code (eg. 
> from OpenCores)?
>
> Thanks,
> George
>
>
>
> -------------------------------------------------------
> This SF.Net email is sponsored by the JBoss Inc.
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[myhdl-list] Interfacing to existing Verilog/VHDL

[George P. <ge...@ga...>]

Hi all,
     Is it possible for me to connect (at the python level) my 
myHDL-generated Verilog with some pre-existing Verilog/VHDL code (eg. 
from OpenCores)?

Thanks,
George

[myhdl-list] Re: signed bit vectors

[Jan D. <ja...@ja...>]

Matt Ettus wrote:
> Tom Dillon wrote:
> 
>>Matt,
>>
>>The current version of toVerilog does not support signed numbers.
>>
>>It is in the works for the next release. Check out the new features:
>>
>>http://myhdl.jandecaluwe.com/doku.php/whatsnew:0.5
> 
> 
> 
> I'm not using toVerilog.  I am doing cosimulation with icarus, and
> negative numbers I send into the verilog side have x's in them (but not
> all the bits, just the upper ones).

As it happens, I am working on signed support for Verilog currently. It
was not yet supported for Verilog conversion (documented) and for
co-simulation (undocumented - don't know why). I deferred this because I 
thought it would be tricky. It is! (at the Verilog side).

I have found that Icarus is buggy with respect to signed support. See:

    http://groups.google.be/groups?q=Verilog+signed+arithmetic+Decaluwe

"Buggy" simply means that it doesn't what other Verilog simulators,
including the big ones, do. I am relying on Cver for this now.

Development version 0.5dev2 has Verilog co-simulation support for
negative intbv's (I need this to verify the Verilog conversion work).

Regards, Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
     Electronic design with Python:
     http://myhdl.jandecaluwe.com

[myhdl-list] Re: signed bit vectors

[Jan D. <ja...@ja...>]

David Brochart wrote:
> Yes, but you can also specify the range explicitly:
> 
> s = Signal(intbv(0)[m : n])
> 
> s would be a std_logic_vector(m - 1 downto n) in VHDL.

Actually, it's more like std_logic_vector(m-n-1 downto 0). However, the
typical usage pattern in this case would be with n=0.

I thought it was useful to add a FAQ entry for the original question:

    http://myhdl.jandecaluwe.com/doku.php/faq

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
     Electronic design with Python:
     http://myhdl.jandecaluwe.com

Re: [myhdl-list] signed bit vectors

[Matt E. <ma...@et...>]

Tom Dillon wrote:
> Matt,
> 
> There are also a couple of changes required to _Cosimulation.py to pass
> the numbers properly.
> 
> I can send you my hacked version if you like.

That would be a wonderful help, thanks!

Matt

Re: [myhdl-list] signed bit vectors

[Tom D. <td...@di...>]

Matt,

There are also a couple of changes required to _Cosimulation.py to pass 
the numbers properly.

I can send you my hacked version if you like.

Tom


Matt Ettus wrote:

>Tom Dillon wrote:
>  
>
>>Matt,
>>
>>The current version of toVerilog does not support signed numbers.
>>
>>It is in the works for the next release. Check out the new features:
>>
>>http://myhdl.jandecaluwe.com/doku.php/whatsnew:0.5
>>    
>>
>
>
>I'm not using toVerilog.  I am doing cosimulation with icarus, and
>negative numbers I send into the verilog side have x's in them (but not
>all the bits, just the upper ones).
>
>Matt
>
>
>-------------------------------------------------------
>This SF.Net email is sponsored by the JBoss Inc.
>Get Certified Today * Register for a JBoss Training Course
>Free Certification Exam for All Training Attendees Through End of 2005
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>_______________________________________________
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>https://lists.sourceforge.net/lists/listinfo/myhdl-list
>
>  
>

Re: [myhdl-list] signed bit vectors

[Matt E. <ma...@et...>]

Tom Dillon wrote:
> Matt,
> 
> The current version of toVerilog does not support signed numbers.
> 
> It is in the works for the next release. Check out the new features:
> 
> http://myhdl.jandecaluwe.com/doku.php/whatsnew:0.5


I'm not using toVerilog.  I am doing cosimulation with icarus, and
negative numbers I send into the verilog side have x's in them (but not
all the bits, just the upper ones).

Matt

Re: [myhdl-list] signed bit vectors

[Tom D. <td...@di...>]

Matt,

The current version of toVerilog does not support signed numbers.

It is in the works for the next release. Check out the new features:

http://myhdl.jandecaluwe.com/doku.php/whatsnew:0.5

Tom



Matt Ettus wrote:

>nicran wrote:
>  
>
>>As I know, there is no way to specify the bitwidth, you can only
>>specify the default value of a bitvector.
>>
>>
>>2005/10/25, Matt Ettus <ma...@et...>:
>>
>>    
>>
>>>I just discovered MyHDL today, and it appears to be just what I've been
>>>looking for!  Thanks for making it and for documenting it so well!  I
>>>was able to get up and running with complex simulations in less than
>>>half a day.
>>>
>>>I just have a couple of questions -- Is there any way to make intbv's
>>>signed?  Also, how do I specify the bitwidth?
>>>      
>>>
>
>I just found how to set ranges, which is I guess the substitute for
>setting bitwidths.  However, when I set an intbv signal to a negative
>value, it is giving me X's in my verilog simulation.
>
>Any ideas?
>
>Thanks,
>Matt
>
>
>-------------------------------------------------------
>This SF.Net email is sponsored by the JBoss Inc.
>Get Certified Today * Register for a JBoss Training Course
>Free Certification Exam for All Training Attendees Through End of 2005
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>https://lists.sourceforge.net/lists/listinfo/myhdl-list
>
>  
>

Re: [myhdl-list] signed bit vectors

[David B. <dav...@fr...>]

Yes, but you can also specify the range explicitly:

s =3D Signal(intbv(0)[m : n])

s would be a std_logic_vector(m - 1 downto n) in VHDL.

David.



Selon Matt Ettus <ma...@et...>:

> David Brochart wrote:
> > Yes you can:
> >
> > http://www.jandecaluwe.com/Tools/MyHDL/manual/ref-intbv.html
> >
>
> Do you mean that the bitwidth is specified implicitly through the min
> and max?
>
> Matt
>
>
> -------------------------------------------------------
> This SF.Net email is sponsored by the JBoss Inc.
> Get Certified Today * Register for a JBoss Training Course
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>

Re: [myhdl-list] signed bit vectors

[Matt E. <ma...@et...>]

David Brochart wrote:
> Yes you can:
> 
> http://www.jandecaluwe.com/Tools/MyHDL/manual/ref-intbv.html
> 

Do you mean that the bitwidth is specified implicitly through the min
and max?

Matt

Re: [myhdl-list] signed bit vectors

[Matt E. <ma...@et...>]

nicran wrote:
> As I know, there is no way to specify the bitwidth, you can only
> specify the default value of a bitvector.
> 
> 
> 2005/10/25, Matt Ettus <ma...@et...>:
> 
>>I just discovered MyHDL today, and it appears to be just what I've been
>>looking for!  Thanks for making it and for documenting it so well!  I
>>was able to get up and running with complex simulations in less than
>>half a day.
>>
>>I just have a couple of questions -- Is there any way to make intbv's
>>signed?  Also, how do I specify the bitwidth?

I just found how to set ranges, which is I guess the substitute for
setting bitwidths.  However, when I set an intbv signal to a negative
value, it is giving me X's in my verilog simulation.

Any ideas?

Thanks,
Matt

Re: [myhdl-list] signed bit vectors

[David B. <dav...@fr...>]

Yes you can:

http://www.jandecaluwe.com/Tools/MyHDL/manual/ref-intbv.html

David.



Selon nicran <ni...@gm...>:

> As I know, there is no way to specify the bitwidth, you can only
> specify the default value of a bitvector.
>
>
> 2005/10/25, Matt Ettus <ma...@et...>:
> > I just discovered MyHDL today, and it appears to be just what I've be=
en
> > looking for!  Thanks for making it and for documenting it so well!  I
> > was able to get up and running with complex simulations in less than
> > half a day.
> >
> > I just have a couple of questions -- Is there any way to make intbv's
> > signed?  Also, how do I specify the bitwidth?
> >
> > Thanks,
> > Matt
> >
> >
> > -------------------------------------------------------
> > This SF.Net email is sponsored by the JBoss Inc.
> > Get Certified Today * Register for a JBoss Training Course
> > Free Certification Exam for All Training Attendees Through End of 200=
5
> > Visit http://www.jboss.com/services/certification for more informatio=
n
> > _______________________________________________
> > myhdl-list mailing list
> > myh...@li...
> > https://lists.sourceforge.net/lists/listinfo/myhdl-list
> >
>
>
> -------------------------------------------------------
> This SF.Net email is sponsored by the JBoss Inc.
> Get Certified Today * Register for a JBoss Training Course
> Free Certification Exam for All Training Attendees Through End of 2005
> Visit http://www.jboss.com/services/certification for more information
> _______________________________________________
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>

Re: [myhdl-list] signed bit vectors

[nicran <ni...@gm...>]

As I know, there is no way to specify the bitwidth, you can only
specify the default value of a bitvector.


2005/10/25, Matt Ettus <ma...@et...>:
> I just discovered MyHDL today, and it appears to be just what I've been
> looking for!  Thanks for making it and for documenting it so well!  I
> was able to get up and running with complex simulations in less than
> half a day.
>
> I just have a couple of questions -- Is there any way to make intbv's
> signed?  Also, how do I specify the bitwidth?
>
> Thanks,
> Matt
>
>
> -------------------------------------------------------
> This SF.Net email is sponsored by the JBoss Inc.
> Get Certified Today * Register for a JBoss Training Course
> Free Certification Exam for All Training Attendees Through End of 2005
> Visit http://www.jboss.com/services/certification for more information
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>

[myhdl-list] signed bit vectors

[Matt E. <ma...@et...>]

I just discovered MyHDL today, and it appears to be just what I've been
looking for!  Thanks for making it and for documenting it so well!  I
was able to get up and running with complex simulations in less than
half a day.

I just have a couple of questions -- Is there any way to make intbv's
signed?  Also, how do I specify the bitwidth?

Thanks,
Matt

[myhdl-list] Re: upgrading from 0.4

[Jan D. <ja...@ja...>]

George Pantazopoulos wrote:
> Hi all,
> 
>    To upgrade, can I just install myHDL 0.5 over my current installation 
> of 0.4? (I'm using 0.4 on cygwin)

Although that should work, I would first move the existing installation
away so that you can go back easily if required. Note that there are
only development snapshots for 0.5.

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
     Electronic design with Python:
     http://myhdl.jandecaluwe.com