myhdl-list — Mailing list for discussions on MyHDL

Re: [myhdl-list] myhdl.org page

[Brendan R. <bre...@gm...>]

Jan Decaluwe <jan <at> jandecaluwe.com> writes:

> > Hi Jan,
> > 
> > Have you looked at Skeletonz (http://orangoo.com/skeletonz/).  The maintainer is
> > a sharp coder and it's based on Python.
> 
> Briefly.
> 
> It seems to have some interesting features (e.g. simple plugin system)
> but the markup language seems to be missing some features we need.
> 
> More importantly, this seems to be an early-stage projects with not
> that many users (e.g. no ready to use third-party templates).
> Also, I just read an e-mail from the lead developer
> (answering to someone who asked what he plans to do on Skeletonz
> now that he has a new job) stating that he considers the work "done"
> and that he doesn't plan to add new features.
> 
> So I am not over-exited.
> 
> Jan
> 

Plone's your only other realistic option.  I think it will have Wiki-like markup
support (Textile/Markup) in version 3.0, and, of course, it is rather
feature-rich (with the associated bloat).

Good luck!

- Brendan

Re: [myhdl-list] myhdl.org page

[Jan D. <ja...@ja...>]

Brendan Rankin wrote:
> Jan Decaluwe <jan <at> jandecaluwe.com> writes:
> 
> 
>>Hi:
>>
>>I have finally written a page about a future myhdl.org website:
>>
>>    http://myhdl.jandecaluwe.com/doku.php/dev:myhdl.org
>>
>>Regards,
>>
>>Jan
>>
> 
> 
> Hi Jan,
> 
> Have you looked at Skeletonz (http://orangoo.com/skeletonz/).  The maintainer is
> a sharp coder and it's based on Python.

Briefly.

It seems to have some interesting features (e.g. simple plugin system)
but the markup language seems to be missing some features we need.

More importantly, this seems to be an early-stage projects with not
that many users (e.g. no ready to use third-party templates).
Also, I just read an e-mail from the lead developer
(answering to someone who asked what he plans to do on Skeletonz
now that he has a new job) stating that he considers the work "done"
and that he doesn't plan to add new features.

So I am not over-exited.

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
     From Python to silicon:
     http://myhdl.jandecaluwe.com

Re: [myhdl-list] myhdl.org page

[Brendan R. <bre...@gm...>]

Jan Decaluwe <jan <at> jandecaluwe.com> writes:

> 
> Hi:
> 
> I have finally written a page about a future myhdl.org website:
> 
>     http://myhdl.jandecaluwe.com/doku.php/dev:myhdl.org
> 
> Regards,
> 
> Jan
>

Hi Jan,

Have you looked at Skeletonz (http://orangoo.com/skeletonz/).  The maintainer is
a sharp coder and it's based on Python.

Regards,

- Brendan

[myhdl-list] myhdl.org page

[Jan D. <ja...@ja...>]

Hi:

I have finally written a page about a future myhdl.org website:

    http://myhdl.jandecaluwe.com/doku.php/dev:myhdl.org

Regards,

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
     From Python to silicon:
     http://myhdl.jandecaluwe.com

Re: [myhdl-list] =?utf-8?q?Visual_Timing_Specification_for_unit_testi?= =?utf-8?q?ng_-=09complete_example?=

[M. <jos...@pt...>]

Great.
I changed your code to suport "negedge" clk. 

It seams to work
:)
...


# - Begin code ---------------------------------------------------------------

# myhdl_vts.py
# George Pantazopoulos http://www.gammaburst.net

from myhdl import *

# ----------------------------------------------------------------------------

def visual_timing_spec_parse(vts, print_cts=False):
    """
    Visual Timing Specification parser for MyHDL

    Parses a Visual Timing Specification into a condensed
    format suitable for driving or checking signals

    A Visual Timing Specification (VTS) is an ascii-based
    format for conveying signal timing information.

    The same timing spec is both human- and machine-readable.

    A VTS object can be used for driving signals as well
    as checking signal outputs.

    Example VTS objects:

        signals_to_drive = dict(
        edges =   "|0....|1....|2....|3....|4....|5....|6....",
        rst   =   "------____________________________________",
        we    =   "______------------________________________",
        re    =   "____________------------__________________",
        dwr   =   "0x00  0b110 0xBB  0xCC  0xDD  ...   0xEE  ")

        correct_outputs = dict(
        edges =   "|0....|1....|2....|3....|4....|5....|6....",
        drd   =   "X     0     X     0b110 0xBB  X     X     ",
        empty =   "X     ------____________------------------",
        full  =   "X     ____________________________________")

    - A VTS is a Python dictionary.

    - Each dictionary key is the name of a signal in the design.

    - Each key's value is an ASCII string describing that signals behavior

    - In addition to the signal keys, a special key named 'edges'
      is required.

      Its string value contains edge markers and padding. The edge markers
      are denoted by '|' for positive edges.
      Other characters are currently ignored.

    How a VTS is parsed:
    --------------------

    - Only characters "under" the edge markers are looked at.

    - '-' = signal is high at this clock edge

    - '_' = signal is low  at this clock edge

    - '.' = no change    (used when driving signals)

    - 'X' = "don't care" (used when checking signals)

    - integer data values are supported.
      Their first character needs to be under the edge marker.

      Hex values must be preceded by "0x"
      Binary values must be preceded by "0b"

      Padding may be added to the 'edges' string to accomodate
      data values of any length. One whitespace character must follow
      the data item and come before the next edge marker.

     
    Timing:
    -------

    When driving signals with the VTS, assume that the signal
    will be valid at the clock edge.

    When checking signals with the VTS, the signal value checked for
    must be valid by the time the corresponding edge arrives.

     
    Condensed Timing Spec
    ---------------------

    The result of parsing a Visual Timing Spec is a Condensed Timing Spec.
    Its format is similar to the VTS, except that it's not restricted to
    ASCII and contains only the data for each clock edge, with no padding.

    The CTS is to be passed as input to the actual driver and monitor
    functions.  

    TODO:
    -----

    TODO: Make it possible to optionally specify negedges too. Eg:
    edges  =   "|0....v.....|1....v.....|2....v...."
    Where 'v' denotes a negedge

    TODO: Make it possible to concatenate multiple VTS's into a list,
    so long timing specs remain easily readable.

    """

    __author__   = "George Pantazopoulos http://www.gammaburst.net"
    __revision__ = ""
    __date__     = "2 Oct 2006"
    __version__  = "0.1.0"
    __requires__ = ('myhdl', '>= 0.5.1')

    # Create an empty Condensed Timing Specification
    cts = dict()

    for sig in vts:
        cts[sig] = []

    # There should be dictionary item called "edges"
    # We'll use this to figure out when to sample

    edgenum = 0
    # For each character in the 'edges' specifier string
    for i in range(len(vts['edges'])):

        # Grab the character value
        c = vts['edges'][i]

        if c == '/' or c == '\\':
            # We sample here.

            # For each signal specifier string in vts
            for sig in vts:

                if sig == 'edges':
                    data = ( edgenum , c=='/' )
                    edgenum += 1

                elif sig != 'edges':

                    # Get the character at the edge sampling index
                    d = vts[sig][i]

                    if   d == '_':
                        data = False

                    elif d == '-':
                        data = True

                    # This is a "don't-care".
                    # Intended for use when checking signals,
                    # not driving them.
                    elif d == 'X':
                        data = ' '

                    # "dont update this signal" when used for driving
                    elif (d == '.'):
                        data = ' '

                    # A space under an edge marker is illegal, because it
                    # could mean a formatting error was made by the user.
                    #
                    # This type of error can be hard to spot.
                    # If we don't trap this, it could lead to wasted time
                    # and misleading test results.
                    elif d == ' ':

                        diag = "signal: " + sig + ", offset=" + str(i)
                        raise Exception, \
                        "Spaces are not allowed under edge markers " + diag

                    else:
                        # Treat this char that's under the edge marker
                        # as the start of a data value string
                        #
                        # We need to parse the data string until we reach
                        # whitespace or the next edge marker.
                        #                               
                        # grab the next chars until we hit whitespace or the
                        # next edge marker.
                        #
                        # Start at the char 'under' the current edge marker.

                        # TODO: Stop if we hit the next edge marker        

                        n = 0
                        dstr = ""
                        while d != ' ':
                            d = vts[sig][i+n]
                            dstr += d
                            n += 1

                        # convert to an int.
                        # The (required) trailing whitespace is ok.

                        # Hex
                        if   dstr[:2] == "0x":
                            data = int(dstr[2:],16)   

                        # Binary
                        elif dstr[:2] == "0b":
                            data = int(dstr[2:], 2)

                        # Decimal
                        else:
                            data = int(dstr)

                # Add the data item to the appropriate signal's list.       
                cts[sig].append(data)

                   
    if print_cts:

        print "cts: "

        import pprint
        print pprint.pprint(cts) 

          
    return cts   

# ----------------------------------------------------------------------------

def drive_signals_from_cts(sigs, cts):
    """
    drive_signals_from_cts() - unit test tool for MyHDL

    Given a Condensed Timing Spec object, drive the signals according to
    that specification. See the Visual Timing Spec parser doc.

    The signal dictionary must contain a 'clk' signal
    """

    __author__   = "George Pantazopoulos http://www.gammaburst.net"
    __revision__ = ""
    __date__     = "2 Oct 2006"
    __version__  = "0.1.0"
    __requires__ = ('myhdl', '>= 0.5.1')

    if 'clk' not in sigs:
        raise Exception, \
        "signal dictionary 'sigs' must contain a 'clk' signal"

    clk = sigs['clk']

    for i in range(len(cts['edges'])):

	if 1==cts['edges'][i][1]:
        	# Setup for positive edge i

        	# Drive each signal with the correct value for
        	# the upcoming positive edge i
        	for sig in cts:
            		value = cts[sig][i]
            		if sig != 'edges':
				if value != ' ':
                    			sigs[sig].next = value

        	# positive edge i
        	yield clk.posedge
	if 0==cts['edges'][i][1]:
        	# Setup for negative edge i

        	# Drive each signal with the correct value for
        	# the upcoming positive edge i
        	for sig in cts:
            		value = cts[sig][i]
            		if sig != 'edges':
				if value != ' ':
                    			sigs[sig].next = value


        	# negative edge i
        	yield clk.negedge

# ----------------------------------------------------------------------------

def check_signals_against_cts(sigs, cts):
    """
    check_signals_against_cts() - unit test tool for MyHDL

    Given a Condensed Timing Spec object, ensure the signals match
    that specification. See the Visual Timing Spec parser doc.

    The signal dictionary must contain a 'clk' signal
    """      

    __author__   = "George Pantazopoulos http://www.gammaburst.net"
    __revision__ = ""
    __date__     = "2 Oct 2006"
    __version__  = "0.1.0"
    __requires__ = ('myhdl', '>= 0.5.1')

    if 'clk' not in sigs:
        raise Exception, \
        "signal dictionary 'sigs' must contain a 'clk' signal"

    clk = sigs['clk']

            
    for i in range(len(cts['edges'])):

        # Setup for edge i
        if 1==cts['edges'][i][1]:
            # Edge i
            yield clk.posedge
	else:
	    yield clk.negedge

        # Check the outputs that should have been valid by
        # the time this edge comes around
        for sig in cts:

            value = cts[sig][i]

            if sig != 'edges':

                # Skip this for 'don't-care' values
                if value != ' ':

                    # If the signal is not the value it should have been
                    if sigs[sig] != value:

                        # Raise an exception and show some helpful info.
                        info = "Edge #" + str(i) + \
                               " Signal \'" + sig + "\'" + \
                               " = "  + str(sigs[sig]) + \
                               ". Correct value = " + str(value)
                        raise Exception, info         

        #yield clk.negedge

         
    raise StopSimulation()

# ----------------------------------------------------------------------------

def up_counter(sigs):

    # Unbundle needed signals. Name them from the perspective of this module.
    clk_i    = sigs['clk']
    rst_i    = sigs['rst']

    count_o  = sigs['count']   
    enable_i = sigs['count_en']

    @always(clk_i.posedge)
    def count_proc():

        if rst_i:
            count_o.next = 0

        else:
            if enable_i:
                count_o.next = (count_o + 1) % 2**len(count_o)

    return instances()

# ----------------------------------------------------------------------------

def up_counter_bench():

    # Embedded function definition for clock generator
    def clkgen(clk):

        while True:
            yield delay(10)
            clk.next = not clk

    # Shared clk signal
    clk = Signal(bool(0))

    # Create the signal group for the counter
    counter_sigs=dict(clk      = clk,
                      rst      = Signal(bool(0)),
                      count    = Signal(intbv(0)[4:]),
                      count_en = Signal(bool(0)))

    # Instantiate a clock generator and connect to the shared clock
    clkgen_inst = clkgen(clk)

    dut = up_counter(counter_sigs)

    # Visual Timing Specification
    # ---------------------------

    signals_to_drive = dict(
    edges      = "/0____/1--\__/2____/3____/4____/5____/6____",
    rst        = "--------------_____________________________",
    count_en   = "___________________------------------------")

    correct_outputs = dict(
    edges      = "/0____/1--\__/2____/3____/4____/5____/6____",
    count      = "X     0   0  0     0     1     2     3     ")

    # Signal driver
    driver = drive_signals_from_cts(

            sigs = counter_sigs,
            cts  = visual_timing_spec_parse(signals_to_drive)
            )

    # Signal monitor
    monitor = check_signals_against_cts(

            sigs = counter_sigs,
            cts  = visual_timing_spec_parse(correct_outputs)
            )   

    return instances()

# ----------------------------------------------------------------------------

if __name__ == '__main__':
    def test_up_counter():
        tb = up_counter_bench()
        sim = Simulation(tb)
        sim.run()

    test_up_counter()

# - End code -----------------------------------------------------------------

Re: [myhdl-list] =?utf-8?q?Visual_Timing_Specification_for_unit_testi?= =?utf-8?q?ng_-=09complete_example?=

[M. <jos...@pt...>]

I think it is great!

I've altered your code to suport negedges. Hope it works fine!

:)


# - Begin code ---------------------------------------------------------------

# myhdl_vts.py
# George Pantazopoulos http://www.gammaburst.net

from myhdl import *

# ----------------------------------------------------------------------------

def visual_timing_spec_parse(vts, print_cts=False):
    """
    Visual Timing Specification parser for MyHDL

    Parses a Visual Timing Specification into a condensed
    format suitable for driving or checking signals

    A Visual Timing Specification (VTS) is an ascii-based
    format for conveying signal timing information.

    The same timing spec is both human- and machine-readable.

    A VTS object can be used for driving signals as well
    as checking signal outputs.

    Example VTS objects:

        signals_to_drive = dict(
        edges =   "|0....|1....|2....|3....|4....|5....|6....",
        rst   =   "------____________________________________",
        we    =   "______------------________________________",
        re    =   "____________------------__________________",
        dwr   =   "0x00  0b110 0xBB  0xCC  0xDD  ...   0xEE  ")

        correct_outputs = dict(
        edges =   "|0....|1....|2....|3....|4....|5....|6....",
        drd   =   "X     0     X     0b110 0xBB  X     X     ",
        empty =   "X     ------____________------------------",
        full  =   "X     ____________________________________")

    - A VTS is a Python dictionary.

    - Each dictionary key is the name of a signal in the design.

    - Each key's value is an ASCII string describing that signals behavior

    - In addition to the signal keys, a special key named 'edges'
      is required.

      Its string value contains edge markers and padding. The edge markers
      are denoted by '|' for positive edges.
      Other characters are currently ignored.

    How a VTS is parsed:
    --------------------

    - Only characters "under" the edge markers are looked at.

    - '-' = signal is high at this clock edge

    - '_' = signal is low  at this clock edge

    - '.' = no change    (used when driving signals)

    - 'X' = "don't care" (used when checking signals)

    - integer data values are supported.
      Their first character needs to be under the edge marker.

      Hex values must be preceded by "0x"
      Binary values must be preceded by "0b"

      Padding may be added to the 'edges' string to accomodate
      data values of any length. One whitespace character must follow
      the data item and come before the next edge marker.

     
    Timing:
    -------

    When driving signals with the VTS, assume that the signal
    will be valid at the clock edge.

    When checking signals with the VTS, the signal value checked for
    must be valid by the time the corresponding edge arrives.

     
    Condensed Timing Spec
    ---------------------

    The result of parsing a Visual Timing Spec is a Condensed Timing Spec.
    Its format is similar to the VTS, except that it's not restricted to
    ASCII and contains only the data for each clock edge, with no padding.

    The CTS is to be passed as input to the actual driver and monitor
    functions.  

    TODO:
    -----

    TODO: Make it possible to optionally specify negedges too. Eg:
    edges  =   "|0....v.....|1....v.....|2....v...."
    Where 'v' denotes a negedge

    TODO: Make it possible to concatenate multiple VTS's into a list,
    so long timing specs remain easily readable.

    """

    __author__   = "George Pantazopoulos http://www.gammaburst.net"
    __revision__ = ""
    __date__     = "2 Oct 2006"
    __version__  = "0.1.0"
    __requires__ = ('myhdl', '>= 0.5.1')

    # Create an empty Condensed Timing Specification
    cts = dict()

    for sig in vts:
        cts[sig] = []

    # There should be dictionary item called "edges"
    # We'll use this to figure out when to sample

    edgenum = 0
    # For each character in the 'edges' specifier string
    for i in range(len(vts['edges'])):

        # Grab the character value
        c = vts['edges'][i]

        if c == '|' or c == '^':
            # We sample here.

            # For each signal specifier string in vts
            for sig in vts:

                if sig == 'edges':
                    data = ( edgenum , c=='|' )
                    edgenum += 1

                elif sig != 'edges':

                    # Get the character at the edge sampling index
                    d = vts[sig][i]

                    if   d == '_':
                        data = False

                    elif d == '-':
                        data = True

                    # This is a "don't-care".
                    # Intended for use when checking signals,
                    # not driving them.
                    elif d == 'X':
                        data = ' '

                    # "dont update this signal" when used for driving
                    elif (d == '.'):
                        data = ' '

                    # A space under an edge marker is illegal, because it
                    # could mean a formatting error was made by the user.
                    #
                    # This type of error can be hard to spot.
                    # If we don't trap this, it could lead to wasted time
                    # and misleading test results.
                    elif d == ' ':

                        diag = "signal: " + sig + ", offset=" + str(i)
                        raise Exception, \
                        "Spaces are not allowed under edge markers " + diag

                    else:
                        # Treat this char that's under the edge marker
                        # as the start of a data value string
                        #
                        # We need to parse the data string until we reach
                        # whitespace or the next edge marker.
                        #                               
                        # grab the next chars until we hit whitespace or the
                        # next edge marker.
                        #
                        # Start at the char 'under' the current edge marker.

                        # TODO: Stop if we hit the next edge marker        

                        n = 0
                        dstr = ""
                        while d != ' ':
                            d = vts[sig][i+n]
                            dstr += d
                            n += 1

                        # convert to an int.
                        # The (required) trailing whitespace is ok.

                        # Hex
                        if   dstr[:2] == "0x":
                            data = int(dstr[2:],16)   

                        # Binary
                        elif dstr[:2] == "0b":
                            data = int(dstr[2:], 2)

                        # Decimal
                        else:
                            data = int(dstr)

                # Add the data item to the appropriate signal's list.       
                cts[sig].append(data)

                   
    if print_cts:

        print "cts: "

        import pprint
        print pprint.pprint(cts) 

          
    return cts   

# ----------------------------------------------------------------------------

def drive_signals_from_cts(sigs, cts):
    """
    drive_signals_from_cts() - unit test tool for MyHDL

    Given a Condensed Timing Spec object, drive the signals according to
    that specification. See the Visual Timing Spec parser doc.

    The signal dictionary must contain a 'clk' signal
    """

    __author__   = "George Pantazopoulos http://www.gammaburst.net"
    __revision__ = ""
    __date__     = "2 Oct 2006"
    __version__  = "0.1.0"
    __requires__ = ('myhdl', '>= 0.5.1')

    if 'clk' not in sigs:
        raise Exception, \
        "signal dictionary 'sigs' must contain a 'clk' signal"

    clk = sigs['clk']

    for i in range(len(cts['edges'])):

	if 1==cts['edges'][i][1]:
        	# Setup for positive edge i

        	# Drive each signal with the correct value for
        	# the upcoming positive edge i
        	for sig in cts:
            		value = cts[sig][i]
            		if sig != 'edges':
				if value != ' ':
                    			sigs[sig].next = value

        	# positive edge i
        	yield clk.posedge
	if 0==cts['edges'][i][1]:
        	# Setup for negative edge i

        	# Drive each signal with the correct value for
        	# the upcoming positive edge i
        	for sig in cts:
            		value = cts[sig][i]
            		if sig != 'edges':
				if value != ' ':
                    			sigs[sig].next = value


        	# negative edge i
        	yield clk.negedge

# ----------------------------------------------------------------------------

def check_signals_against_cts(sigs, cts):
    """
    check_signals_against_cts() - unit test tool for MyHDL

    Given a Condensed Timing Spec object, ensure the signals match
    that specification. See the Visual Timing Spec parser doc.

    The signal dictionary must contain a 'clk' signal
    """      

    __author__   = "George Pantazopoulos http://www.gammaburst.net"
    __revision__ = ""
    __date__     = "2 Oct 2006"
    __version__  = "0.1.0"
    __requires__ = ('myhdl', '>= 0.5.1')

    if 'clk' not in sigs:
        raise Exception, \
        "signal dictionary 'sigs' must contain a 'clk' signal"

    clk = sigs['clk']

            
    for i in range(len(cts['edges'])):

        # Setup for edge i
        if 1==cts['edges'][i][1]:
            # Edge i
            yield clk.posedge
	else:
	    yield clk.negedge

        # Check the outputs that should have been valid by
        # the time this edge comes around
        for sig in cts:

            value = cts[sig][i]

            if sig != 'edges':

                # Skip this for 'don't-care' values
                if value != ' ':

                    # If the signal is not the value it should have been
                    if sigs[sig] != value:

                        # Raise an exception and show some helpful info.
                        info = "Edge #" + str(i) + \
                               " Signal \'" + sig + "\'" + \
                               " = "  + str(sigs[sig]) + \
                               ". Correct value = " + str(value)
                        raise Exception, info         

        #yield clk.negedge

         
    raise StopSimulation()

# ----------------------------------------------------------------------------

def up_counter(sigs):

    # Unbundle needed signals. Name them from the perspective of this module.
    clk_i    = sigs['clk']
    rst_i    = sigs['rst']

    count_o  = sigs['count']   
    enable_i = sigs['count_en']

    @always(clk_i.posedge)
    def count_proc():

        if rst_i:
            count_o.next = 0

        else:
            if enable_i:
                count_o.next = (count_o + 1) % 2**len(count_o)

    return instances()

# ----------------------------------------------------------------------------

def up_counter_bench():

    # Embedded function definition for clock generator
    def clkgen(clk):

        while True:
            yield delay(10)
            clk.next = not clk

    # Shared clk signal
    clk = Signal(bool(0))

    # Create the signal group for the counter
    counter_sigs=dict(clk      = clk,
                      rst      = Signal(bool(0)),
                      count    = Signal(intbv(0)[4:]),
                      count_en = Signal(bool(0)))

    # Instantiate a clock generator and connect to the shared clock
    clkgen_inst = clkgen(clk)

    dut = up_counter(counter_sigs)

    # Visual Timing Specification
    # ---------------------------

    signals_to_drive = dict(
    edges      = "|0....|1..^..|2....|3....|4....|5....|6....",
    rst        = "--------------_____________________________",
    count_en   = "___________________------------------------")

    correct_outputs = dict(
    edges      = "|0....|1..^..|2....|3....|4....|5....|6....",
    count      = "X     0   0  0     0     1     2     3     ")

    # Signal driver
    driver = drive_signals_from_cts(

            sigs = counter_sigs,
            cts  = visual_timing_spec_parse(signals_to_drive)
            )

    # Signal monitor
    monitor = check_signals_against_cts(

            sigs = counter_sigs,
            cts  = visual_timing_spec_parse(correct_outputs)
            )   

    return instances()

# ----------------------------------------------------------------------------

if __name__ == '__main__':
    def test_up_counter():
        tb = up_counter_bench()
        sim = Simulation(tb)
        sim.run()

    test_up_counter()

# - End code ---------------------------------------------------------------

Re: [myhdl-list] Reflections on a MyHDL IP library

[Brendan R. <bre...@gm...>]

dannoritzer <dannoritzer <at> web.de> writes:

> 
> Brendan Rankin wrote:
> > 
> > I'm definitely not a fan of Zope and, through relation, Plone.
> > It's just too complex.
> > There are a few new python-based CMSs, however, and of these I think
> > that skeletonz (http://orangoo.com/skeletonz/) looks pretty promising,
> > though there's bound to be one for Turbogears or Django as well.
> 
> How would you compare Skeletonz, TurboGears, and Django in terms of how
> much development has been done to it? I got the feeling that Django
> exists already for quite some time, where as TurboGears and Skeletonz
> are newer, but there seems to be quite some activity in development
> going on with the two later ones?
> 
> Cheers,
> 
> Guenter
> 

Guenter,

Sorry for the long delay in responding...vacation is bliss!

You can't directly compare Skeletonz, TG, and Django as Skeletonz is 
more of a complete CMS, whereas the latter two are web frameworks 
(lower level stuff).  In terms of maturity, Django is the most mature, 
with TG right behind it and Skeletonz trailing.  That being said, 
I think that Skeletonz is more pythonic and adheres to my favorite KISS 
(keep it simple stupid) principle.  I'll be developing 1-2 websites with
Skeletonz, in the next month or so, and will have a better idea of its
capabilities following that.

Cheers, and Happy New Year!

- Brendan

Re: [myhdl-list] Python 2.5 released!

[<dan...@we...>]

Jan Decaluwe wrote:
> 
> I have upgraded in the mean time and I remember there was a small issue with
> Verilog conversion, revealed by those specific unit tests. It has been
> addressed in the 0.6 dev version.
> 
> Jan
> 

Hi Jan,

I recognized I did not run those tests.

I started creating a rpm for suse, but just added the plain installation
yet. I would like to add the cosimulation for at least icarus to it. So
that cosimulation works when icarus is installed.

Need to figure out how to do that with rpm installation. One way is to
compile it and just add it with the installation, but then it would be
fixed to suse and a specific icarus version. If the rpm installation
process would include the possibility to compile it when installing, it
could be made flexible to the existing system.

Cheers and Happy New Year,

Guenter

Re: [myhdl-list] Python 2.5 released!

[<dan...@we...>]

George Pantazopoulos wrote:
> Hi Guenter,
> 
>     Over the past 3 years, I've run RedHat, Gentoo, and Debian (in that 
> order). I thought Linux actually was nice for developing (once you get 
> it set up), but I didn't like it as a general desktop. And installing a 
> new video card or other hardware was often way too much of a pain and 
> interrupted my flow. Too much learning and tinkering needed IMHO. I've 
> been there, done that. I want my computer to 'just work' so I can create 
> new things now.
> 

Hi George,

Yes, I understand that. There is a steep learning curve with Linux and
with some hardware it can become a nightmare.

>     Sadly, Windows has a leg up on Linux in that respect. I've found a 
> nice working balance using Windows XP and cygwin together. Not sure 
> where the FPGA software stands, but ultimately, I think, I want a Mac 
> (::drool::).

I feel like the 3D desktop is one place where Linux is advanced over
Windows. Suse 10.2 started using that http://de.wikipedia.org/wiki/Xgl.
Though, as you said, getting the hardware to go if it is not supported
adds some extra work. Sounds like the Mac also has already something
like that.



> I've done dual-boot and I think that's a good idea in general. Something 
> I'd rather do now is run Linux and Windows side-by-side AND be able to 
> copy/paste stuff across the divide... got any ideas for that? VMWare?
> 

On my Windows partition I am also using cygwin. I ran across something
called coLinux http://www.colinux.org/ I haven't tried it, but it seems
to be a way to run Linux under Windows.

The other way around is XEN under Linux, which is an open source version
of VMWare, though I wonder how good it will be in running Windows.

Do you really need to run it side-by-side or just have access to data
from both domains?

I am using an extra ext3 partition for that. There is a driver under
Windows to access ext3 partitions and so I put all my data and emails on
that partition. Using Thunderbird as email client I am able to have
access to the emails from both domains.

Cheers and Happy New Year,

Guenter

Re: [myhdl-list] Python 2.5 released!

[Jan D. <ja...@ja...>]

George Pantazopoulos wrote:

> 
>     Over the past 3 years, I've run RedHat, Gentoo, and Debian (in that 
> order). I thought Linux actually was nice for developing (once you get 
> it set up), but I didn't like it as a general desktop. And installing a 
> new video card or other hardware was often way too much of a pain and 
> interrupted my flow.

Actually, I have just been off-line for a few days because of that.
I recently decided to upgrade from RH9 to Fedora 6. Everything went OK,
except for my Linksys wireless usb adapter. I had had problems with it on
RH9, but had been able to fix them. I figured that by now usb support
would be transparant ... It actually is much better for usb storage keys,
but for the Linksys product, things have apparently worsened. I finally got
fed up and gave up, and went to a shop for the "obvious" solution (to me):
an wireless ethernet adapter ... except they didn't have such a thing
(only usb gear, often with "Windows only" warnings.)

But I found a different solution: I bought 2 Netgear "wall-plugged"
ethernet bridges. So I'm now using the electrical power network in
my house as an ethernet connection between my desktop and my
Internet router. Seems to work great! And also faster & more reliable
than my previous wireless connection.

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
     From Python to silicon:
     http://myhdl.jandecaluwe.com

Re: [myhdl-list] Python 2.5 released!

[Jan D. <ja...@ja...>]

Günter Dannoritzer wrote:
> Jan Decaluwe wrote:
> 
>>George Pantazopoulos wrote:
>>
>>>A brand new version of my favorite programming language is out, Python 2.5:
>>
>>Right. Many new/changed features. If someone can checks whether
>>nothing breaks in MyHDL with 2.5, that would be nice.
> 
> 
> This is an old post and I don't know whether I overlooked that someone
> confirmed this already. Just want to say that I installed 0.5.1 under
> Python 2.5 and running the test_all.py in the myhdl/test folder worked
> out fine.

I have upgraded in the mean time and I remember there was a small issue with
Verilog conversion, revealed by those specific unit tests. It has been
addressed in the 0.6 dev version.

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
     From Python to silicon:
     http://myhdl.jandecaluwe.com

Re: [myhdl-list] Python 2.5 released!

[George P. <ge...@ga...>]

>> s Guenter, I appreciate that! Now if only cygwin would finally 
>> upgrade to 2.5... :-)
>>     
>
> I remember in an earlier post you wrote that you had tried Linux before.
> Did you have so bad experience with it?
>
>   
Hi Guenter,

    Over the past 3 years, I've run RedHat, Gentoo, and Debian (in that 
order). I thought Linux actually was nice for developing (once you get 
it set up), but I didn't like it as a general desktop. And installing a 
new video card or other hardware was often way too much of a pain and 
interrupted my flow. Too much learning and tinkering needed IMHO. I've 
been there, done that. I want my computer to 'just work' so I can create 
new things now.

    Sadly, Windows has a leg up on Linux in that respect. I've found a 
nice working balance using Windows XP and cygwin together. Not sure 
where the FPGA software stands, but ultimately, I think, I want a Mac 
(::drool::).

    Also, I use Eclipse with PyDev and PyDev Extensions (I paid for 
those). Best IDE I've ever used, it ROCKS for Python!
> I have my laptop as a dual boot system. So I have Windows and Linux on
> it. I upgraded my openSuse from 10.1 to 10.2 now. The way I do it is
> that I have an exact second hard drive as the one in the laptop and I
> hook that up as a USB drive. Then I clone my hard drive and do the
> update. That way I always have a fall back position if something goes
> wrong with the update.
>
>   
I've done dual-boot and I think that's a good idea in general. Something 
I'd rather do now is run Linux and Windows side-by-side AND be able to 
copy/paste stuff across the divide... got any ideas for that? VMWare?

> But openSuse has Python 2.5 also only with the latest 10.2 release,
> which came out a few weeks ago. So you might find it soon with cygwin too.
>   
Nice! Can't wait. But, as I jump on this bandwagon I remind myself that 
Python 3K looms over the horizon.. what's a guy to do? :-)

Rock on,
George

Re: [myhdl-list] Python 2.5 released!

[<dan...@we...>]

George Pantazopoulos wrote:

> Thanks Guenter, I appreciate that! Now if only cygwin would finally 
> upgrade to 2.5... :-)

I remember in an earlier post you wrote that you had tried Linux before.
Did you have so bad experience with it?

I have my laptop as a dual boot system. So I have Windows and Linux on
it. I upgraded my openSuse from 10.1 to 10.2 now. The way I do it is
that I have an exact second hard drive as the one in the laptop and I
hook that up as a USB drive. Then I clone my hard drive and do the
update. That way I always have a fall back position if something goes
wrong with the update.

But openSuse has Python 2.5 also only with the latest 10.2 release,
which came out a few weeks ago. So you might find it soon with cygwin too.

Cheers,

Guenter

Re: [myhdl-list] Python 2.5 released!

[George P. <ge...@ga...>]

Günter Dannoritzer wrote:
> Jan Decaluwe wrote:
>   
>> George Pantazopoulos wrote:
>>     
>>> A brand new version of my favorite programming language is out, Python 2.5:
>>>       
>> Right. Many new/changed features. If someone can checks whether
>> nothing breaks in MyHDL with 2.5, that would be nice.
>>     
>
> This is an old post and I don't know whether I overlooked that someone
> confirmed this already. Just want to say that I installed 0.5.1 under
> Python 2.5 and running the test_all.py in the myhdl/test folder worked
> out fine.
>
> Cheers,
>
> Guenter
>   
Thanks Guenter, I appreciate that! Now if only cygwin would finally 
upgrade to 2.5... :-)

George

Re: [myhdl-list] Python 2.5 released!

[<dan...@we...>]

Jan Decaluwe wrote:
> George Pantazopoulos wrote:
>> A brand new version of my favorite programming language is out, Python 2.5:
> 
> Right. Many new/changed features. If someone can checks whether
> nothing breaks in MyHDL with 2.5, that would be nice.

This is an old post and I don't know whether I overlooked that someone
confirmed this already. Just want to say that I installed 0.5.1 under
Python 2.5 and running the test_all.py in the myhdl/test folder worked
out fine.

Cheers,

Guenter

Re: [myhdl-list] Reflections on a MyHDL IP library

[dannoritzer <dan...@we...>]

Brendan Rankin wrote:
> 
> I'm definitely not a fan of Zope and, through relation, Plone.  It's just too
> complex.  There are a few new python-based CMSs, however, and of these I think
> that skeletonz (http://orangoo.com/skeletonz/) looks pretty promising, though
> there's bound to be one for Turbogears or Django as well.

How would you compare Skeletonz, TurboGears, and Django in terms of how
much development has been done to it? I got the feeling that Django
exists already for quite some time, where as TurboGears and Skeletonz
are newer, but there seems to be quite some activity in development
going on with the two later ones?

Cheers,

Guenter

Re: [myhdl-list] Reflections on a MyHDL IP library

[dannoritzer <dan...@we...>]

George Pantazopoulos wrote:
> 
> Here's the site.
> http://www.webfaction.com/

I looked on that page and saw that they also host TurboGears and Django
pages. Have you looked in any of those?

There is a page about all kind of python web frameworks available:

  http://wiki.python.org/moin/WebFrameworks

TurboGears looks pretty slick, I watched a movie done by the creator.
But it seems like there is more work necessary to just get the basic
page going, what in contrast is already provided by Plone.

BTW, there is a book about Plone available online:

  http://docs.neuroinf.de/PloneBook/


Cheers,

Guenter

Re: [myhdl-list] Reflections on a MyHDL IP library

[George P. <ge...@ga...>]

Jan Decaluwe wrote:
> George Pantazopoulos wrote:
>
>   
>> Desired Features (so far):
>> --------------------------
>>
>> * Version control for IP
>>     
>
> All your other points have to do with documentation,
> and I agree with all of them.
>
> But this one is about (open-source) development. What
> do you see as the value of hosting that ourselves, as opposed to
> simply opening a project in sourceforge or google code
> or perhaps others?
>
>   
Hi Jan,

 I didn't necessarily mean that we had to host it ourselves, just that 
we need it somehow. I think writing down our requirements, even if 
they're obvious can help us see the big picture better. I think it's 
best at this stage to focus on what we need and not on how we're to get 
it (that comes later).

Regards,
George


>> * Easily editable web content (no HTML required)
>> * Versioned web content (as in Wiki's)
>> * LaTeX support would be nice (for light use of equations).
>> * Ability to seamlessly integrate links to member pages (and/or host 
>> member sites)
>> * Ability to do Wiki-style pages and not just blog posts.
>>     
>
>   

Re: [myhdl-list] Reflections on a MyHDL IP library

[Jan D. <ja...@ja...>]

George Pantazopoulos wrote:

> 
> Desired Features (so far):
> --------------------------
> 
> * Version control for IP

All your other points have to do with documentation,
and I agree with all of them.

But this one is about (open-source) development. What
do you see as the value of hosting that ourselves, as opposed to
simply opening a project in sourceforge or google code
or perhaps others?

> * Easily editable web content (no HTML required)
> * Versioned web content (as in Wiki's)
> * LaTeX support would be nice (for light use of equations).
> * Ability to seamlessly integrate links to member pages (and/or host 
> member sites)
> * Ability to do Wiki-style pages and not just blog posts.

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
     From Python to silicon:
     http://myhdl.jandecaluwe.com

Re: [myhdl-list] Reflections on a MyHDL IP library

[George P. <ge...@ga...>]

Tom Dillon wrote:
> On Thursday 14 December 2006 07:53, George Pantazopoulos wrote:
>   
>> FYI I just found a python-oriented hosting provider that already has
>> Zope AND Plone installed and ready to create websites on. I was really
>> impressed by their features, and I signed up for month to month, so all
>> I risk is $34.95 right now. Haven't set it up just yet, but I'll let you
>> all know how it goes.
>>
>> Another interesting tidbit from their site:
>> "As both python and open-source lovers we're happy to offer free
>> trac/subversion hosting for open-source python projects. We already host
>> more than 400 of them."
>>     
>
> We have offered to host the myhdl.org site on our servers. We have plone, 
> subversion, and trac all running. Trac and subversion at this point are only 
> used internally, but those could be extended for public access.
>
> I would recommend making sure plone is not overkill for this site. Again think 
> we should come up with a list of features required, and find the simplest 
> solution as nobody wants to spend more time on web development than they need 
> to.
>
> Tom
>   
Hi Tom, I agree wholeheartedly on putting together a list of features 
for myhdl.org. I'm grateful that you've offered all those features. I 
bought a hosting plan because I have substantial needs for my own 
website, which is not directly related to myhdl.org. What is your site?

Desired Features (so far):
--------------------------

* Version control for IP
* Easily editable web content (no HTML required)
* Versioned web content (as in Wiki's)
* LaTeX support would be nice (for light use of equations).
* Ability to seamlessly integrate links to member pages (and/or host 
member sites)
* Ability to do Wiki-style pages and not just blog posts.

Rock on,
George

Re: [myhdl-list] Reflections on a MyHDL IP library

[Tom D. <TD...@di...>]

On Thursday 14 December 2006 07:53, George Pantazopoulos wrote:
> FYI I just found a python-oriented hosting provider that already has
> Zope AND Plone installed and ready to create websites on. I was really
> impressed by their features, and I signed up for month to month, so all
> I risk is $34.95 right now. Haven't set it up just yet, but I'll let you
> all know how it goes.
>
> Another interesting tidbit from their site:
> "As both python and open-source lovers we're happy to offer free
> trac/subversion hosting for open-source python projects. We already host
> more than 400 of them."

We have offered to host the myhdl.org site on our servers. We have plone, 
subversion, and trac all running. Trac and subversion at this point are only 
used internally, but those could be extended for public access.

I would recommend making sure plone is not overkill for this site. Again think 
we should come up with a list of features required, and find the simplest 
solution as nobody wants to spend more time on web development than they need 
to.

Tom

Re: [myhdl-list] Reflections on a MyHDL IP library

[George P. <ge...@ga...>]

dannoritzer wrote:
> George Pantazopoulos wrote:
>
>   
>>>   
>>>       
>> FYI I just found a python-oriented hosting provider that already has 
>> Zope AND Plone installed and ready to create websites on. I was really 
>> impressed by their features, and I signed up for month to month, so all 
>> I risk is $34.95 right now. Haven't set it up just yet, but I'll let you 
>> all know how it goes.
>>     
>
> You should spend that money on a hard drive and install Linux on it ;)
> Most distributions come at least with zope and you can install plone on
> top of that.
>
> But hey, what am I saying, there used to be a windows installer for
> plone. Might be another way for testing.
>
> Guenter
>   
Been there, done that (Gentoo and Ubuntu), too busy to deal with all 
that right now. I want it to Just Work(tm) ;-)

George

Re: [myhdl-list] Reflections on a MyHDL IP library

[dannoritzer <dan...@we...>]

George Pantazopoulos wrote:

>>
>>   
> FYI I just found a python-oriented hosting provider that already has 
> Zope AND Plone installed and ready to create websites on. I was really 
> impressed by their features, and I signed up for month to month, so all 
> I risk is $34.95 right now. Haven't set it up just yet, but I'll let you 
> all know how it goes.

You should spend that money on a hard drive and install Linux on it ;)
Most distributions come at least with zope and you can install plone on
top of that.

But hey, what am I saying, there used to be a windows installer for
plone. Might be another way for testing.

Guenter

Re: [myhdl-list] Reflections on a MyHDL IP library

[George P. <ge...@ga...>]

Tom Dillon wrote:
>> Mm, but have you ever used it :-) Several year ago, I have a number of
>> times, and never really liked it. I found if very complicated and full of
>> jargon. Also, it has something unpythonic: it's large, not orthogonal and
>> complex. It was supposed to become the Python killer app, but from what I
>> hear many pythonistas simply don't like it.
>>
>> I never used Plone, but I imagine it has been invented to take away
>> some complexity from the underlying Zope to make a more usable system.
>> Still, I fear that the underlying complexity still shines through.
>> Tom is using it for his site, so he may give good advice here.
>>
>>     
>
> I agree it is complicated. Newer versions of plone keep you further away from 
> zope but there is still more to know than  you would like to. I had to buy a 
> book to help me understand how to use it.
>
> On the other hand, it provides a lot. All the site structure is just there. 
> There are add on products for just about anything you could need, including a 
> wiki.
>
> All in all, it is probably overkill for a small site, if something easier to 
> use was available that provided all the features required for the site that 
> would be a better option.
>
> Maybe the thing to do is so compile a list of features needed to properly host 
> the site.
>
> Tom
>
>   
FYI I just found a python-oriented hosting provider that already has 
Zope AND Plone installed and ready to create websites on. I was really 
impressed by their features, and I signed up for month to month, so all 
I risk is $34.95 right now. Haven't set it up just yet, but I'll let you 
all know how it goes.

Another interesting tidbit from their site:
"As both python and open-source lovers we're happy to offer free 
trac/subversion hosting for open-source python projects. We already host 
more than 400 of them."

Here's the site.
http://www.webfaction.com/

Rock on,
George

Re: [myhdl-list] Reflections on a MyHDL IP library

[Tom D. <TD...@di...>]

> Mm, but have you ever used it :-) Several year ago, I have a number of
> times, and never really liked it. I found if very complicated and full of
> jargon. Also, it has something unpythonic: it's large, not orthogonal and
> complex. It was supposed to become the Python killer app, but from what I
> hear many pythonistas simply don't like it.
>
> I never used Plone, but I imagine it has been invented to take away
> some complexity from the underlying Zope to make a more usable system.
> Still, I fear that the underlying complexity still shines through.
> Tom is using it for his site, so he may give good advice here.
>

I agree it is complicated. Newer versions of plone keep you further away from 
zope but there is still more to know than  you would like to. I had to buy a 
book to help me understand how to use it.

On the other hand, it provides a lot. All the site structure is just there. 
There are add on products for just about anything you could need, including a 
wiki.

All in all, it is probably overkill for a small site, if something easier to 
use was available that provided all the features required for the site that 
would be a better option.

Maybe the thing to do is so compile a list of features needed to properly host 
the site.

Tom