myhdl-list — Mailing list for discussions on MyHDL

Re: [myhdl-list] Strange problem, VALUES instead of symbols being toVerilog'ed

[Jan D. <ja...@ja...>]

Oystein Homelien wrote:
> On Wed, 7 May 2008, Jan Decaluwe wrote:
> 
> 
>>I'm trying to understand your example:
> 
> 
> Thanks for the quick reply!  I really appreciate it.  Was a little scared 
> since there has been little activity on the list..
> 
> 
>>- I see that wb is passed as a parameter, but also returned by the
>>module. Why is that necessary?
> 
> 
> I return wb to avoid an extra line in the main module, "powersoc";
> 
>      i_uart, wb_uart = uart.uart(wb.slave(0xC), baudclk, rxd, txd) # moving 
> this up fixed stuff

Ok, this is the problem. When, in the uart, you say:

     return (registers, transmitter), wb

the result is no longer a "sequence of generators". MyHDL uses this to decide whether
or not the function represents hardware or not. The problem is that the uart is
silently ignored during hierarchy extraction.

Workaround:

in uart.py:
     return (registers, transmitter)

in powersoc:
     wb_uart = wb.slave(0xC)
     i_uart  = uart.uart(wb_uart, baudclk, rxd, txd) # moving this up fixed stuff

To solve the problem fundamentally, there are some options. MyHDL could give
an error if a sequence of generators contains other things. Probably we should
limit this to special kinds of hardware-oriented generators, the ones created
by MyHDL decorators. Or MyHDL could "filter" return values and throw out
what it doesn't like. I think I prefer the first option.

Jan



-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Kaboutermansstraat 97, B-3000 Leuven, Belgium
     From Python to silicon:
     http://myhdl.jandecaluwe.com

Re: [myhdl-list] Strange problem, VALUES instead of symbols being toVerilog'ed

[Oystein H. <oy...@ho...>]

On Wed, 7 May 2008, Jan Decaluwe wrote:

> I'm trying to understand your example:

Thanks for the quick reply!  I really appreciate it.  Was a little scared 
since there has been little activity on the list..

> - I see that wb is passed as a parameter, but also returned by the
> module. Why is that necessary?

I return wb to avoid an extra line in the main module, "powersoc";

     i_uart, wb_uart = uart.uart(wb.slave(0xC), baudclk, rxd, txd) # moving 
this up fixed stuff

wb.slave() is supposed to set up a slave wishbone instance with chip 
select for the given major nibble, and for all modules I return the 
wishbone bus as well as the instance itself so I can avoid typing:

 	wb_uart = wb.slave(0x0C)
 	iuart = uart.uart(wb_uart, ...)

It just seems clearer to me, but opinions may differ.  Could this be the 
problem, if I just skip returning it then it will work?  Then why does it 
work for all the other slaves:

     i_rom, wb_rom = zpu.rom(wb.slave(0x0))
     i_bram, wb_bram = hw.sram(wb.slave(0xF), sram)
     i_debugreg, wb_debugreg = hw.debugreg(wb.slave(0xE), debugreg);

.. as expected (i think)?  The design, prior to adding the uart, converts 
and synthesizes.

> - what is wb? if it's a class instance, as suggested by the code, I don't
> understand how you get to converted code at all. I tried it, and toVerilog
> chokes on return values that are not generators or sequences of generators.
> Did you perhaps modify some of the code in _extractHierarchy.py?

It's a class instance so that I can avoid typing all the signal names 
every time I change parts of the bus (see hw.py in my example).  I find it 
gives much clearer code to be able to pass class instances like this, the 
only annoyance is that myhdl barfs on them during conversion so I have to 
"explode" the buses in the top of the instance functions:

     wb_rst_i, wb_clk_i, wb_adr_i, wb_dat_o, wb_dat_i, wb_we_i, wb_sel_i, wb_stb_i, wb_ack_o, wb_cyc_i
  =  wb.rst_i, wb.clk_i, wb.adr_i, wb.dat_o, wb.dat_i, wb.we_i, wb.sel_i, wb.stb_i, wb.ack_o, wb.cyc_i

I basically replace "." by "_".  Is it possible MyHDL (convertible) might 
support this usage pattern (without having to "explode" the buses) in the 
future?  I tried having a look at the code but it made little sense to me.
It is just for grouping of signals.

Regarding whether I modified myhdl, Yes I did try to remove an assertion 
but nothing more.  If you try my design ("python powersoc") on various 
versions of myhdl you will see that it usually converts, but some versions 
barf with an assertion on curlevel < -1 or something like that.

Sorry for not being more presice, I will look further into this when I get 
home, just wanted to get your reactions on my thoughts above.

And thank you _very much_ for making MyHDL.  I simply love it!


Oystein Homelien, CVO             |  oy...@po...
PowerTech Information Systems AS  |  http://www.powertech.no/
Nedre Slottsgate 5, N-0157 OSLO   |  tel: +47-2301-0010, fax: +47-2301-0001

Re: [myhdl-list] Strange problem, VALUES instead of symbols being toVerilog'ed

[Blubaugh, D. A. <dbl...@be...>]

I am glad to see that there is still development for MyHDL.  I was
concerned that development had expired, since I was not seeing any new
messages being posted on the MyHDL website.  I was also wondering if it
would one day be possible if MyHDL would be a timeless Python, where all
the necessary timing issues would be automatically be handled by MyHDL
generator.  

Thanks,

David Blubaugh




 

-----Original Message-----
From: myh...@li...
[mailto:myh...@li...] On Behalf Of Jan
Decaluwe
Sent: Wednesday, May 07, 2008 10:36 AM
To: myh...@li...
Subject: Re: [myhdl-list] Strange problem,VALUES instead of symbols
being toVerilog'ed

I'm trying to understand your example:

- I see that wb is passed as a parameter, but also returned by the
module. Why is that necessary?

- what is wb? if it's a class instance, as suggested by the code, I
don't understand how you get to converted code at all. I tried it, and
toVerilog chokes on return values that are not generators or sequences
of generators.
Did you perhaps modify some of the code in _extractHierarchy.py?

Jan

Oystein Homelien wrote:
> Hello, this is my first post although I have lurked for some time.  
> First of all let me say that I simply love the idea of MyHDL.  The 
> simplicity and power of python, direct to synthesizable verilog code..
yummie!
> 
> Second I must admit that I am a newbie, so be nice with me.  I have 
> done some stuff with MyHDL and stumbled upon some of its (or 
> verilog's?) limitations wrt verilog conversion.  So far I have been 
> able to work around all of them, but now I am stuck.
> 
> I am adding a myhdl "uart" module to my project.  The instance is in 
> the file uart.py, def uart().  Here's the start of it:
> 
> def uart(wb, baudclk, rxd, txd):
>      wb_rst_i, wb_clk_i, wb_adr_i, wb_dat_o, wb_dat_i, wb_we_i,
wb_sel_i, wb_stb_i, wb_ack_o, wb_cyc_i
>   =  wb.rst_i, wb.clk_i, wb.adr_i, wb.dat_o, wb.dat_i, wb.we_i, 
> wb.sel_i, wb.stb_i, wb.ack_o, wb.cyc_i ;
>      char = Signal(bool(0));
>      send = Signal(bool(0));
>      sending = Signal(bool(0));
>      send_done = Signal(bool(0));
> 
>      @always(wb_clk_i.posedge)
>      def registers():
>          wb_ack_o.next = False
>          if wb_cyc_i:
>              if wb_we_i:
>                  char.next = wb_dat_i
>                  send.next = True
>              else:
>                  wb_dat_o.next = concat(intbv(0x11)[5:], rxd, send,
sending)
>              wb_ack_o.next = True
> 
> .. as you can see I am "exploding" a wishbone bus in the beginning, 
> and then declaring some internal registers (at least this is what I am

> trying to do).  But, registers() is converted into the following
verilog:
> 
> always @(posedge wb_clk_i) begin: POWERSOC_I_UART_0
>      uart_ack_o <= 0;
>      if (uart_cyc_i) begin
>          if (wb_we_o) begin
>              False <= wb_dat_o;     <-- LOOK HERE
>              False <= 1;            <-- AND HERE
>          end
>          else begin
>              uart_dat_o <= {5'h11, rxd, False, False};  <-- AND HERE
>          end
>          uart_ack_o <= 1;
>      end
> end
> 
> .. it seems as though the _values_ of my vars are being written to 
> verilog instead of the symbol names.  What am I doing wrong?  It only 
> happens with the uart, and I have tried all kinds of strange things to

> make it work. Of course this does not synthesize (i use Xilinx' 
> tools).  :-)
> 
> I have put a zip file with design files for you to try yourself 
> (./powersoc), at http://home.powertech.no/oystein/myhdl-bug1.zip .
> 
> For the record, I have tried it with the following myhdl versions:
> 
> drwxr-xr-x 8 oystein oystein   4096 2008-05-07 12:51 myhdl-0.5.1dev1
> -rw-r--r-- 1 oystein oystein 768032 2008-05-07 12:50
myhdl-0.5.1dev1.tar.gz
> drwxr-xr-x 7 oystein oystein   4096 2008-05-07 12:48 myhdl-0.5c1
> -rw-r--r-- 1 oystein oystein 760268 2008-05-07 12:47
myhdl-0.5c1.tar.gz
> drwxr-xr-x 6 oystein oystein   4096 2008-05-07 12:47 myhdl-0.6dev6
> -rw-r--r-- 1 oystein oystein 156404 2008-05-07 12:46
myhdl-0.6dev6.tar.gz
> drwxr-xr-x 6 oystein oystein   4096 2008-05-07 10:24 myhdl-0.6dev8
> -rw-r--r-- 1 oystein oystein 181734 2008-05-07 10:23 
> myhdl-0.6dev8.tar.gz
> 
> .. i could not get it working.  Hope to get some input on how to work 
> around this.
> 
> yours,
> oystein
> 
> 
> ----------------------------------------------------------------------
> --- This SF.net email is sponsored by the 2008 JavaOne(SM) Conference 
> Don't miss this year's exciting event. There's still time to save
$100.
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> /javaone


--
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Kaboutermansstraat 97, B-3000 Leuven, Belgium
     From Python to silicon:
     http://myhdl.jandecaluwe.com


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Re: [myhdl-list] Strange problem, VALUES instead of symbols being toVerilog'ed

[Jan D. <ja...@ja...>]

I'm trying to understand your example:

- I see that wb is passed as a parameter, but also returned by the
module. Why is that necessary?

- what is wb? if it's a class instance, as suggested by the code, I don't
understand how you get to converted code at all. I tried it, and toVerilog
chokes on return values that are not generators or sequences of generators.
Did you perhaps modify some of the code in _extractHierarchy.py?

Jan

Oystein Homelien wrote:
> Hello, this is my first post although I have lurked for some time.  First 
> of all let me say that I simply love the idea of MyHDL.  The simplicity 
> and power of python, direct to synthesizable verilog code..  yummie!
> 
> Second I must admit that I am a newbie, so be nice with me.  I have done 
> some stuff with MyHDL and stumbled upon some of its (or verilog's?) 
> limitations wrt verilog conversion.  So far I have been able to work 
> around all of them, but now I am stuck.
> 
> I am adding a myhdl "uart" module to my project.  The instance is in the 
> file uart.py, def uart().  Here's the start of it:
> 
> def uart(wb, baudclk, rxd, txd):
>      wb_rst_i, wb_clk_i, wb_adr_i, wb_dat_o, wb_dat_i, wb_we_i, wb_sel_i, wb_stb_i, wb_ack_o, wb_cyc_i
>   =  wb.rst_i, wb.clk_i, wb.adr_i, wb.dat_o, wb.dat_i, wb.we_i, wb.sel_i, wb.stb_i, wb.ack_o, wb.cyc_i
> ;
>      char = Signal(bool(0));
>      send = Signal(bool(0));
>      sending = Signal(bool(0));
>      send_done = Signal(bool(0));
> 
>      @always(wb_clk_i.posedge)
>      def registers():
>          wb_ack_o.next = False
>          if wb_cyc_i:
>              if wb_we_i:
>                  char.next = wb_dat_i
>                  send.next = True
>              else:
>                  wb_dat_o.next = concat(intbv(0x11)[5:], rxd, send, sending)
>              wb_ack_o.next = True
> 
> .. as you can see I am "exploding" a wishbone bus in the beginning, and 
> then declaring some internal registers (at least this is what I am trying 
> to do).  But, registers() is converted into the following verilog:
> 
> always @(posedge wb_clk_i) begin: POWERSOC_I_UART_0
>      uart_ack_o <= 0;
>      if (uart_cyc_i) begin
>          if (wb_we_o) begin
>              False <= wb_dat_o;     <-- LOOK HERE
>              False <= 1;            <-- AND HERE
>          end
>          else begin
>              uart_dat_o <= {5'h11, rxd, False, False};  <-- AND HERE
>          end
>          uart_ack_o <= 1;
>      end
> end
> 
> .. it seems as though the _values_ of my vars are being written to verilog 
> instead of the symbol names.  What am I doing wrong?  It only happens with 
> the uart, and I have tried all kinds of strange things to make it work. Of 
> course this does not synthesize (i use Xilinx' tools).  :-)
> 
> I have put a zip file with design files for you to try yourself 
> (./powersoc), at http://home.powertech.no/oystein/myhdl-bug1.zip .
> 
> For the record, I have tried it with the following myhdl versions:
> 
> drwxr-xr-x 8 oystein oystein   4096 2008-05-07 12:51 myhdl-0.5.1dev1
> -rw-r--r-- 1 oystein oystein 768032 2008-05-07 12:50 myhdl-0.5.1dev1.tar.gz
> drwxr-xr-x 7 oystein oystein   4096 2008-05-07 12:48 myhdl-0.5c1
> -rw-r--r-- 1 oystein oystein 760268 2008-05-07 12:47 myhdl-0.5c1.tar.gz
> drwxr-xr-x 6 oystein oystein   4096 2008-05-07 12:47 myhdl-0.6dev6
> -rw-r--r-- 1 oystein oystein 156404 2008-05-07 12:46 myhdl-0.6dev6.tar.gz
> drwxr-xr-x 6 oystein oystein   4096 2008-05-07 10:24 myhdl-0.6dev8
> -rw-r--r-- 1 oystein oystein 181734 2008-05-07 10:23 myhdl-0.6dev8.tar.gz
> 
> .. i could not get it working.  Hope to get some input on how to work 
> around this.
> 
> yours,
> oystein
> 
> 
> -------------------------------------------------------------------------
> This SF.net email is sponsored by the 2008 JavaOne(SM) Conference 
> Don't miss this year's exciting event. There's still time to save $100. 
> Use priority code J8TL2D2. 
> http://ad.doubleclick.net/clk;198757673;13503038;p?http://java.sun.com/javaone


-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Kaboutermansstraat 97, B-3000 Leuven, Belgium
     From Python to silicon:
     http://myhdl.jandecaluwe.com

[myhdl-list] Strange problem, VALUES instead of symbols being toVerilog'ed

[Oystein H. <oy...@ho...>]

Hello, this is my first post although I have lurked for some time.  First 
of all let me say that I simply love the idea of MyHDL.  The simplicity 
and power of python, direct to synthesizable verilog code..  yummie!

Second I must admit that I am a newbie, so be nice with me.  I have done 
some stuff with MyHDL and stumbled upon some of its (or verilog's?) 
limitations wrt verilog conversion.  So far I have been able to work 
around all of them, but now I am stuck.

I am adding a myhdl "uart" module to my project.  The instance is in the 
file uart.py, def uart().  Here's the start of it:

def uart(wb, baudclk, rxd, txd):
     wb_rst_i, wb_clk_i, wb_adr_i, wb_dat_o, wb_dat_i, wb_we_i, wb_sel_i, wb_stb_i, wb_ack_o, wb_cyc_i
  =  wb.rst_i, wb.clk_i, wb.adr_i, wb.dat_o, wb.dat_i, wb.we_i, wb.sel_i, wb.stb_i, wb.ack_o, wb.cyc_i
;
     char = Signal(bool(0));
     send = Signal(bool(0));
     sending = Signal(bool(0));
     send_done = Signal(bool(0));

     @always(wb_clk_i.posedge)
     def registers():
         wb_ack_o.next = False
         if wb_cyc_i:
             if wb_we_i:
                 char.next = wb_dat_i
                 send.next = True
             else:
                 wb_dat_o.next = concat(intbv(0x11)[5:], rxd, send, sending)
             wb_ack_o.next = True

.. as you can see I am "exploding" a wishbone bus in the beginning, and 
then declaring some internal registers (at least this is what I am trying 
to do).  But, registers() is converted into the following verilog:

always @(posedge wb_clk_i) begin: POWERSOC_I_UART_0
     uart_ack_o <= 0;
     if (uart_cyc_i) begin
         if (wb_we_o) begin
             False <= wb_dat_o;     <-- LOOK HERE
             False <= 1;            <-- AND HERE
         end
         else begin
             uart_dat_o <= {5'h11, rxd, False, False};  <-- AND HERE
         end
         uart_ack_o <= 1;
     end
end

.. it seems as though the _values_ of my vars are being written to verilog 
instead of the symbol names.  What am I doing wrong?  It only happens with 
the uart, and I have tried all kinds of strange things to make it work. Of 
course this does not synthesize (i use Xilinx' tools).  :-)

I have put a zip file with design files for you to try yourself 
(./powersoc), at http://home.powertech.no/oystein/myhdl-bug1.zip .

For the record, I have tried it with the following myhdl versions:

drwxr-xr-x 8 oystein oystein   4096 2008-05-07 12:51 myhdl-0.5.1dev1
-rw-r--r-- 1 oystein oystein 768032 2008-05-07 12:50 myhdl-0.5.1dev1.tar.gz
drwxr-xr-x 7 oystein oystein   4096 2008-05-07 12:48 myhdl-0.5c1
-rw-r--r-- 1 oystein oystein 760268 2008-05-07 12:47 myhdl-0.5c1.tar.gz
drwxr-xr-x 6 oystein oystein   4096 2008-05-07 12:47 myhdl-0.6dev6
-rw-r--r-- 1 oystein oystein 156404 2008-05-07 12:46 myhdl-0.6dev6.tar.gz
drwxr-xr-x 6 oystein oystein   4096 2008-05-07 10:24 myhdl-0.6dev8
-rw-r--r-- 1 oystein oystein 181734 2008-05-07 10:23 myhdl-0.6dev8.tar.gz

.. i could not get it working.  Hope to get some input on how to work 
around this.

yours,
oystein

Re: [myhdl-list] Calling VHDL modules within MyHDL?

[Jan D. <ja...@ja...>]

Tom Dillon wrote:
> Jan,
> 
> Could he not use User-defined Verilog code to make a connection to the Verilog module then use a 
> Verilog simulator for simulation?
> 
> http://www.jandecaluwe.com/Tools/MyHDL/manual/ref-conv-user.html
> 
> Could even just use regular float numbers and simulate with MyHDL and only use the User-defined 
> Verilog when converting to Verilog.

Correct, this is an interesting solution. One would still have to write
a MyHDL model "manually" for MyHDL simulation, but it can be a high
level model that is much simpler than the (synthesizable) equivalent
that may be available in Verilog/VHDL.

This is definitely one of the target applications of user-defined
Verilog/VHDL code.

Thanks,

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Kaboutermansstraat 97, B-3000 Leuven, Belgium
     From Python to silicon:
     http://myhdl.jandecaluwe.com

Re: [myhdl-list] Calling VHDL modules within MyHDL?

[Blubaugh, D. A. <dbl...@be...>]

Jan,


One second thought.  I believe that you are correct.  I would love to
jumpstart a MyHDL IP Library!!!


Thanks,

David Blubaugh

 

-----Original Message-----
From: myh...@li...
[mailto:myh...@li...] On Behalf Of Jan
Decaluwe
Sent: Tuesday, April 08, 2008 11:31 AM
To: myh...@li...
Subject: Re: [myhdl-list] Calling VHDL modules within MyHDL?

Blubaugh, David A. wrote:
> Chris,
> 
> 
> Is there a way to call or import modules in VHDL or Verilog into
MyHDL? 

Not currently.

> If that can be done, I believe, I can call or import a VHDL module 
> from OPENCORES.org which handles the necessary floating-point 
> multiplication, subtraction, addition, and especially division.  Does 
> anyone believe that this is feasible??

Probably yes.

However, I think it will be difficult to find a MyHDL-lover to implement
such a capabibility. It would be a lot of work that would promote
keeping VHDL or Verilog as a front-end language.

Here's an alternative. If you find a useful open-source IP block, why
not rewrite it in MyHDL? Look at the advantages:

* for a write-once, use-many IP block, rewriting makes sense
* rewriting may be straightforward or easy, given the existing code
* verification is likely much easier/elegant using Python and a unit
test framework
* you would jumpstart a MyHDL IP library
* with the MyHDL convertors, you would now have an equivalent block
available in 3 languages: MyHDL, Verilog and VHDL. This capability is
unique, and makes this approach even interesting to those who prefer to
stick with Verilog an VHDL.

Jan

--
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Kaboutermansstraat 97, B-3000 Leuven, Belgium
     From Python to silicon:
     http://myhdl.jandecaluwe.com


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This e-mail transmission contains information that is confidential and may be 
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After replying, please erase it from your computer system. Your assistance in 
correcting this error is appreciated.

Re: [myhdl-list] Calling VHDL modules within MyHDL?

[Blubaugh, D. A. <dbl...@be...>]

Tom and Jan,


The logic behind this is to use MyHDL and ultimately python as a
platform to QUICKLY develop simulation as to how the algorithm, with the
assistance of the floating-point verilog modules, is truly behaving.  I
ultimately believe that MyHDL with the integration of the ability to
develop, simulate, test, and finally generate floating-point-based
algorithms within Verilog or VHDL would make a unique development
platform.  Also there are legacy VHDL modules that could be imported by
MyHDL for simulation and testing purposes.  In final words, please do
not refer to me in the third person.  

Thanks,

David Blubaugh
 

-----Original Message-----
From: myh...@li...
[mailto:myh...@li...] On Behalf Of Tom
Dillon
Sent: Tuesday, April 08, 2008 2:26 PM
To: General discussions on MyHDL
Subject: Re: [myhdl-list] Calling VHDL modules within MyHDL?

Jan,

Could he not use User-defined Verilog code to make a connection to the
Verilog module then use a Verilog simulator for simulation?

http://www.jandecaluwe.com/Tools/MyHDL/manual/ref-conv-user.html

Could even just use regular float numbers and simulate with MyHDL and
only use the User-defined Verilog when converting to Verilog.

On the other hand, it would not be very difficult to implement the
floating point modules in MyHDL.

Tom


On Tuesday 08 April 2008 10:31:17 am Jan Decaluwe wrote:
> Blubaugh, David A. wrote:
> > Chris,
> >
> >
> > Is there a way to call or import modules in VHDL or Verilog into
MyHDL?
>
> Not currently.
>
> > If that can be done, I believe, I can call or import a VHDL module 
> > from OPENCORES.org which handles the necessary floating-point 
> > multiplication, subtraction, addition, and especially division.  
> > Does anyone believe that this is feasible??
>
> Probably yes.
>
> However, I think it will be difficult to find a MyHDL-lover to 
> implement such a capabibility. It would be a lot of work that would 
> promote keeping VHDL or Verilog as a front-end language.
>
> Here's an alternative. If you find a useful open-source IP block, why 
> not rewrite it in MyHDL? Look at the advantages:
>
> * for a write-once, use-many IP block, rewriting makes sense
> * rewriting may be straightforward or easy, given the existing code
> * verification is likely much easier/elegant using Python and a unit 
> test framework * you would jumpstart a MyHDL IP library
> * with the MyHDL convertors, you would now have an equivalent block 
> available in 3 languages: MyHDL, Verilog and VHDL. This capability is 
> unique, and makes this approach even interesting to those who prefer 
> to stick with Verilog an VHDL.
>
> Jan



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Re: [myhdl-list] Calling VHDL modules within MyHDL?

[Tom D. <TD...@di...>]

Jan,

Could he not use User-defined Verilog code to make a connection to the Verilog module then use a 
Verilog simulator for simulation?

http://www.jandecaluwe.com/Tools/MyHDL/manual/ref-conv-user.html

Could even just use regular float numbers and simulate with MyHDL and only use the User-defined 
Verilog when converting to Verilog.

On the other hand, it would not be very difficult to implement the floating point modules in MyHDL.

Tom


On Tuesday 08 April 2008 10:31:17 am Jan Decaluwe wrote:
> Blubaugh, David A. wrote:
> > Chris,
> >
> >
> > Is there a way to call or import modules in VHDL or Verilog into MyHDL?
>
> Not currently.
>
> > If that can be done, I believe, I can call or import a VHDL module from
> > OPENCORES.org which handles the necessary floating-point multiplication,
> > subtraction, addition, and especially division.  Does anyone believe
> > that this is feasible??
>
> Probably yes.
>
> However, I think it will be difficult to find a MyHDL-lover to implement
> such a capabibility. It would be a lot of work that would promote keeping
> VHDL or Verilog as a front-end language.
>
> Here's an alternative. If you find a useful open-source IP block, why
> not rewrite it in MyHDL? Look at the advantages:
>
> * for a write-once, use-many IP block, rewriting makes sense
> * rewriting may be straightforward or easy, given the existing code
> * verification is likely much easier/elegant using Python and a unit test
> framework * you would jumpstart a MyHDL IP library
> * with the MyHDL convertors, you would now have an equivalent block
> available in 3 languages: MyHDL, Verilog and VHDL. This capability is
> unique, and makes this approach even interesting to those who prefer to
> stick with Verilog an VHDL.
>
> Jan

Re: [myhdl-list] Calling VHDL modules within MyHDL?

[Jan D. <ja...@ja...>]

Blubaugh, David A. wrote:
> Chris,
> 
> 
> Is there a way to call or import modules in VHDL or Verilog into MyHDL? 

Not currently.

> If that can be done, I believe, I can call or import a VHDL module from 
> OPENCORES.org which handles the necessary floating-point multiplication, 
> subtraction, addition, and especially division.  Does anyone believe 
> that this is feasible??

Probably yes.

However, I think it will be difficult to find a MyHDL-lover to implement
such a capabibility. It would be a lot of work that would promote keeping
VHDL or Verilog as a front-end language.

Here's an alternative. If you find a useful open-source IP block, why
not rewrite it in MyHDL? Look at the advantages:

* for a write-once, use-many IP block, rewriting makes sense
* rewriting may be straightforward or easy, given the existing code
* verification is likely much easier/elegant using Python and a unit test framework
* you would jumpstart a MyHDL IP library
* with the MyHDL convertors, you would now have an equivalent block available
in 3 languages: MyHDL, Verilog and VHDL. This capability is unique, and makes
this approach even interesting to those who prefer to stick with Verilog
an VHDL.

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Kaboutermansstraat 97, B-3000 Leuven, Belgium
     From Python to silicon:
     http://myhdl.jandecaluwe.com

Re: [myhdl-list] Calling VHDL modules within MyHDL?

[Christopher L. F. <cf...@uc...>]

MyHDL supports co-simulation with Verilog and VHDL.  Currently the 
Verilog co-simulation uses the PLI/VPI interface.  Icarus and Cver are 
supported with the downloaded code.

More information can be found in the MyHDL manual.

Jan can comment on this topic better than I.

Blubaugh, David A. wrote:
> Chris,
> 
> 
> Is there a way to call or import modules in VHDL or Verilog into MyHDL?  
> If that can be done, I believe, I can call or import a VHDL module from 
> OPENCORES.org which handles the necessary floating-point multiplication, 
> subtraction, addition, and especially division.  Does anyone believe 
> that this is feasible??
> 
> 
> Thanks,
> 
> 
> David Blubaugh
> 
> 
> 
> 
> This e-mail transmission contains information that is confidential and 
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[myhdl-list] Calling VHDL modules within MyHDL?

[Blubaugh, D. A. <dbl...@be...>]

Chris,


Is there a way to call or import modules in VHDL or Verilog into MyHDL?
If that can be done, I believe, I can call or import a VHDL module from
OPENCORES.org which handles the necessary floating-point multiplication,
subtraction, addition, and especially division.  Does anyone believe
that this is feasible?? 


Thanks,


David Blubaugh





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Re: [myhdl-list] FW: Floating-point support

[Blubaugh, D. A. <dbl...@be...>]

Tom,

Would you be interested in helping??  For the purpose of allowing Jan to
concentrate on making an already impressive development entity (MyHDL)
become even better.  

David Blubaugh




-----Original Message-----
From: myh...@li...
[mailto:myh...@li...] On Behalf Of Tom
Dillon
Sent: Wednesday, March 26, 2008 10:13 PM
To: General discussions on MyHDL
Subject: Re: [myhdl-list] FW: Floating-point support

On Friday 21 March 2008 11:39:54 am Blubaugh, David A. wrote:
> Is there a possibility that you would consider creating a separate 
> project??
>
> Thanks,
>
> David Blubaugh
>

In my opinion I would hate to have Jan's efforts on MyHDL diluted by
taking on another project. I think there is plenty of effective use for
MyHDL in a design flow now and plenty of future improvements that will
make it even more useful and I would not like to have Jan using his free
time on anything else. 

I should say that is my selfish opinion.

Tom




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Re: [myhdl-list] Bit-wise inversion issue

[Christopher L. F. <cf...@uc...>]

Thanks!  VHDL is generated without errors now.

On Mar 27, 2008, at 11:14 AM, Jan Decaluwe wrote:

> Jan Decaluwe wrote:
>> Christopher L. Felton wrote:
>>
>>> Jan,
>>>
>>> First, thanks for the changes in the latest development release,
>>> incredible effort on your end with the timely changes!
>>>
>>> But (there is always a but) the VHDL conversion with the development
>>> build fails (at least for my example)?  I have not looked into the
>>> details why it is failing, but I attached the files that I am  
>>> using and
>>> below is the error.
>>>
>>> The Verilog conversion works fine, by inspection and cosimulation  
>>> it is
>>> valid (haven't synthesized).
>>
>>
>> Thanks, I'm able to reproduce the error.
>
> Development 0.6dev8 (just released) solves the problem in my
> unit tests. However, I haven't tried it on your example.
>
> In the process, I think I made the type inferencing mechanism
> in the VHDL convertor more robust in general.
>
> Jan
>
> --
> Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
> Kaboutermansstraat 97, B-3000 Leuven, Belgium
>     From Python to silicon:
>     http://myhdl.jandecaluwe.com
>
>
> -------------------------------------------------------------------------
> Check out the new SourceForge.net Marketplace.
> It's the best place to buy or sell services for
> just about anything Open Source.
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> _______________________________________________
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> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list

Re: [myhdl-list] Bit-wise inversion issue

[Jan D. <ja...@ja...>]

Jan Decaluwe wrote:
> Christopher L. Felton wrote:
> 
>>Jan,
>>
>>First, thanks for the changes in the latest development release, 
>>incredible effort on your end with the timely changes!
>>
>>But (there is always a but) the VHDL conversion with the development 
>>build fails (at least for my example)?  I have not looked into the 
>>details why it is failing, but I attached the files that I am using and 
>>below is the error.
>>
>>The Verilog conversion works fine, by inspection and cosimulation it is 
>>valid (haven't synthesized).
> 
> 
> Thanks, I'm able to reproduce the error.

Development 0.6dev8 (just released) solves the problem in my
unit tests. However, I haven't tried it on your example.

In the process, I think I made the type inferencing mechanism
in the VHDL convertor more robust in general.

Jan

--
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Kaboutermansstraat 97, B-3000 Leuven, Belgium
     From Python to silicon:
     http://myhdl.jandecaluwe.com

[myhdl-list] 0.6dev8

[Jan D. <ja...@ja...>]

Development version 0.6dev8 is available from here:

      http://myhdl.jandecaluwe.com/doku.php/dev:snapshots#snapshots

This solves a problem with bit inversion when used in expressions,
and converted to VHDL.

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Kaboutermansstraat 97, B-3000 Leuven, Belgium
      From Python to silicon:
      http://myhdl.jandecaluwe.com

Re: [myhdl-list] FW: Floating-point support

[Tom D. <TD...@di...>]

On Friday 21 March 2008 11:39:54 am Blubaugh, David A. wrote:
> Is there a possibility that you would consider creating a separate
> project??
>
> Thanks,
>
> David Blubaugh
>

In my opinion I would hate to have Jan's efforts on MyHDL diluted by taking on another project. I 
think there is plenty of effective use for MyHDL in a design flow now and plenty of future 
improvements that will make it even more useful and I would not like to have Jan using his free 
time on anything else. 

I should say that is my selfish opinion.

Tom

Re: [myhdl-list] Bit-wise inversion issue

[Jan D. <ja...@ja...>]

Christopher L. Felton wrote:
> Jan,
> 
> First, thanks for the changes in the latest development release, 
> incredible effort on your end with the timely changes!
> 
> But (there is always a but) the VHDL conversion with the development 
> build fails (at least for my example)?  I have not looked into the 
> details why it is failing, but I attached the files that I am using and 
> below is the error.
> 
> The Verilog conversion works fine, by inspection and cosimulation it is 
> valid (haven't synthesized).

Thanks, I'm able to reproduce the error. Unfortunately the fix is
not as obvious as I thought at first - apparently some special
care is needed to deal with the conversion of bit inversions used
in expresssions. (And next week I'm on holiday so it may take
some time.)

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Kaboutermansstraat 97, B-3000 Leuven, Belgium
     From Python to silicon:
     http://myhdl.jandecaluwe.com

Re: [myhdl-list] FW: Floating-point support

[Jan D. <ja...@ja...>]

Blubaugh, David A. wrote:
> Is there a possibility that you would consider creating a separate
> project??  

Mm, one open-source project is enough for me currently :-)

If such a credible, open-source, Python to MyHDL behavioral
synthesis project would exist, I'd be a very interested
supporter and possibly contributor.

For those that warm up to the idea, I would start by studying the
open-source solution mentioned in this thread. In fact, I would
expect that the core of such a tool does not depend on the input
language (e.g. C) or the output language (e.g. RTL). In that case,
one could get a head start by simply implementing an alternative
front end (Python subset) and back end (MyHDL RTL.)

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Kaboutermansstraat 97, B-3000 Leuven, Belgium
     From Python to silicon:
     http://myhdl.jandecaluwe.com

Re: [myhdl-list] Bit-wise inversion issue

[Christopher L. F. <cf...@uc...>]

Jan,

First, thanks for the changes in the latest development release,  
incredible effort on your end with the timely changes!

But (there is always a but) the VHDL conversion with the development  
build fails (at least for my example)?  I have not looked into the  
details why it is failing, but I attached the files that I am using  
and below is the error.

The Verilog conversion works fine, by inspection and cosimulation it  
is valid (haven't synthesized).

*** Error ?? ****
     def inferBinaryOpType(self, node, left, right, op=None):
E       if isinstance(left.vhd, (vhd_boolean, vhd_std_logic)):
 >       AttributeError: Invert instance has no attribute 'vhd'
**** ****

Thanks



On Mar 9, 2008, at 10:44 AM, Jan Decaluwe wrote:

> Jan Decaluwe wrote:
>
>> Conclusion
>> ----------
>>
>> The drawback of the "Pure Python" solution is probably fatal
>> for practical purposes. Therefore, I propose to keep the
>> "Practical Hardware" solution.
>
> I have implemented this, including conversion support for
> Verilog and VHDL.
>
> This will be included in the upcoming development release 0.6dev7.
>
> Jan
>
> -- 
> Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
> Kaboutermansstraat 97, B-3000 Leuven, Belgium
>     From Python to silicon:
>     http://myhdl.jandecaluwe.com
>
>
> -------------------------------------------------------------------------
> This SF.net email is sponsored by: Microsoft
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Re: [myhdl-list] FW: Floating-point support

[Blubaugh, D. A. <dbl...@be...>]

Is there a possibility that you would consider creating a separate
project??  

Thanks,

David Blubaugh


 

-----Original Message-----
From: myh...@li...
[mailto:myh...@li...] On Behalf Of Jan
Decaluwe
Sent: Friday, March 21, 2008 12:17 PM
To: myh...@li...
Subject: Re: [myhdl-list] FW: Floating-point support

Blubaugh, David A. wrote:
> Thank you very much for your response.  
> 
> 
> 
> The commercial packages that I am referring to is the ImpulseC
complier.
> This compiler can extract c source code, which has been written with 
> floats and doubles.  Where upon it then converts most of the C- source

> code, including the float and double mathematical processing, and 
> converts it directly into VHDL or verilog.  This is done for high 
> precision and numerical applications research, like the Fast Fourier 
> Transform.

If I understand this correctly, the tool starts from an untimed c
description and generates RTL code. It contains features such as
scheduling and resource allocation and can therefore be qualified as a
"behavioral synthesis tool".

I believe that the analogy in the Python world would be a behavioral
synthesis tool that takes a generic Python description as input and
generates RTL code, perhaps using a Python package such as MyHDL. MyHDL
adds an event-driven paradigm to Python, to you need something like it
for "timed" hardware descriptions.

Therefore, MyHDL is of little help for the input part of a similar
Python-based tool, and it has nothing that can help with the behavioral
synthesis part.
Developing a behavioral synthesis tool is a truly large effort. If I
would consider such an effort, I would start a separate project.

Best regards,

Jan

--
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Kaboutermansstraat 97, B-3000 Leuven, Belgium
     From Python to silicon:
     http://myhdl.jandecaluwe.com


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After replying, please erase it from your computer system. Your assistance in 
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Re: [myhdl-list] FW: Floating-point support

[Jan D. <ja...@ja...>]

Blubaugh, David A. wrote:
> Thank you very much for your response.  
> 
> 
> 
> The commercial packages that I am referring to is the ImpulseC complier.
> This compiler can extract c source code, which has been written with
> floats and doubles.  Where upon it then converts most of the C- source
> code, including the float and double mathematical processing, and
> converts it directly into VHDL or verilog.  This is done for high
> precision and numerical applications research, like the Fast Fourier
> Transform.

If I understand this correctly, the tool starts from an untimed c description
and generates RTL code. It contains features such as scheduling and resource
allocation and can therefore be qualified as a "behavioral synthesis tool".

I believe that the analogy in the Python world would be a behavioral synthesis
tool that takes a generic Python description as input and generates RTL code,
perhaps using a Python package such as MyHDL. MyHDL adds an event-driven
paradigm to Python, to you need something like it for "timed" hardware
descriptions.

Therefore, MyHDL is of little help for the input part of a similar Python-based
tool, and it has nothing that can help with the behavioral synthesis part.
Developing a behavioral synthesis tool is a truly large effort. If I would
consider such an effort, I would start a separate project.

Best regards,

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Kaboutermansstraat 97, B-3000 Leuven, Belgium
     From Python to silicon:
     http://myhdl.jandecaluwe.com

Re: [myhdl-list] FW: Floating-point support

[Blubaugh, D. A. <dbl...@be...>]

Chris,

That is true.  However, the developers at ImpulseC have truly done an
excellent job in developing a great development system, which is far
more advanced and capable than the Stream-C compiler from Los Alamos.  I
am starting to wonder if I should not combine both ImpulseC and MyHDL
together, since both development systems have excellent features to
utilize in any research and development nightmare, like the one I am
currently facing with my Master's thesis.  In second thought, maybe I
will go ahead and develop a hybrid combination of the two systems.
Anyone interested in helping with be more than appreciated!!

Thanks,

David Blubaugh




-----Original Message-----
From: myh...@li...
[mailto:myh...@li...] On Behalf Of
Christopher L. Felton
Sent: Friday, March 21, 2008 2:57 AM
To: General discussions on MyHDL
Cc: ja...@ja...
Subject: Re: [myhdl-list] FW: Floating-point support

Impulse-C is based off the open-source Streams-C compiler.

You can get more information on the implementation from here
(http://www.streams-c.lanl.gov/ ).

On Mar 20, 2008, at 4:12 PM, Blubaugh, David A. wrote:

> Thank you very much for your response.
>
>
>
> The commercial packages that I am referring to is the ImpulseC 
> complier.
> This compiler can extract c source code, which has been written with 
> floats and doubles.  Where upon it then converts most of the C- source

> code, including the float and double mathematical processing, and 
> converts it directly into VHDL or verilog.  This is done for high 
> precision and numerical applications research, like the Fast Fourier 
> Transform.
>
>
> I was wondering that floating-point algorithms, like the FFT,  could 
> be eventually supported by MyHDL, with a direct conversion of 
> floating-point python to VHDL or verilog?  I believe one way to handle

> this would be to develop a module which handles the floating-point 
> procedure for addition, subtraction, multiplication, and division, 
> which has been defined by IEEE and then import this module to handle 
> the
> computational tasks within MyHDL.  Is that possible?   I definitely  
> hope
> so!!!!
>
>
> Also, is there a method to automatically generate pipeline 
> architectures
> with MyHDL?   Thanks for all of the help and answers!!!!
>
>
> David Blubaugh
>
>
>
>
>
>
>
>
>
> -----Original Message-----
> From: myh...@li...
> [mailto:myh...@li...] On Behalf Of Jan 
> Decaluwe
> Sent: Thursday, March 20, 2008 5:53 PM
> To: myh...@li...
> Subject: Re: [myhdl-list] FW: Floating-point support
>
> Blubaugh, David A. wrote:
>> Would anyone know as to how to develop floating point support for the

>> MyHDL module?  Has anyone worked with any alternative versions of the

>> IEEE standard for floating -point?  Also, has anyone developed a 
>> floating-point library for a module within the python environment in 
>> order to execute numerical computations.  I would imagine since I am 
>> translating python to verilog by using MyHDL , that I will have to 
>> develop the floating-point support module in python source code as
> well ??
>>
>> I believe this is what will be required in order to develop 
>> floating-point capable algorithms within Verilog.  If I can develop 
>> this one feature from MyHDL, it would allow this module to be fairly 
>> competitive with commercial products.
>
> I am no expert in floating point. What is it exactly that the 
> commercial products you refer to do?
>
> Jan
>
> --
> Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com 
> Kaboutermansstraat 97, B-3000 Leuven, Belgium
>     From Python to silicon:
>     http://myhdl.jandecaluwe.com
>
>
> ----------------------------------------------------------------------
> --
> -
> This SF.net email is sponsored by: Microsoft Defy all challenges. 
> Microsoft(R) Visual Studio 2008.
> http://clk.atdmt.com/MRT/go/vse0120000070mrt/direct/01/
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> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>
> This e-mail transmission contains information that is confidential and

> may be privileged. It is intended only for the addressee(s) named 
> above. If you receive this e-mail in error, please do not read, copy 
> or disseminate it in any manner.
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Re: [myhdl-list] FW: Floating-point support

[Christopher L. F. <cf...@uc...>]

Impulse-C is based off the open-source Streams-C compiler.

You can get more information on the implementation from here (http://www.streams-c.lanl.gov/ 
).

On Mar 20, 2008, at 4:12 PM, Blubaugh, David A. wrote:

> Thank you very much for your response.
>
>
>
> The commercial packages that I am referring to is the ImpulseC  
> complier.
> This compiler can extract c source code, which has been written with
> floats and doubles.  Where upon it then converts most of the C- source
> code, including the float and double mathematical processing, and
> converts it directly into VHDL or verilog.  This is done for high
> precision and numerical applications research, like the Fast Fourier
> Transform.
>
>
> I was wondering that floating-point algorithms, like the FFT,  could  
> be
> eventually supported by MyHDL, with a direct conversion of
> floating-point python to VHDL or verilog?  I believe one way to handle
> this would be to develop a module which handles the floating-point
> procedure for addition, subtraction, multiplication, and division,  
> which
> has been defined by IEEE and then import this module to handle the
> computational tasks within MyHDL.  Is that possible?   I definitely  
> hope
> so!!!!
>
>
> Also, is there a method to automatically generate pipeline  
> architectures
> with MyHDL?   Thanks for all of the help and answers!!!!
>
>
> David Blubaugh
>
>
>
>
>
>
>
>
>
> -----Original Message-----
> From: myh...@li...
> [mailto:myh...@li...] On Behalf Of Jan
> Decaluwe
> Sent: Thursday, March 20, 2008 5:53 PM
> To: myh...@li...
> Subject: Re: [myhdl-list] FW: Floating-point support
>
> Blubaugh, David A. wrote:
>> Would anyone know as to how to develop floating point support for the
>> MyHDL module?  Has anyone worked with any alternative versions of the
>> IEEE standard for floating -point?  Also, has anyone developed a
>> floating-point library for a module within the python environment in
>> order to execute numerical computations.  I would imagine since I am
>> translating python to verilog by using MyHDL , that I will have to
>> develop the floating-point support module in python source code as
> well ??
>>
>> I believe this is what will be required in order to develop
>> floating-point capable algorithms within Verilog.  If I can develop
>> this one feature from MyHDL, it would allow this module to be fairly
>> competitive with commercial products.
>
> I am no expert in floating point. What is it exactly that the  
> commercial
> products you refer to do?
>
> Jan
>
> --
> Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
> Kaboutermansstraat 97, B-3000 Leuven, Belgium
>     From Python to silicon:
>     http://myhdl.jandecaluwe.com
>
>
> ------------------------------------------------------------------------
> -
> This SF.net email is sponsored by: Microsoft
> Defy all challenges. Microsoft(R) Visual Studio 2008.
> http://clk.atdmt.com/MRT/go/vse0120000070mrt/direct/01/
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>
> This e-mail transmission contains information that is confidential  
> and may be
> privileged. It is intended only for the addressee(s) named above. If  
> you receive
> this e-mail in error, please do not read, copy or disseminate it in  
> any manner.
> If you are not the intended recipient, any disclosure, copying,  
> distribution or
> use of the contents of this information is prohibited. Please reply  
> to the
> message immediately by informing the sender that the message was  
> misdirected.
> After replying, please erase it from your computer system. Your  
> assistance in
> correcting this error is appreciated.
>
>
> -------------------------------------------------------------------------
> This SF.net email is sponsored by: Microsoft
> Defy all challenges. Microsoft(R) Visual Studio 2008.
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Re: [myhdl-list] FW: Floating-point support

[Blubaugh, D. A. <dbl...@be...>]

Thank you very much for your response.  



The commercial packages that I am referring to is the ImpulseC complier.
This compiler can extract c source code, which has been written with
floats and doubles.  Where upon it then converts most of the C- source
code, including the float and double mathematical processing, and
converts it directly into VHDL or verilog.  This is done for high
precision and numerical applications research, like the Fast Fourier
Transform.  


I was wondering that floating-point algorithms, like the FFT,  could be
eventually supported by MyHDL, with a direct conversion of
floating-point python to VHDL or verilog?  I believe one way to handle
this would be to develop a module which handles the floating-point
procedure for addition, subtraction, multiplication, and division, which
has been defined by IEEE and then import this module to handle the
computational tasks within MyHDL.  Is that possible?   I definitely hope
so!!!! 


Also, is there a method to automatically generate pipeline architectures
with MyHDL?   Thanks for all of the help and answers!!!!


David Blubaugh 







 

-----Original Message-----
From: myh...@li...
[mailto:myh...@li...] On Behalf Of Jan
Decaluwe
Sent: Thursday, March 20, 2008 5:53 PM
To: myh...@li...
Subject: Re: [myhdl-list] FW: Floating-point support

Blubaugh, David A. wrote:
> Would anyone know as to how to develop floating point support for the 
> MyHDL module?  Has anyone worked with any alternative versions of the 
> IEEE standard for floating -point?  Also, has anyone developed a 
> floating-point library for a module within the python environment in 
> order to execute numerical computations.  I would imagine since I am 
> translating python to verilog by using MyHDL , that I will have to 
> develop the floating-point support module in python source code as
well ??
> 
> I believe this is what will be required in order to develop 
> floating-point capable algorithms within Verilog.  If I can develop 
> this one feature from MyHDL, it would allow this module to be fairly 
> competitive with commercial products.

I am no expert in floating point. What is it exactly that the commercial
products you refer to do?

Jan

--
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Kaboutermansstraat 97, B-3000 Leuven, Belgium
     From Python to silicon:
     http://myhdl.jandecaluwe.com


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Defy all challenges. Microsoft(R) Visual Studio 2008.
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