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From: Brendan R. <bre...@gm...> - 2008-06-05 18:28:15
|
Jan Decaluwe <jan <at> jandecaluwe.com> writes: > > I finally become frustrated enough from a hosting service > without shell access (yahoo) to decide to move all my web > activities to webfaction, including myhdl.jandecaluwe.com. > > From what I learned so far, I think I should have done > this much sooner > > If you notice something strange, let me know. > > Jan > I have a couple of sites (well... 5) there, myself. Webfaction are great and their panel stuff is teh bomb! Enjoy! - Brendan |
|
From: Günter D. <dan...@we...> - 2008-06-05 18:23:52
|
Jan Decaluwe wrote:
...
>
> I have now included your file. Not sure this is what you'd expect.
> I also see something strange with rendering constants like 1'b0.
This is odd, I found the Johnson Counter example and see what you are
saying. There is something messed up. I took that Verilog code and ran
it here with the code through the highlighter and got the following
result below. You can put that into an html file and look at it with the
browser. (Was not sure whether the mailing list accepts attachments)
The highlighting looks fine there. One thing I noticed, the created
highlighted html file does not have any html tags, like <header> or <body>.
Guenter
----------------------------
<pre class="verilog"><span style="color: #A52A2A; font-weight:
bold;">module</span> jc2 <span style="color: #9F79EE;">(</span>
goLeft<span style="color: #5D478B;">,</span>
goRight<span style="color: #5D478B;">,</span>
stop<span style="color: #5D478B;">,</span>
clk<span style="color: #5D478B;">,</span>
q
<span style="color: #9F79EE;">)</span><span style="color:
#5D478B;">;</span>
<span style="color: #A52A2A; font-weight: bold;">input</span>
goLeft<span style="color: #5D478B;">;</span>
<span style="color: #A52A2A; font-weight: bold;">input</span>
goRight<span style="color: #5D478B;">;</span>
<span style="color: #A52A2A; font-weight: bold;">input</span> stop<span
style="color: #5D478B;">;</span>
<span style="color: #A52A2A; font-weight: bold;">input</span> clk<span
style="color: #5D478B;">;</span>
<span style="color: #A52A2A; font-weight: bold;">output</span> <span
style="color: #9F79EE;">[</span><span style="color:
#ff0055;">3</span><span style="color: #5D478B;">:</span><span
style="color: #ff0055;">0</span><span style="color:
#9F79EE;">]</span> q<span style="color: #5D478B;">;</span>
<span style="color: #A52A2A; font-weight: bold;">reg</span> <span
style="color: #9F79EE;">[</span><span style="color:
#ff0055;">3</span><span style="color: #5D478B;">:</span><span
style="color: #ff0055;">0</span><span style="color:
#9F79EE;">]</span> q<span style="color: #5D478B;">;</span>
<span style="color: #A52A2A; font-weight: bold;">reg</span> run<span
style="color: #5D478B;">;</span>
<span style="color: #A52A2A; font-weight: bold;">reg</span> <span
style="color: #9F79EE;">[</span><span style="color:
#ff0055;">0</span><span style="color: #5D478B;">:</span><span
style="color: #ff0055;">0</span><span style="color:
#9F79EE;">]</span> dir<span style="color: #5D478B;">;</span>
<span style="color: #A52A2A; font-weight: bold;">always</span> <span
style="color: #5D478B;">@</span><span style="color:
#9F79EE;">(</span><span style="color: #A52A2A; font-weight:
bold;">posedge</span> clk<span style="color: #9F79EE;">)</span>
<span style="color: #A52A2A; font-weight: bold;">begin</span><span
style="color: #5D478B;">:</span> _jc2_logic
<span style="color: #A52A2A; font-weight: bold;">if</span> <span
style="color: #9F79EE;">(</span><span style="color:
#9F79EE;">(</span>goRight <span style="color: #5D478B;">==</span>
<span style="color: #ff0055;">0</span><span style="color:
#9F79EE;">)</span><span style="color: #9F79EE;">)</span> <span
style="color: #A52A2A; font-weight: bold;">begin</span>
dir <span style="color: #5D478B;"><=</span> <span
style="color: #ff0055;"><span style="color:
#ff0055;">1</span>'b0</span><span style="color: #5D478B;">|>;</span>
run <span style="color: #5D478B;"><=</span> <span
style="color: #ff0055;">1</span><span style="color: #5D478B;">;</span>
<span style="color: #A52A2A; font-weight: bold;">end</span>
<span style="color: #A52A2A; font-weight: bold;">else</span> <span
style="color: #A52A2A; font-weight: bold;">if</span> <span style="color:
#9F79EE;">(</span><span style="color: #9F79EE;">(</span>goLeft
<span style="color: #5D478B;">==</span> <span style="color:
#ff0055;">0</span><span style="color: #9F79EE;">)</span><span
style="color: #9F79EE;">)</span> <span style="color: #A52A2A;
font-weight: bold;">begin</span>
dir <span style="color: #5D478B;"><=</span> <span
style="color: #ff0055;"><span style="color:
#ff0055;">1</span>'b1</span><span style="color: #5D478B;">|>;</span>
run <span style="color: #5D478B;"><=</span> <span
style="color: #ff0055;">1</span><span style="color: #5D478B;">;</span>
<span style="color: #A52A2A; font-weight: bold;">end</span>
<span style="color: #A52A2A; font-weight: bold;">if</span> <span
style="color: #9F79EE;">(</span><span style="color:
#9F79EE;">(</span>stop <span style="color: #5D478B;">==</span> <span
style="color: #ff0055;">0</span><span style="color:
#9F79EE;">)</span><span style="color: #9F79EE;">)</span> <span
style="color: #A52A2A; font-weight: bold;">begin</span>
run <span style="color: #5D478B;"><=</span> <span
style="color: #ff0055;">0</span><span style="color: #5D478B;">;</span>
<span style="color: #A52A2A; font-weight: bold;">end</span>
<span style="color: #A52A2A; font-weight: bold;">if</span> <span
style="color: #9F79EE;">(</span>run<span style="color:
#9F79EE;">)</span> <span style="color: #A52A2A; font-weight:
bold;">begin</span>
<span style="color: #00008B; font-style: italic;">// synthesis
parallel_case full_case</span>
<span style="color: #A52A2A; font-weight: bold;">casez</span>
<span style="color: #9F79EE;">(</span>dir<span style="color:
#9F79EE;">)</span>
<span style="color: #ff0055;"><span style="color:
#ff0055;">1</span>'b1</span><span style="color: #5D478B;">|>:</span>
<span style="color: #A52A2A; font-weight: bold;">begin</span>
q<span style="color: #9F79EE;">[</span><span
style="color: #ff0055;">4</span><span style="color:
#ff0055;">-1</span><span style="color: #5D478B;">:</span><span
style="color: #ff0055;">1</span><span style="color:
#9F79EE;">]</span> <span style="color: #5D478B;"><=</span> q<span
style="color: #9F79EE;">[</span><span style="color:
#ff0055;">3</span><span style="color: #ff0055;">-1</span><span
style="color: #5D478B;">:</span><span style="color:
#ff0055;">0</span><span style="color: #9F79EE;">]</span><span
style="color: #5D478B;">;</span>
q<span style="color: #9F79EE;">[</span><span
style="color: #ff0055;">0</span><span style="color:
#9F79EE;">]</span> <span style="color: #5D478B;"><=</span> <span
style="color: #9F79EE;">(</span><span style="color:
#5D478B;">!</span>q<span style="color: #9F79EE;">[</span><span
style="color: #ff0055;">3</span><span style="color:
#9F79EE;">]</span><span style="color: #9F79EE;">)</span><span
style="color: #5D478B;">;</span>
<span style="color: #A52A2A; font-weight: bold;">end</span>
<span style="color: #A52A2A; font-weight:
bold;">default</span><span style="color: #5D478B;">:</span> <span
style="color: #A52A2A; font-weight: bold;">begin</span>
q<span style="color: #9F79EE;">[</span><span
style="color: #ff0055;">3</span><span style="color:
#ff0055;">-1</span><span style="color: #5D478B;">:</span><span
style="color: #ff0055;">0</span><span style="color:
#9F79EE;">]</span> <span style="color: #5D478B;"><=</span> q<span
style="color: #9F79EE;">[</span><span style="color:
#ff0055;">4</span><span style="color: #ff0055;">-1</span><span
style="color: #5D478B;">:</span><span style="color:
#ff0055;">1</span><span style="color: #9F79EE;">]</span><span
style="color: #5D478B;">;</span>
q<span style="color: #9F79EE;">[</span><span
style="color: #ff0055;">3</span><span style="color:
#9F79EE;">]</span> <span style="color: #5D478B;"><=</span> <span
style="color: #9F79EE;">(</span><span style="color:
#5D478B;">!</span>q<span style="color: #9F79EE;">[</span><span
style="color: #ff0055;">0</span><span style="color:
#9F79EE;">]</span><span style="color: #9F79EE;">)</span><span
style="color: #5D478B;">;</span>
<span style="color: #A52A2A; font-weight: bold;">end</span>
<span style="color: #A52A2A; font-weight: bold;">endcase</span>
<span style="color: #A52A2A; font-weight: bold;">end</span>
<span style="color: #A52A2A; font-weight: bold;">end</span>
<span style="color: #A52A2A; font-weight: bold;">endmodule</span>
</pre>
|
|
From: Günter D. <dan...@we...> - 2008-06-05 18:10:51
|
Maybe I am not up to date and this got actually already fixed. I justed noticed that in the Verilog generated code of the stopwatch example: http://myhdl.jandecaluwe.com/doku.php/cookbook:stopwatch there are blocking and non-blocking assignments in the same always block. Is that intended or would it be better to have only non-blocking assignments used? Guenter |
|
From: Günter D. <dan...@we...> - 2008-06-05 18:06:28
|
Jan Decaluwe wrote: ... > > I have now included your file. Not sure this is what you'd expect. > I also see something strange with rendering constants like 1'b0. The keywords are actually to be brown. There must be something else, like from the color scheme of the web page that takes over and adjusts the used colors? I haven't found a constants like 1'b0 on the web page yet. Still looking. They should be all the color like a single number, like 0. Guenter |
|
From: Jan D. <ja...@ja...> - 2008-06-05 18:00:10
|
I finally become frustrated enough from a hosting service without shell access (yahoo) to decide to move all my web activities to webfaction, including myhdl.jandecaluwe.com. From what I learned so far, I think I should have done this much sooner :-) If you notice something strange, let me know. Jan -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Kaboutermansstraat 97, B-3000 Leuven, Belgium From Python to silicon: http://myhdl.jandecaluwe.com |
|
From: Jan D. <ja...@ja...> - 2008-06-05 17:56:15
|
Günter Dannoritzer wrote: > > I am glad it is of some help. I created it for another web page on which > I wrote a Verilog introduction in German. Only strange thing is that it > does not use all the colors I specified: > > http://www.mikrocontroller.net/articles/Verilog > > It will be interesting to see how it looks on the myhdl page. I have now included your file. Not sure this is what you'd expect. I also see something strange with rendering constants like 1'b0. Jan -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Kaboutermansstraat 97, B-3000 Leuven, Belgium From Python to silicon: http://myhdl.jandecaluwe.com |
|
From: Günter D. <dan...@we...> - 2008-05-29 21:47:35
|
Jan Decaluwe wrote: ... > > Will you try to get this in the geshi distribution? Yes, I mailed it today to the maintainer. ... > > I'm sure your file is much more complete and I plan to use it (or, > if you get it into geshi, that will happen automatically). I am glad it is of some help. I created it for another web page on which I wrote a Verilog introduction in German. Only strange thing is that it does not use all the colors I specified: http://www.mikrocontroller.net/articles/Verilog It will be interesting to see how it looks on the myhdl page. Guenter |
|
From: Jan D. <ja...@ja...> - 2008-05-29 20:57:46
|
Günter Dannoritzer wrote: > Hi Jan, > > Slightly off topic, but when I was searching for a Verilog syntax > highlighter for GeSHi I got a few hits on the myhdl web page. > > I noticed that you must have some kind of Verilog syntax highlighter > going, as all the keywords for Verilog are shown bold. > > Anyhow, I have created one for GeSHi following somewhat the color scheme > used in vim. > > I have uploaded it to a page and it can be downloaded from this link: > > http://www.mikrocontroller.net/attachment/35709/verilog.php Thanks Guenter, Will you try to get this in the geshi distribution? It's quite some time ago already, but I think I reasoned as follows. Dokuwiki also uses geshi, but geshi had (has) no Verilog support. It had vhdl, so I thought Verilog would soon be available. In the mean time, I used a quick hack for Verilog based on the Python file. I have attached it for your reference. (Note: this is a private hack so the header is not consistent with the content - not for distribution.) I'm sure your file is much more complete and I plan to use it (or, if you get it into geshi, that will happen automatically). Jan -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Kaboutermansstraat 97, B-3000 Leuven, Belgium From Python to silicon: http://myhdl.jandecaluwe.com |
|
From: Jan D. <ja...@ja...> - 2008-05-29 20:23:53
|
Blubaugh, David A. wrote: > Jan, > > Hello. This is David Blubaugh. I have also worked on distributed > systems before. I have worked on a sensor fusion system based on the > kalman filter, which was in a distributed network form. I agree that > distributed systems are indeed what the future holds. I was just > wondering if the distributed technique that you described can be carried > over to the generation of verilog source code? David, I was talking about revision control systems (the software tools to manage source code development), not "real" systems :-) -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Kaboutermansstraat 97, B-3000 Leuven, Belgium From Python to silicon: http://myhdl.jandecaluwe.com |
|
From: Günter D. <dan...@we...> - 2008-05-29 19:41:44
|
Hi Jan, Slightly off topic, but when I was searching for a Verilog syntax highlighter for GeSHi I got a few hits on the myhdl web page. I noticed that you must have some kind of Verilog syntax highlighter going, as all the keywords for Verilog are shown bold. Anyhow, I have created one for GeSHi following somewhat the color scheme used in vim. I have uploaded it to a page and it can be downloaded from this link: http://www.mikrocontroller.net/attachment/35709/verilog.php Cheers, Guenter |
|
From: Blubaugh, D. A. <dbl...@be...> - 2008-05-29 19:35:38
|
Jan,
Hello. This is David Blubaugh. I have also worked on distributed
systems before. I have worked on a sensor fusion system based on the
kalman filter, which was in a distributed network form. I agree that
distributed systems are indeed what the future holds. I was just
wondering if the distributed technique that you described can be carried
over to the generation of verilog source code?
Thanks,
David Blubaugh
-----Original Message-----
From: myh...@li...
[mailto:myh...@li...] On Behalf Of Jan
Decaluwe
Sent: Thursday, May 29, 2008 2:27 PM
To: myh...@li...
Subject: [myhdl-list] Distributed revision control for MyHDL
Hello:
In the past I've called subversion a "winning solution" for revision
control and I have been using it for MyHDL.
Despite this, I never truly liked it. In particular, the way to do tags
and branches ("everything is a copy") seems attractive at first, but is
very unpractical, to the point of being unusable.
Recently I have understood that there are really 2 types of revision
control systems: centralized versus distributed. While subversion is a
winner among centralized systems, I have now become convinced that
distributed is the wave of the future.
I had experience with darcs (a distributed system) before, but I never
found that very convincing. What triggered my thinking were 2 things:
- a google video from Linus Torvalds about git
- a very positive experience with git in a real design project
With git, I found that after some days I was routinely doing things that
I had considered "advanced" with others systems, such as short-lived
feature branches.
Also, it is clear that distributed is much more powerful and versatile
in an open-source environment. Some issues inherent to centralized (e.g.
need for a connection to a server) simply go away.
After this, I decided I wanted something like this for MyHDL.
Besides git, only 1 other system is "tolerated" by Linus, and that is
mercurial. As this is a Python-based system (unlike git) and as many
high-profile projects are converting to it, you can guess what choice I
made ... I think git is probably more powerful at this point, but
mercurial is probably somewhat easier to learn and handle.
mercurial contains a convert tool that can convert subversion
repositories, which uses the subversion Python bindings. I had to do
quite some hacking (recompiling subversion with some libraries
disabled) before the conversion worked, but it finally did.
Then I followed a recipe to publish the repo on sourceforge.
You can see the result here:
http://myhdl.sourceforge.net/hg/myhdl
You can use this to browse the repo, but also for other things - but
this I will explain in a subsequent post.
Jan
--
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Kaboutermansstraat 97, B-3000 Leuven, Belgium
From Python to silicon:
http://myhdl.jandecaluwe.com
------------------------------------------------------------------------
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From: Jan D. <ja...@ja...> - 2008-05-29 19:27:02
|
Hello:
In the past I've called subversion a "winning solution" for
revision control and I have been using it for MyHDL.
Despite this, I never truly liked it. In particular, the way
to do tags and branches ("everything is a copy") seems attractive
at first, but is very unpractical, to the point of being unusable.
Recently I have understood that there are really 2 types of
revision control systems: centralized versus distributed. While
subversion is a winner among centralized systems, I have now
become convinced that distributed is the wave of the future.
I had experience with darcs (a distributed system) before, but
I never found that very convincing. What triggered my thinking
were 2 things:
- a google video from Linus Torvalds about git
- a very positive experience with git in a real design project
With git, I found that after some days I was routinely doing
things that I had considered "advanced" with others systems,
such as short-lived feature branches.
Also, it is clear that distributed is much more powerful and
versatile in an open-source environment. Some issues inherent
to centralized (e.g. need for a connection to a server) simply
go away.
After this, I decided I wanted something like this for MyHDL.
Besides git, only 1 other system is "tolerated" by Linus, and
that is mercurial. As this is a Python-based system (unlike git)
and as many high-profile projects are converting to it, you can
guess what choice I made ... I think git is probably more
powerful at this point, but mercurial is probably somewhat
easier to learn and handle.
mercurial contains a convert tool that can convert subversion
repositories, which uses the subversion Python bindings. I had
to do quite some hacking (recompiling subversion with some libraries
disabled) before the conversion worked, but it finally did.
Then I followed a recipe to publish the repo on sourceforge.
You can see the result here:
http://myhdl.sourceforge.net/hg/myhdl
You can use this to browse the repo, but also for other
things - but this I will explain in a subsequent post.
Jan
--
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Kaboutermansstraat 97, B-3000 Leuven, Belgium
From Python to silicon:
http://myhdl.jandecaluwe.com
|
|
From: Blubaugh, D. A. <dbl...@be...> - 2008-05-22 19:41:43
|
Dear Sir, My question still has not been answered. Will there be any development as far as dynamic data typing is concerned? Such as between an integer and a complex number within complex arithmetic? Thanks, David -----Original Message----- From: myh...@li... [mailto:myh...@li...] On Behalf Of Brendan Rankin Sent: Thursday, May 22, 2008 2:10 PM To: myh...@li... Subject: Re: [myhdl-list] Dynamic data type Blubaugh, David A. <dblubaugh <at> belcan.com> writes: > To Whom It May Concern, > > I was wondering that if one were to include floating-point support for > MyHDL by developing a support module for such number processing. I was wondering if MYHDL will be able to handle dynamic data type processing. Such as if I were to multiply a complex number (real and complex values are integers) with a floating point number and then finally dividing with an integer number. Will MYHDL and or python be able to handle the multiple different data types to create a final result of a floating-point complex number. Has anyone out there done any relevant work on this topic that will allow for myhdl to create synthesizable Verilog, that handles these multiple variable data type processing?? > Thanks, > > David Blubaugh Hi David, Including direct support for floating point conversion doesn't make sense. Floating point implementations tend to be architecture (device) specific. Anything that attempts to be generic would not be what people want anyway. What might make sense is something that helps you to convert your floating point algorithms to fixed point, though I'm not convinced that it should be a part of MyHDL. MyHDL should to being an excellent HDL experimentation and generation tool. Along the lines of floating-to-fixed conversion, I found this online: http://users.ece.utexas.edu/~bevans/projects/wordlength/converter/index. html Tom Dillon's company also has some pretty good information on this topic: http://www.dilloneng.com/ingenuity/fixed-vs-floating-point Cheers, - Brendan ------------------------------------------------------------------------ - This SF.net email is sponsored by: Microsoft Defy all challenges. Microsoft(R) Visual Studio 2008. http://clk.atdmt.com/MRT/go/vse0120000070mrt/direct/01/ _______________________________________________ myhdl-list mailing list myh...@li... https://lists.sourceforge.net/lists/listinfo/myhdl-list This e-mail transmission contains information that is confidential and may be privileged. It is intended only for the addressee(s) named above. If you receive this e-mail in error, please do not read, copy or disseminate it in any manner. If you are not the intended recipient, any disclosure, copying, distribution or use of the contents of this information is prohibited. Please reply to the message immediately by informing the sender that the message was misdirected. After replying, please erase it from your computer system. Your assistance in correcting this error is appreciated. |
|
From: Brendan R. <bre...@gm...> - 2008-05-22 18:10:46
|
Blubaugh, David A. <dblubaugh <at> belcan.com> writes: > To Whom It May Concern, > > I was wondering that if one were to include floating-point support for MyHDL by developing a support module for such number processing. I was wondering if MYHDL will be able to handle dynamic data type processing. Such as if I were to multiply a complex number (real and complex values are integers) with a floating point number and then finally dividing with an integer number. Will MYHDL and or python be able to handle the multiple different data types to create a final result of a floating-point complex number. Has anyone out there done any relevant work on this topic that will allow for myhdl to create synthesizable Verilog, that handles these multiple variable data type processing?? > Thanks, > > David Blubaugh Hi David, Including direct support for floating point conversion doesn't make sense. Floating point implementations tend to be architecture (device) specific. Anything that attempts to be generic would not be what people want anyway. What might make sense is something that helps you to convert your floating point algorithms to fixed point, though I'm not convinced that it should be a part of MyHDL. MyHDL should to being an excellent HDL experimentation and generation tool. Along the lines of floating-to-fixed conversion, I found this online: http://users.ece.utexas.edu/~bevans/projects/wordlength/converter/index.html Tom Dillon's company also has some pretty good information on this topic: http://www.dilloneng.com/ingenuity/fixed-vs-floating-point Cheers, - Brendan |
|
From: Christopher F. <cf...@uc...> - 2008-05-20 20:16:22
|
MyHDL will only convert intbv (maybe others?) data types currently. It wouldn't support what you are suggesting. There seems to be 2 different methods in your comments, 1. Implementing support in MyHDL to handle complex data types 2. Building models for the different complex data types. I believe from previous posts method 1 was encouraged to be a separate tool that utilizes MyHDL but not built into MyHDL, leaving MyHDL as an RTL language. Method 2 would be a collections of floating-point modules etc implemented in MyHDL. On Tue, 20 May 2008 15:46:54 -0400 "Blubaugh, David A." <dbl...@be...> wrote: > To Whom It May Concern, > > > I was wondering that if one were to include floating-point support >for > MyHDL by developing a support module for such number processing. I >was > wondering if MYHDL will be able to handle dynamic data type >processing. > Such as if I were to multiply a complex number (real and complex >values > are integers) with a floating point number and then finally dividing > with an integer number. Will MYHDL and or python be able to handle >the > multiple different data types to create a final result of a > floating-point complex number. Has anyone out there done any >relevant > work on this topic that will allow for myhdl to create synthesizable > Verilog, that handles these multiple variable data type processing?? > > > > Thanks, > > > David Blubaugh > > > > > This e-mail transmission contains information that is confidential >and may be > privileged. It is intended only for the addressee(s) named above. If >you receive > this e-mail in error, please do not read, copy or disseminate it in >any manner. > If you are not the intended recipient, any disclosure, copying, >distribution or > use of the contents of this information is prohibited. Please reply >to the > message immediately by informing the sender that the message was >misdirected. > After replying, please erase it from your computer system. Your >assistance in > correcting this error is appreciated. > |
|
From: Blubaugh, D. A. <dbl...@be...> - 2008-05-20 19:47:04
|
To Whom It May Concern, I was wondering that if one were to include floating-point support for MyHDL by developing a support module for such number processing. I was wondering if MYHDL will be able to handle dynamic data type processing. Such as if I were to multiply a complex number (real and complex values are integers) with a floating point number and then finally dividing with an integer number. Will MYHDL and or python be able to handle the multiple different data types to create a final result of a floating-point complex number. Has anyone out there done any relevant work on this topic that will allow for myhdl to create synthesizable Verilog, that handles these multiple variable data type processing?? Thanks, David Blubaugh This e-mail transmission contains information that is confidential and may be privileged. It is intended only for the addressee(s) named above. If you receive this e-mail in error, please do not read, copy or disseminate it in any manner. If you are not the intended recipient, any disclosure, copying, distribution or use of the contents of this information is prohibited. Please reply to the message immediately by informing the sender that the message was misdirected. After replying, please erase it from your computer system. Your assistance in correcting this error is appreciated. |
|
From: Jon C. <jo...@ho...> - 2008-05-15 13:18:07
|
Yes, it shows the same problem. This is a real bummer for me because I tried a previous version and it crashed when I tried to bring this particular signal up. From: cf...@uc... To: myh...@li... Date: Wed, 14 May 2008 19:57:52 -0600 Subject: Re: [myhdl-list] Displaying Finite State Machine States I attached the VCD file that displayed correctly with 3.0.2. Try loading this VCD in your version, 3.1.6 and see if it displays correctly. If not it maybe a version issue. _________________________________________________________________ Stay in touch when you're away with Windows Live Messenger. http://www.windowslive.com/messenger/overview.html?ocid=TXT_TAGLM_WL_Refresh_messenger_052008 |
|
From: Christopher L. F. <cf...@uc...> - 2008-05-15 01:57:54
|
I attached the VCD file that displayed correctly with 3.0.2. Try loading this VCD in your version, 3.1.6 and see if it displays correctly. If not it maybe a version issue. On May 14, 2008, at 7:13 PM, Jon Choy wrote: > > According to the myhdl examples on FSM, I should be able to > display the states as strings within gtkwave. I'm using version > 3.1.6 and it just displays a bunch of question marks. I tried > messing with the data formats and it doesn't seem to make a > difference. I ran my own code as well as the fsm.py example and I > still get the same result. Is there a particular trick I need to use > to get the states to display like the manual's examples. > > Jon > > > > > > > Windows Live SkyDrive lets you share files with faraway friends. > Start sharing. > ------------------------------------------------------------------------- > This SF.net email is sponsored by: Microsoft > Defy all challenges. Microsoft(R) Visual Studio 2008. > http://clk.atdmt.com/MRT/go/vse0120000070mrt/direct/01/_______________________________________________ > myhdl-list mailing list > myh...@li... > https://lists.sourceforge.net/lists/listinfo/myhdl-list |
|
From: Christopher L. F. <cf...@uc...> - 2008-05-15 01:52:24
|
I took the example from the manual, and using gtkwave 3.0.2 the enumerated types were displayed. On May 14, 2008, at 7:13 PM, Jon Choy wrote: > > According to the myhdl examples on FSM, I should be able to > display the states as strings within gtkwave. I'm using version > 3.1.6 and it just displays a bunch of question marks. I tried > messing with the data formats and it doesn't seem to make a > difference. I ran my own code as well as the fsm.py example and I > still get the same result. Is there a particular trick I need to use > to get the states to display like the manual's examples. > > Jon > > > > > > > Windows Live SkyDrive lets you share files with faraway friends. > Start sharing. > ------------------------------------------------------------------------- > This SF.net email is sponsored by: Microsoft > Defy all challenges. Microsoft(R) Visual Studio 2008. > http://clk.atdmt.com/MRT/go/vse0120000070mrt/direct/01/_______________________________________________ > myhdl-list mailing list > myh...@li... > https://lists.sourceforge.net/lists/listinfo/myhdl-list |
|
From: Jon C. <jo...@ho...> - 2008-05-15 01:13:46
|
According to the myhdl examples on FSM, I should be able to display the states as strings within gtkwave. I'm using version 3.1.6 and it just displays a bunch of question marks. I tried messing with the data formats and it doesn't seem to make a difference. I ran my own code as well as the fsm.py example and I still get the same result. Is there a particular trick I need to use to get the states to display like the manual's examples. Jon _________________________________________________________________ Windows Live SkyDrive lets you share files with faraway friends. http://www.windowslive.com/skydrive/overview.html?ocid=TXT_TAGLM_WL_Refresh_skydrive_052008 |
|
From: Christopher L. F. <cf...@uc...> - 2008-05-09 12:15:42
|
> > To solve the problem fundamentally, there are some options. MyHDL > could give > an error if a sequence of generators contains other things. Probably > we should > limit this to special kinds of hardware-oriented generators, the > ones created > by MyHDL decorators. Or MyHDL could "filter" return values and throw > out > what it doesn't like. I think I prefer the first option. I would agree, the first solution (MyHDL checks the returned generators) makes more sense than filter. During simulation and conversion the other outputs would be useless in any case. |
|
From: Jan D. <ja...@ja...> - 2008-05-09 07:35:41
|
Oystein Homelien wrote:
> On Wed, 7 May 2008, Jan Decaluwe wrote:
>
>
>>I'm trying to understand your example:
>
>
> Thanks for the quick reply! I really appreciate it. Was a little scared
> since there has been little activity on the list..
>
>
>>- I see that wb is passed as a parameter, but also returned by the
>>module. Why is that necessary?
>
>
> I return wb to avoid an extra line in the main module, "powersoc";
>
> i_uart, wb_uart = uart.uart(wb.slave(0xC), baudclk, rxd, txd) # moving
> this up fixed stuff
Ok, this is the problem. When, in the uart, you say:
return (registers, transmitter), wb
the result is no longer a "sequence of generators". MyHDL uses this to decide whether
or not the function represents hardware or not. The problem is that the uart is
silently ignored during hierarchy extraction.
Workaround:
in uart.py:
return (registers, transmitter)
in powersoc:
wb_uart = wb.slave(0xC)
i_uart = uart.uart(wb_uart, baudclk, rxd, txd) # moving this up fixed stuff
To solve the problem fundamentally, there are some options. MyHDL could give
an error if a sequence of generators contains other things. Probably we should
limit this to special kinds of hardware-oriented generators, the ones created
by MyHDL decorators. Or MyHDL could "filter" return values and throw out
what it doesn't like. I think I prefer the first option.
Jan
--
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Kaboutermansstraat 97, B-3000 Leuven, Belgium
From Python to silicon:
http://myhdl.jandecaluwe.com
|
|
From: Oystein H. <oy...@ho...> - 2008-05-08 15:13:36
|
On Wed, 7 May 2008, Jan Decaluwe wrote:
> I'm trying to understand your example:
Thanks for the quick reply! I really appreciate it. Was a little scared
since there has been little activity on the list..
> - I see that wb is passed as a parameter, but also returned by the
> module. Why is that necessary?
I return wb to avoid an extra line in the main module, "powersoc";
i_uart, wb_uart = uart.uart(wb.slave(0xC), baudclk, rxd, txd) # moving
this up fixed stuff
wb.slave() is supposed to set up a slave wishbone instance with chip
select for the given major nibble, and for all modules I return the
wishbone bus as well as the instance itself so I can avoid typing:
wb_uart = wb.slave(0x0C)
iuart = uart.uart(wb_uart, ...)
It just seems clearer to me, but opinions may differ. Could this be the
problem, if I just skip returning it then it will work? Then why does it
work for all the other slaves:
i_rom, wb_rom = zpu.rom(wb.slave(0x0))
i_bram, wb_bram = hw.sram(wb.slave(0xF), sram)
i_debugreg, wb_debugreg = hw.debugreg(wb.slave(0xE), debugreg);
.. as expected (i think)? The design, prior to adding the uart, converts
and synthesizes.
> - what is wb? if it's a class instance, as suggested by the code, I don't
> understand how you get to converted code at all. I tried it, and toVerilog
> chokes on return values that are not generators or sequences of generators.
> Did you perhaps modify some of the code in _extractHierarchy.py?
It's a class instance so that I can avoid typing all the signal names
every time I change parts of the bus (see hw.py in my example). I find it
gives much clearer code to be able to pass class instances like this, the
only annoyance is that myhdl barfs on them during conversion so I have to
"explode" the buses in the top of the instance functions:
wb_rst_i, wb_clk_i, wb_adr_i, wb_dat_o, wb_dat_i, wb_we_i, wb_sel_i, wb_stb_i, wb_ack_o, wb_cyc_i
= wb.rst_i, wb.clk_i, wb.adr_i, wb.dat_o, wb.dat_i, wb.we_i, wb.sel_i, wb.stb_i, wb.ack_o, wb.cyc_i
I basically replace "." by "_". Is it possible MyHDL (convertible) might
support this usage pattern (without having to "explode" the buses) in the
future? I tried having a look at the code but it made little sense to me.
It is just for grouping of signals.
Regarding whether I modified myhdl, Yes I did try to remove an assertion
but nothing more. If you try my design ("python powersoc") on various
versions of myhdl you will see that it usually converts, but some versions
barf with an assertion on curlevel < -1 or something like that.
Sorry for not being more presice, I will look further into this when I get
home, just wanted to get your reactions on my thoughts above.
And thank you _very much_ for making MyHDL. I simply love it!
Oystein Homelien, CVO | oy...@po...
PowerTech Information Systems AS | http://www.powertech.no/
Nedre Slottsgate 5, N-0157 OSLO | tel: +47-2301-0010, fax: +47-2301-0001
|
|
From: Blubaugh, D. A. <dbl...@be...> - 2008-05-07 18:18:17
|
I am glad to see that there is still development for MyHDL. I was
concerned that development had expired, since I was not seeing any new
messages being posted on the MyHDL website. I was also wondering if it
would one day be possible if MyHDL would be a timeless Python, where all
the necessary timing issues would be automatically be handled by MyHDL
generator.
Thanks,
David Blubaugh
-----Original Message-----
From: myh...@li...
[mailto:myh...@li...] On Behalf Of Jan
Decaluwe
Sent: Wednesday, May 07, 2008 10:36 AM
To: myh...@li...
Subject: Re: [myhdl-list] Strange problem,VALUES instead of symbols
being toVerilog'ed
I'm trying to understand your example:
- I see that wb is passed as a parameter, but also returned by the
module. Why is that necessary?
- what is wb? if it's a class instance, as suggested by the code, I
don't understand how you get to converted code at all. I tried it, and
toVerilog chokes on return values that are not generators or sequences
of generators.
Did you perhaps modify some of the code in _extractHierarchy.py?
Jan
Oystein Homelien wrote:
> Hello, this is my first post although I have lurked for some time.
> First of all let me say that I simply love the idea of MyHDL. The
> simplicity and power of python, direct to synthesizable verilog code..
yummie!
>
> Second I must admit that I am a newbie, so be nice with me. I have
> done some stuff with MyHDL and stumbled upon some of its (or
> verilog's?) limitations wrt verilog conversion. So far I have been
> able to work around all of them, but now I am stuck.
>
> I am adding a myhdl "uart" module to my project. The instance is in
> the file uart.py, def uart(). Here's the start of it:
>
> def uart(wb, baudclk, rxd, txd):
> wb_rst_i, wb_clk_i, wb_adr_i, wb_dat_o, wb_dat_i, wb_we_i,
wb_sel_i, wb_stb_i, wb_ack_o, wb_cyc_i
> = wb.rst_i, wb.clk_i, wb.adr_i, wb.dat_o, wb.dat_i, wb.we_i,
> wb.sel_i, wb.stb_i, wb.ack_o, wb.cyc_i ;
> char = Signal(bool(0));
> send = Signal(bool(0));
> sending = Signal(bool(0));
> send_done = Signal(bool(0));
>
> @always(wb_clk_i.posedge)
> def registers():
> wb_ack_o.next = False
> if wb_cyc_i:
> if wb_we_i:
> char.next = wb_dat_i
> send.next = True
> else:
> wb_dat_o.next = concat(intbv(0x11)[5:], rxd, send,
sending)
> wb_ack_o.next = True
>
> .. as you can see I am "exploding" a wishbone bus in the beginning,
> and then declaring some internal registers (at least this is what I am
> trying to do). But, registers() is converted into the following
verilog:
>
> always @(posedge wb_clk_i) begin: POWERSOC_I_UART_0
> uart_ack_o <= 0;
> if (uart_cyc_i) begin
> if (wb_we_o) begin
> False <= wb_dat_o; <-- LOOK HERE
> False <= 1; <-- AND HERE
> end
> else begin
> uart_dat_o <= {5'h11, rxd, False, False}; <-- AND HERE
> end
> uart_ack_o <= 1;
> end
> end
>
> .. it seems as though the _values_ of my vars are being written to
> verilog instead of the symbol names. What am I doing wrong? It only
> happens with the uart, and I have tried all kinds of strange things to
> make it work. Of course this does not synthesize (i use Xilinx'
> tools). :-)
>
> I have put a zip file with design files for you to try yourself
> (./powersoc), at http://home.powertech.no/oystein/myhdl-bug1.zip .
>
> For the record, I have tried it with the following myhdl versions:
>
> drwxr-xr-x 8 oystein oystein 4096 2008-05-07 12:51 myhdl-0.5.1dev1
> -rw-r--r-- 1 oystein oystein 768032 2008-05-07 12:50
myhdl-0.5.1dev1.tar.gz
> drwxr-xr-x 7 oystein oystein 4096 2008-05-07 12:48 myhdl-0.5c1
> -rw-r--r-- 1 oystein oystein 760268 2008-05-07 12:47
myhdl-0.5c1.tar.gz
> drwxr-xr-x 6 oystein oystein 4096 2008-05-07 12:47 myhdl-0.6dev6
> -rw-r--r-- 1 oystein oystein 156404 2008-05-07 12:46
myhdl-0.6dev6.tar.gz
> drwxr-xr-x 6 oystein oystein 4096 2008-05-07 10:24 myhdl-0.6dev8
> -rw-r--r-- 1 oystein oystein 181734 2008-05-07 10:23
> myhdl-0.6dev8.tar.gz
>
> .. i could not get it working. Hope to get some input on how to work
> around this.
>
> yours,
> oystein
>
>
> ----------------------------------------------------------------------
> --- This SF.net email is sponsored by the 2008 JavaOne(SM) Conference
> Don't miss this year's exciting event. There's still time to save
$100.
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--
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Kaboutermansstraat 97, B-3000 Leuven, Belgium
From Python to silicon:
http://myhdl.jandecaluwe.com
------------------------------------------------------------------------
-
This SF.net email is sponsored by the 2008 JavaOne(SM) Conference
Don't miss this year's exciting event. There's still time to save $100.
Use priority code J8TL2D2.
http://ad.doubleclick.net/clk;198757673;13503038;p?http://java.sun.com/j
avaone
_______________________________________________
myhdl-list mailing list
myh...@li...
https://lists.sourceforge.net/lists/listinfo/myhdl-list
This e-mail transmission contains information that is confidential and may be
privileged. It is intended only for the addressee(s) named above. If you receive
this e-mail in error, please do not read, copy or disseminate it in any manner.
If you are not the intended recipient, any disclosure, copying, distribution or
use of the contents of this information is prohibited. Please reply to the
message immediately by informing the sender that the message was misdirected.
After replying, please erase it from your computer system. Your assistance in
correcting this error is appreciated.
|
|
From: Jan D. <ja...@ja...> - 2008-05-07 15:34:41
|
I'm trying to understand your example:
- I see that wb is passed as a parameter, but also returned by the
module. Why is that necessary?
- what is wb? if it's a class instance, as suggested by the code, I don't
understand how you get to converted code at all. I tried it, and toVerilog
chokes on return values that are not generators or sequences of generators.
Did you perhaps modify some of the code in _extractHierarchy.py?
Jan
Oystein Homelien wrote:
> Hello, this is my first post although I have lurked for some time. First
> of all let me say that I simply love the idea of MyHDL. The simplicity
> and power of python, direct to synthesizable verilog code.. yummie!
>
> Second I must admit that I am a newbie, so be nice with me. I have done
> some stuff with MyHDL and stumbled upon some of its (or verilog's?)
> limitations wrt verilog conversion. So far I have been able to work
> around all of them, but now I am stuck.
>
> I am adding a myhdl "uart" module to my project. The instance is in the
> file uart.py, def uart(). Here's the start of it:
>
> def uart(wb, baudclk, rxd, txd):
> wb_rst_i, wb_clk_i, wb_adr_i, wb_dat_o, wb_dat_i, wb_we_i, wb_sel_i, wb_stb_i, wb_ack_o, wb_cyc_i
> = wb.rst_i, wb.clk_i, wb.adr_i, wb.dat_o, wb.dat_i, wb.we_i, wb.sel_i, wb.stb_i, wb.ack_o, wb.cyc_i
> ;
> char = Signal(bool(0));
> send = Signal(bool(0));
> sending = Signal(bool(0));
> send_done = Signal(bool(0));
>
> @always(wb_clk_i.posedge)
> def registers():
> wb_ack_o.next = False
> if wb_cyc_i:
> if wb_we_i:
> char.next = wb_dat_i
> send.next = True
> else:
> wb_dat_o.next = concat(intbv(0x11)[5:], rxd, send, sending)
> wb_ack_o.next = True
>
> .. as you can see I am "exploding" a wishbone bus in the beginning, and
> then declaring some internal registers (at least this is what I am trying
> to do). But, registers() is converted into the following verilog:
>
> always @(posedge wb_clk_i) begin: POWERSOC_I_UART_0
> uart_ack_o <= 0;
> if (uart_cyc_i) begin
> if (wb_we_o) begin
> False <= wb_dat_o; <-- LOOK HERE
> False <= 1; <-- AND HERE
> end
> else begin
> uart_dat_o <= {5'h11, rxd, False, False}; <-- AND HERE
> end
> uart_ack_o <= 1;
> end
> end
>
> .. it seems as though the _values_ of my vars are being written to verilog
> instead of the symbol names. What am I doing wrong? It only happens with
> the uart, and I have tried all kinds of strange things to make it work. Of
> course this does not synthesize (i use Xilinx' tools). :-)
>
> I have put a zip file with design files for you to try yourself
> (./powersoc), at http://home.powertech.no/oystein/myhdl-bug1.zip .
>
> For the record, I have tried it with the following myhdl versions:
>
> drwxr-xr-x 8 oystein oystein 4096 2008-05-07 12:51 myhdl-0.5.1dev1
> -rw-r--r-- 1 oystein oystein 768032 2008-05-07 12:50 myhdl-0.5.1dev1.tar.gz
> drwxr-xr-x 7 oystein oystein 4096 2008-05-07 12:48 myhdl-0.5c1
> -rw-r--r-- 1 oystein oystein 760268 2008-05-07 12:47 myhdl-0.5c1.tar.gz
> drwxr-xr-x 6 oystein oystein 4096 2008-05-07 12:47 myhdl-0.6dev6
> -rw-r--r-- 1 oystein oystein 156404 2008-05-07 12:46 myhdl-0.6dev6.tar.gz
> drwxr-xr-x 6 oystein oystein 4096 2008-05-07 10:24 myhdl-0.6dev8
> -rw-r--r-- 1 oystein oystein 181734 2008-05-07 10:23 myhdl-0.6dev8.tar.gz
>
> .. i could not get it working. Hope to get some input on how to work
> around this.
>
> yours,
> oystein
>
>
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--
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Kaboutermansstraat 97, B-3000 Leuven, Belgium
From Python to silicon:
http://myhdl.jandecaluwe.com
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