myhdl-list — Mailing list for discussions on MyHDL

Re: [myhdl-list] Programmable LFSR

[Christopher F. <chr...@gm...>]

You are now creating the constant / static bit-vector during the 
elaboration phase (elaboration is great cause you can use all of 
Python's power).  I think the issue is, the constant bit-vector exists 
but what is the hardware representation of the "bitvector".  Kinda like 
the RAM/ROM modules you posted about earlier.  I believe there still 
needs to be some component for the bitvector, need a signal and possibly 
addition generator that describes what bitvector (or corresponding 
signal) is.

First need a signal for the bitvector

sbit = Signal(bitvector)

Instead of if bitvectore[i], use if sbit[i]

And possibly some behavioral definition that states what the sbit is in 
hardware (register, combo constants, etc).  Example make it a register

@always(clk.posedge)
def rtl_bitvector_reg():
    if rst:
        sbit.next = bitvector
  

I didn't test this but hopefully this will helps

Chris

Joseph Cali wrote:
> I tried to use the bitvector approach, but I am not getting a new 
> error. I think that I am not using the intbv class correctly in some 
> cases, as I have seen this error pop up several times in other MyHDL 
> generators that I have written.  I also should note that I am using 
> the most recent MyHDL from the mercurial repository.  
>
> Here is the code
> ---------------------------------------------------------------------
>
> def Galois(out, clk, rst, width=32):
> '''
> Implement a Galois Linear Feedback Shift Register (LFSR).
>
> Parameters
> ----------
> width : integer
> The length of the LFSR
>
> Input Ports
> -----------
> clk : The clock
> rst : Active high reset
>
>
> Output Ports
> ------------
> out : Pseudo-Random word
> '''
> sel_table = width - 3
> polynomial = GALOIS_TABLE[sel_table]
> polynomial = polynomial[1:len(polynomial)-1]
> bitvector = intbv(0)[width:]
> for i in range(0, width):
> if i in polynomial:
> bitvector[i] = 1
> else:
> bitvector[i] = 0
>
>
>
> state = Signal(intbv(0)[width:])
>
> @always(clk.posedge, rst)
> def logic():
> if rst == 1:
> state.next[0] = 1
> else:
> state.next[width-1] = state[0]
> for i in downrange(width-1, 0):
> if bitvector[i]:
> state.next[i] = state[i+1] ^ state[0]
> else:
> state.next[i] = state[i+1]
>

> Joseph
>
>
>
> On Jul 20, 2009, at 4:16 AM, Jan Decaluwe wrote:
>
>> Syntax
>>
>>   if in ...
>>
>> is indeed not supported. This is currently not checked, hence the bad
>> stack trace instead of a clear error message.
>>
>> As a workaround, map the polynomial to a bitvector with the significant
>> bits set before using it inside a generator. Then you can use
>>
>>   if polynomial[i] ...
>>
>> as the check.
>>
>> Probably you mean state.next[i], not state[i].next.
>>
>> All code inside a generator is converted literally, so you will
>> get a for-loop in the output.
>>
>> Jan
>>
>>
>> Joseph Cali wrote:
>>> I am attempting to parameterize the creation of Galois LFSRs.  I 
>>> have a table that contains Galois polynomials (a list of tuples 
>>> named GALOIS_TABLE).  The following is my first attempt at a 
>>> solution in MyHDL.
>>>
>>> def Galois(out, clk, rst, width=32):
>>> '''
>>> Implement a Galois Linear Feedback Shift Register (LFSR).
>>>
>>> Parameters
>>> ----------
>>> width : integer
>>> The length of the LFSR
>>>
>>> Input Ports
>>> -----------
>>> clk : The clock
>>> rst : Active high reset
>>>
>>> Output Ports
>>> ------------
>>> out : Pseudo-Random word
>>> '''
>>> sel_table = width - 3
>>> polynomial = GALOIS_TABLE[sel_table]
>>> polynomial = polynomial[1:len(polynomial)-1]  # Take the relevant 
>>> part of the polynomial
>>>
>>> state = Signal(intbv(0)[width:])
>>>
>>> @always(clk.posedge, rst.negedge)
>>> def logic():
>>> if rst == 1:
>>> state.next[0] = 1
>>> else:
>>> state.next[width-1] = state[0]
>>> for i in downrange(width-1, 0):
>>> if i in polynomial:  # This is where the problem occurs, I believe
>>> state[i].next = state[i+1] ^ state[0]
>>> else:
>>> state[i].next = state[i+1]
>>>
>>> @always_comb
>>> def assignments():
>>> out.next = state
>>>
>>> return logic, assignments
>>>
>>>
>>> --------------------------------------------------------------------------------------------------------------------
>>> I do not think the "if i in whatever" syntax is convertible.  I was 
>>> wondering if anyone had any
>>> suggestions on alternative Python code that would yield a 
>>> convertible example.  Attempting
>>> to convert the above code gives the following stack trace using 
>>> Python 2.6.2:
>>>
>>>  File "galois.py", line 147, in <module>
>>>    galois = toVerilog(Galois, out, clk, rst, width=18)
>>>  File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py", 
>>> line 124, in __call__
>>>    _convertGens(genlist, vfile)
>>>  File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py", 
>>> line 321, in _convertGens
>>>    v.visit(tree)
>>>  File "/usr/lib/python2.6/ast.py", line 231, in visit
>>>    return visitor(node)
>>>  File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py", 
>>> line 1248, in visit_Module
>>>    self.visit(stmt)
>>>  File "/usr/lib/python2.6/ast.py", line 231, in visit
>>>    return visitor(node)
>>>  File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py", 
>>> line 1850, in visit_FunctionDef
>>>    self.visit_stmt(node.body)
>>>  File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py", 
>>> line 1599, in visit_stmt
>>>    self.visit(stmt)
>>>  File "/usr/lib/python2.6/ast.py", line 231, in visit
>>>    return visitor(node)
>>>  File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py", 
>>> line 1177, in visit_If
>>>    self.mapToIf(node)
>>>  File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py", 
>>> line 1232, in mapToIf
>>>    self.visit_stmt(node.else_)
>>>  File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py", 
>>> line 1599, in visit_stmt
>>>    self.visit(stmt)
>>>  File "/usr/lib/python2.6/ast.py", line 231, in visit
>>>    return visitor(node)
>>>  File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py", 
>>> line 1140, in visit_For
>>>    self.visit_stmt(node.body)
>>>  File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py", 
>>> line 1599, in visit_stmt
>>>    self.visit(stmt)
>>>  File "/usr/lib/python2.6/ast.py", line 231, in visit
>>>    return visitor(node)
>>>  File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py", 
>>> line 1177, in visit_If
>>>    self.mapToIf(node)
>>>  File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py", 
>>> line 1221, in mapToIf
>>>    self.visit(test)
>>>  File "/usr/lib/python2.6/ast.py", line 231, in visit
>>>    return visitor(node)
>>>  File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py", 
>>> line 969, in visit_Compare
>>>    self.write(" %s " % opmap[type(node.ops[0])])
>>> KeyError: <class '_ast.In'>
>>>
>>>
>>> --------------------------------------------------------------------------------------------------------------------
>>> For width=18,  a Galois polynomial is x^18 + x^11 + 1.  The target
>>> Verilog should behave as below:
>>>
>>> module galois18(state, clk, rst);
>>> input clk;
>>> input rst;
>>> output [17:0] state;
>>> reg [17:0] state;
>>>
>>> always @(posedge clk) begin
>>> if(~rst) begin
>>> state <= {state[0], state[17:12], state[11]^state[0], state[10:1]};
>>> end
>>> else begin
>>> state[0] <= 1;
>>> end
>>> end
>>> endmodule
>>>
>>>
>>>
>>> Joseph
>>>
>>> ------------------------------------------------------------------------------
>>> Enter the BlackBerry Developer Challenge  
>>> This is your chance to win up to $100,000 in prizes! For a limited 
>>> time,
>>> vendors submitting new applications to BlackBerry App World(TM) will 
>>> have
>>> the opportunity to enter the BlackBerry Developer Challenge. See 
>>> full prize  
>>> details at: http://p.sf.net/sfu/Challenge
>>
>>
>> -- 
>> Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
>>    Python as a HDL: http://www.myhdl.org
>>    VHDL development, the modern way: http://www.sigasi.com
>>    Analog design automation: http://www.mephisto-da.com
>>    World-class digital design: http://www.easics.com
>>
>>
>> ------------------------------------------------------------------------------
>> Enter the BlackBerry Developer Challenge  
>> This is your chance to win up to $100,000 in prizes! For a limited time,
>> vendors submitting new applications to BlackBerry App World(TM) will have
>> the opportunity to enter the BlackBerry Developer Challenge. See full 
>> prize  
>> details at: http://p.sf.net/sfu/Challenge
>> _______________________________________________
>> myhdl-list mailing list
>> myh...@li... 
>> <mailto:myh...@li...>
>> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>
>
> Joseph Cali
> ca...@au... <mailto:ca...@au...>
> Graduate Research Assistant
> Auburn University
> Work:  334-844-8257

Re: [myhdl-list] Programmable LFSR

[Joseph C. <ca...@au...>]

I tried to use the bitvector approach, but I am not getting a new  
error. I think that I am not using the intbv class correctly in some  
cases, as I have seen this error pop up several times in other MyHDL  
generators that I have written.  I also should note that I am using  
the most recent MyHDL from the mercurial repository.

Here is the code
---------------------------------------------------------------------

def Galois(out, clk, rst, width=32):
	'''
	Implement a Galois Linear Feedback Shift Register (LFSR).

	Parameters
	----------
	width : integer
		The length of the LFSR

	Input Ports
	-----------
	clk : The clock
	rst : Active high reset
	
	Output Ports
	------------
	out : Pseudo-Random word
	'''
	sel_table = width - 3
	polynomial = GALOIS_TABLE[sel_table]
	polynomial = polynomial[1:len(polynomial)-1]
	bitvector = intbv(0)[width:]
	for i in range(0, width):
		if i in polynomial:
			bitvector[i] = 1
		else:
			bitvector[i] = 0
	

	state = Signal(intbv(0)[width:])

	@always(clk.posedge, rst)
	def logic():
		if rst == 1:
			state.next[0] = 1
		else:
			state.next[width-1] = state[0]
			for i in downrange(width-1, 0):
				if bitvector[i]:
					state.next[i] = state[i+1] ^ state[0]
				else:
					state.next[i] = state[i+1]



Here is the error (line 136 is the ``if bitvector[i]`` line)
---------------------------------------------------------------------
Traceback (most recent call last):
   File "galois.py", line 158, in <module>
     galois = toVerilog(Galois, out, clk, rst, width=18)
   File "/Users/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py",  
line 124, in __call__
     _convertGens(genlist, vfile)
   File "/Users/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py",  
line 321, in _convertGens
     v.visit(tree)
   File "/opt/local/Library/Frameworks/Python.framework/Versions/2.6/ 
lib/python2.6/ast.py", line 231, in visit
     return visitor(node)
   File "/Users/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py",  
line 1248, in visit_Module
     self.visit(stmt)
   File "/opt/local/Library/Frameworks/Python.framework/Versions/2.6/ 
lib/python2.6/ast.py", line 231, in visit
     return visitor(node)
   File "/Users/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py",  
line 1850, in visit_FunctionDef
     self.visit_stmt(node.body)
   File "/Users/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py",  
line 1599, in visit_stmt
     self.visit(stmt)
   File "/opt/local/Library/Frameworks/Python.framework/Versions/2.6/ 
lib/python2.6/ast.py", line 231, in visit
     return visitor(node)
   File "/Users/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py",  
line 1177, in visit_If
     self.mapToIf(node)
   File "/Users/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py",  
line 1232, in mapToIf
     self.visit_stmt(node.else_)
   File "/Users/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py",  
line 1599, in visit_stmt
     self.visit(stmt)
   File "/opt/local/Library/Frameworks/Python.framework/Versions/2.6/ 
lib/python2.6/ast.py", line 231, in visit
     return visitor(node)
   File "/Users/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py",  
line 1140, in visit_For
     self.visit_stmt(node.body)
   File "/Users/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py",  
line 1599, in visit_stmt
     self.visit(stmt)
   File "/opt/local/Library/Frameworks/Python.framework/Versions/2.6/ 
lib/python2.6/ast.py", line 231, in visit
     return visitor(node)
   File "/Users/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py",  
line 1177, in visit_If
     self.mapToIf(node)
   File "/Users/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py",  
line 1221, in mapToIf
     self.visit(test)
   File "/opt/local/Library/Frameworks/Python.framework/Versions/2.6/ 
lib/python2.6/ast.py", line 231, in visit
     return visitor(node)
   File "/Users/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py",  
line 1538, in visit_Subscript
     self.accessIndex(node)
   File "/Users/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py",  
line 1579, in accessIndex
     self.visit(node.value)
   File "/opt/local/Library/Frameworks/Python.framework/Versions/2.6/ 
lib/python2.6/ast.py", line 231, in visit
     return visitor(node)
   File "/Users/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py",  
line 1305, in visit_Name
     self.getName(node)
   File "/Users/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py",  
line 1346, in getName
     self.raiseError(node, _error.UnsupportedType, "%s, %s" % (n,  
type(obj)))
   File "/Users/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py",  
line 370, in raiseError
     raise ToVerilogError(kind, msg, info)
myhdl.ToVerilogError: in file galois.py, line 136:
     Object type is not supported in this context: bitvector, <class  
'myhdl._intbv.intbv'>

Joseph



On Jul 20, 2009, at 4:16 AM, Jan Decaluwe wrote:

> Syntax
>
>   if in ...
>
> is indeed not supported. This is currently not checked, hence the bad
> stack trace instead of a clear error message.
>
> As a workaround, map the polynomial to a bitvector with the  
> significant
> bits set before using it inside a generator. Then you can use
>
>   if polynomial[i] ...
>
> as the check.
>
> Probably you mean state.next[i], not state[i].next.
>
> All code inside a generator is converted literally, so you will
> get a for-loop in the output.
>
> Jan
>
>
> Joseph Cali wrote:
>> I am attempting to parameterize the creation of Galois LFSRs.  I  
>> have a table that contains Galois polynomials (a list of tuples  
>> named GALOIS_TABLE).  The following is my first attempt at a  
>> solution in MyHDL.
>>
>> def Galois(out, clk, rst, width=32):
>> 	'''
>> 	Implement a Galois Linear Feedback Shift Register (LFSR).
>>
>> 	Parameters
>> 	----------
>> 	width : integer
>> 		The length of the LFSR
>>
>> 	Input Ports
>> 	-----------
>> 	clk : The clock
>> 	rst : Active high reset
>> 	
>> 	Output Ports
>> 	------------
>> 	out : Pseudo-Random word
>> 	'''
>> 	sel_table = width - 3
>> 	polynomial = GALOIS_TABLE[sel_table]
>> 	polynomial = polynomial[1:len(polynomial)-1]  # Take the relevant  
>> part of the polynomial
>>
>> 	state = Signal(intbv(0)[width:])
>>
>> 	@always(clk.posedge, rst.negedge)
>> 	def logic():
>> 		if rst == 1:
>> 			state.next[0] = 1
>> 		else:
>> 			state.next[width-1] = state[0]
>> 			for i in downrange(width-1, 0):
>> 				if i in polynomial:  # This is where the problem occurs, I  
>> believe
>> 					state[i].next = state[i+1] ^ state[0]
>> 				else:
>> 					state[i].next = state[i+1]
>> 	
>> 	@always_comb
>> 	def assignments():
>> 		out.next = state		
>>
>> 	return logic, assignments
>>
>>
>> --------------------------------------------------------------------------------------------------------------------
>> I do not think the "if i in whatever" syntax is convertible.  I was  
>> wondering if anyone had any
>> suggestions on alternative Python code that would yield a  
>> convertible example.  Attempting
>> to convert the above code gives the following stack trace using  
>> Python 2.6.2:
>>
>>  File "galois.py", line 147, in <module>
>>    galois = toVerilog(Galois, out, clk, rst, width=18)
>>  File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py",  
>> line 124, in __call__
>>    _convertGens(genlist, vfile)
>>  File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py",  
>> line 321, in _convertGens
>>    v.visit(tree)
>>  File "/usr/lib/python2.6/ast.py", line 231, in visit
>>    return visitor(node)
>>  File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py",  
>> line 1248, in visit_Module
>>    self.visit(stmt)
>>  File "/usr/lib/python2.6/ast.py", line 231, in visit
>>    return visitor(node)
>>  File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py",  
>> line 1850, in visit_FunctionDef
>>    self.visit_stmt(node.body)
>>  File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py",  
>> line 1599, in visit_stmt
>>    self.visit(stmt)
>>  File "/usr/lib/python2.6/ast.py", line 231, in visit
>>    return visitor(node)
>>  File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py",  
>> line 1177, in visit_If
>>    self.mapToIf(node)
>>  File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py",  
>> line 1232, in mapToIf
>>    self.visit_stmt(node.else_)
>>  File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py",  
>> line 1599, in visit_stmt
>>    self.visit(stmt)
>>  File "/usr/lib/python2.6/ast.py", line 231, in visit
>>    return visitor(node)
>>  File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py",  
>> line 1140, in visit_For
>>    self.visit_stmt(node.body)
>>  File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py",  
>> line 1599, in visit_stmt
>>    self.visit(stmt)
>>  File "/usr/lib/python2.6/ast.py", line 231, in visit
>>    return visitor(node)
>>  File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py",  
>> line 1177, in visit_If
>>    self.mapToIf(node)
>>  File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py",  
>> line 1221, in mapToIf
>>    self.visit(test)
>>  File "/usr/lib/python2.6/ast.py", line 231, in visit
>>    return visitor(node)
>>  File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py",  
>> line 969, in visit_Compare
>>    self.write(" %s " % opmap[type(node.ops[0])])
>> KeyError: <class '_ast.In'>
>>
>>
>> --------------------------------------------------------------------------------------------------------------------
>> For width=18,  a Galois polynomial is x^18 + x^11 + 1.  The target
>> Verilog should behave as below:
>>
>> module galois18(state, clk, rst);
>> 	input clk;
>> 	input rst;
>> 	output [17:0] state;
>> 	reg [17:0] state;
>>
>> 	always @(posedge clk) begin
>> 		if(~rst) begin
>> 			state <= {state[0], state[17:12], state[11]^state[0],  
>> state[10:1]};
>> 		end
>> 		else begin
>> 			state[0] <= 1;
>> 		end
>> 	end
>> endmodule
>>
>>
>>
>> Joseph
>>
>> ------------------------------------------------------------------------------
>> Enter the BlackBerry Developer Challenge
>> This is your chance to win up to $100,000 in prizes! For a limited  
>> time,
>> vendors submitting new applications to BlackBerry App World(TM)  
>> will have
>> the opportunity to enter the BlackBerry Developer Challenge. See  
>> full prize
>> details at: http://p.sf.net/sfu/Challenge
>
>
> -- 
> Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
>    Python as a HDL: http://www.myhdl.org
>    VHDL development, the modern way: http://www.sigasi.com
>    Analog design automation: http://www.mephisto-da.com
>    World-class digital design: http://www.easics.com
>
>
> ------------------------------------------------------------------------------
> Enter the BlackBerry Developer Challenge
> This is your chance to win up to $100,000 in prizes! For a limited  
> time,
> vendors submitting new applications to BlackBerry App World(TM) will  
> have
> the opportunity to enter the BlackBerry Developer Challenge. See  
> full prize
> details at: http://p.sf.net/sfu/Challenge
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list


Joseph Cali
ca...@au...
Graduate Research Assistant
Auburn University
Work:  334-844-8257

Re: [myhdl-list] Programmable LFSR

[Jan D. <ja...@ja...>]

Syntax

   if in ...

is indeed not supported. This is currently not checked, hence the bad
stack trace instead of a clear error message.

As a workaround, map the polynomial to a bitvector with the significant
bits set before using it inside a generator. Then you can use

   if polynomial[i] ...

as the check.

Probably you mean state.next[i], not state[i].next.

All code inside a generator is converted literally, so you will
get a for-loop in the output.

Jan


Joseph Cali wrote:
> I am attempting to parameterize the creation of Galois LFSRs.  I have a table that contains Galois polynomials (a list of tuples named GALOIS_TABLE).  The following is my first attempt at a solution in MyHDL. 
> 
> def Galois(out, clk, rst, width=32):
> 	'''
> 	Implement a Galois Linear Feedback Shift Register (LFSR).
> 
> 	Parameters
> 	----------
> 	width : integer
> 		The length of the LFSR
> 
> 	Input Ports
> 	-----------
> 	clk : The clock
> 	rst : Active high reset
> 	
> 	Output Ports
> 	------------
> 	out : Pseudo-Random word
> 	'''
> 	sel_table = width - 3
> 	polynomial = GALOIS_TABLE[sel_table]
> 	polynomial = polynomial[1:len(polynomial)-1]  # Take the relevant part of the polynomial
> 
> 	state = Signal(intbv(0)[width:])
> 
> 	@always(clk.posedge, rst.negedge)
> 	def logic():
> 		if rst == 1:
> 			state.next[0] = 1
> 		else:
> 			state.next[width-1] = state[0]
> 			for i in downrange(width-1, 0):
> 				if i in polynomial:  # This is where the problem occurs, I believe
> 					state[i].next = state[i+1] ^ state[0]
> 				else:
> 					state[i].next = state[i+1]
> 	
> 	@always_comb
> 	def assignments():
> 		out.next = state		
> 
> 	return logic, assignments
> 
> 
> --------------------------------------------------------------------------------------------------------------------
> I do not think the "if i in whatever" syntax is convertible.  I was wondering if anyone had any
> suggestions on alternative Python code that would yield a convertible example.  Attempting
> to convert the above code gives the following stack trace using Python 2.6.2:
> 
>   File "galois.py", line 147, in <module>
>     galois = toVerilog(Galois, out, clk, rst, width=18)
>   File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py", line 124, in __call__
>     _convertGens(genlist, vfile)
>   File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py", line 321, in _convertGens
>     v.visit(tree)
>   File "/usr/lib/python2.6/ast.py", line 231, in visit
>     return visitor(node)
>   File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py", line 1248, in visit_Module
>     self.visit(stmt)
>   File "/usr/lib/python2.6/ast.py", line 231, in visit
>     return visitor(node)
>   File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py", line 1850, in visit_FunctionDef
>     self.visit_stmt(node.body)
>   File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py", line 1599, in visit_stmt
>     self.visit(stmt)
>   File "/usr/lib/python2.6/ast.py", line 231, in visit
>     return visitor(node)
>   File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py", line 1177, in visit_If
>     self.mapToIf(node)
>   File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py", line 1232, in mapToIf
>     self.visit_stmt(node.else_)
>   File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py", line 1599, in visit_stmt
>     self.visit(stmt)
>   File "/usr/lib/python2.6/ast.py", line 231, in visit
>     return visitor(node)
>   File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py", line 1140, in visit_For
>     self.visit_stmt(node.body)
>   File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py", line 1599, in visit_stmt
>     self.visit(stmt)
>   File "/usr/lib/python2.6/ast.py", line 231, in visit
>     return visitor(node)
>   File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py", line 1177, in visit_If
>     self.mapToIf(node)
>   File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py", line 1221, in mapToIf
>     self.visit(test)
>   File "/usr/lib/python2.6/ast.py", line 231, in visit
>     return visitor(node)
>   File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py", line 969, in visit_Compare
>     self.write(" %s " % opmap[type(node.ops[0])])
> KeyError: <class '_ast.In'>
> 
> 
> --------------------------------------------------------------------------------------------------------------------
> For width=18,  a Galois polynomial is x^18 + x^11 + 1.  The target 
> Verilog should behave as below:
> 
> module galois18(state, clk, rst);
> 	input clk;
> 	input rst;
> 	output [17:0] state;
> 	reg [17:0] state;
> 
> 	always @(posedge clk) begin
> 		if(~rst) begin
> 			state <= {state[0], state[17:12], state[11]^state[0], state[10:1]};
> 		end
> 		else begin
> 			state[0] <= 1;
> 		end
> 	end
> endmodule
> 
> 
> 
> Joseph
> 
> ------------------------------------------------------------------------------
> Enter the BlackBerry Developer Challenge  
> This is your chance to win up to $100,000 in prizes! For a limited time, 
> vendors submitting new applications to BlackBerry App World(TM) will have
> the opportunity to enter the BlackBerry Developer Challenge. See full prize  
> details at: http://p.sf.net/sfu/Challenge


-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
    Python as a HDL: http://www.myhdl.org
    VHDL development, the modern way: http://www.sigasi.com
    Analog design automation: http://www.mephisto-da.com
    World-class digital design: http://www.easics.com

[myhdl-list] Programmable LFSR

[Joseph C. <ca...@au...>]

I am attempting to parameterize the creation of Galois LFSRs.  I have a table that contains Galois polynomials (a list of tuples named GALOIS_TABLE).  The following is my first attempt at a solution in MyHDL. 

def Galois(out, clk, rst, width=32):
	'''
	Implement a Galois Linear Feedback Shift Register (LFSR).

	Parameters
	----------
	width : integer
		The length of the LFSR

	Input Ports
	-----------
	clk : The clock
	rst : Active high reset
	
	Output Ports
	------------
	out : Pseudo-Random word
	'''
	sel_table = width - 3
	polynomial = GALOIS_TABLE[sel_table]
	polynomial = polynomial[1:len(polynomial)-1]  # Take the relevant part of the polynomial

	state = Signal(intbv(0)[width:])

	@always(clk.posedge, rst.negedge)
	def logic():
		if rst == 1:
			state.next[0] = 1
		else:
			state.next[width-1] = state[0]
			for i in downrange(width-1, 0):
				if i in polynomial:  # This is where the problem occurs, I believe
					state[i].next = state[i+1] ^ state[0]
				else:
					state[i].next = state[i+1]
	
	@always_comb
	def assignments():
		out.next = state		

	return logic, assignments


--------------------------------------------------------------------------------------------------------------------
I do not think the "if i in whatever" syntax is convertible.  I was wondering if anyone had any
suggestions on alternative Python code that would yield a convertible example.  Attempting
to convert the above code gives the following stack trace using Python 2.6.2:

  File "galois.py", line 147, in <module>
    galois = toVerilog(Galois, out, clk, rst, width=18)
  File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py", line 124, in __call__
    _convertGens(genlist, vfile)
  File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py", line 321, in _convertGens
    v.visit(tree)
  File "/usr/lib/python2.6/ast.py", line 231, in visit
    return visitor(node)
  File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py", line 1248, in visit_Module
    self.visit(stmt)
  File "/usr/lib/python2.6/ast.py", line 231, in visit
    return visitor(node)
  File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py", line 1850, in visit_FunctionDef
    self.visit_stmt(node.body)
  File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py", line 1599, in visit_stmt
    self.visit(stmt)
  File "/usr/lib/python2.6/ast.py", line 231, in visit
    return visitor(node)
  File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py", line 1177, in visit_If
    self.mapToIf(node)
  File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py", line 1232, in mapToIf
    self.visit_stmt(node.else_)
  File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py", line 1599, in visit_stmt
    self.visit(stmt)
  File "/usr/lib/python2.6/ast.py", line 231, in visit
    return visitor(node)
  File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py", line 1140, in visit_For
    self.visit_stmt(node.body)
  File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py", line 1599, in visit_stmt
    self.visit(stmt)
  File "/usr/lib/python2.6/ast.py", line 231, in visit
    return visitor(node)
  File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py", line 1177, in visit_If
    self.mapToIf(node)
  File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py", line 1221, in mapToIf
    self.visit(test)
  File "/usr/lib/python2.6/ast.py", line 231, in visit
    return visitor(node)
  File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py", line 969, in visit_Compare
    self.write(" %s " % opmap[type(node.ops[0])])
KeyError: <class '_ast.In'>


--------------------------------------------------------------------------------------------------------------------
For width=18,  a Galois polynomial is x^18 + x^11 + 1.  The target 
Verilog should behave as below:

module galois18(state, clk, rst);
	input clk;
	input rst;
	output [17:0] state;
	reg [17:0] state;

	always @(posedge clk) begin
		if(~rst) begin
			state <= {state[0], state[17:12], state[11]^state[0], state[10:1]};
		end
		else begin
			state[0] <= 1;
		end
	end
endmodule



Joseph

Re: [myhdl-list] simulation semantics

[Jan D. <ja...@ja...>]

Geoffrey Brown wrote:
> I've been creating little examples to see if I understand the semantics 
> of myhdl. 
>  I came across one where the behavior differs completely depending
> upon the initial value of a signal (no problem there), but the generated 
> verilog
> is identical 

There is an issue with initial values and conversion, and it's
listed as an open task. For more info:

http://www.myhdl.org/doku.php/dev:tasks#initial_values_support


-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
    Python as a HDL: http://www.myhdl.org
    VHDL development, the modern way: http://www.sigasi.com
    Analog design automation: http://www.mephisto-da.com
    World-class digital design: http://www.easics.com

Re: [myhdl-list] Combinational Logic Modeling

[Joseph C. <ca...@au...>]

On Jul 17, 2009, at 1:34 PM, Jan Decaluwe wrote:

> Joseph Cali wrote:
>> You are correct that Example 2 can be solved with an MSB detector
>> (not only solved, but solved more efficiently) and in that sense it  
>> is
>> not an ideal example.  The general form of the question is how to  
>> write
>> large combinational encoders and decoders in myhdl where neither the
>> input nor the output are binary.  I will look at the EnumItem  
>> suggestion
>> in the coming days.
>
> Please be precise in what you are asking. You original post mentioned
> "how to implement in MyHDL" but from the context I inferred you were
> asking how to *convert* a *specific* design problem from MyHDL to
> Verilog, probably for synthesis. Now you suggest your example was only
> meant to illustrate a general case. If you want meaningful feedback,
> don't make me guess.
>

Right, that was my mistake.  I will be sure to make my questions more  
clear
in the future.  You provided a great solution to that specific  
problem, which
made me realize that I did not give a solid example with a proper  
description.

> There's a *very* big difference between
>
> 1) modeling
> 2) conversion to Verilog/VHDL
> 3) synthesis
>

I understand the distinctions here quite well.   I will be sure to use  
the correct
terminology in any further conversation on this list.

> Modeling in MyHDL is intended to be completely general in the Python
> sense. Much, much more powerful than Verilog.
>
> Conversion is very restrictive. Synthesis is even more restrictive.
> Moreover, I can't control synthesis contraints.
>
> My goal with conversion is the following: whatever you may want to
> write in Verilog *for synthesis*, should be easier or as easy to do
> with MyHDL. But there's no way in which MyHDL can magically avoid
> synthesis restrictions. Therefore, if synthesis is your concern,
> you should also understand synthesis itself quite well.
>

All the reasoning here is sound.

> Jan
>
> -- 
> Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
>    Python as a HDL: http://www.myhdl.org
>    VHDL development, the modern way: http://www.sigasi.com
>    Analog design automation: http://www.mephisto-da.com
>    World-class digital design: http://www.easics.com
>
>
> ------------------------------------------------------------------------------
> Enter the BlackBerry Developer Challenge
> This is your chance to win up to $100,000 in prizes! For a limited  
> time,
> vendors submitting new applications to BlackBerry App World(TM) will  
> have
> the opportunity to enter the BlackBerry Developer Challenge. See  
> full prize
> details at: http://p.sf.net/sfu/Challenge
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list


Joseph

Re: [myhdl-list] always_comb sensitivity list bug?

[Christopher F. <chr...@gm...>]

Ignore the previous post, I ran across this error with an older release.
I tested with the latest release and it is working fine.
Sorry for any confusion.

On Fri, Jul 17, 2009 at 9:26 AM, Felton Christopher
<chr...@gm...>wrote:

> if you have a simple always_comb generator
>
>    @always_comb
>    def rtl_addr():
>        addr.next = concat(addr_hi, addr_lo)
>
> you will get an error (in simulation) that the sensitivity list is empty.
>  The analyze (??) code must not be able to determine the signals inside of a
> function?
>
> Chris
>

Re: [myhdl-list] Combinational Logic Modeling

[Jan D. <ja...@ja...>]

Joseph Cali wrote:
> You are correct that Example 2 can be solved with an MSB detector 
> (not only solved, but solved more efficiently) and in that sense it is  
> not an ideal example.  The general form of the question is how to write 
> large combinational encoders and decoders in myhdl where neither the 
> input nor the output are binary.  I will look at the EnumItem suggestion 
> in the coming days.

Please be precise in what you are asking. You original post mentioned
"how to implement in MyHDL" but from the context I inferred you were
asking how to *convert* a *specific* design problem from MyHDL to
Verilog, probably for synthesis. Now you suggest your example was only
meant to illustrate a general case. If you want meaningful feedback,
don't make me guess.

There's a *very* big difference between

1) modeling
2) conversion to Verilog/VHDL
3) synthesis

Modeling in MyHDL is intended to be completely general in the Python
sense. Much, much more powerful than Verilog.

Conversion is very restrictive. Synthesis is even more restrictive.
Moreover, I can't control synthesis contraints.

My goal with conversion is the following: whatever you may want to
write in Verilog *for synthesis*, should be easier or as easy to do
with MyHDL. But there's no way in which MyHDL can magically avoid
synthesis restrictions. Therefore, if synthesis is your concern,
you should also understand synthesis itself quite well.

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
    Python as a HDL: http://www.myhdl.org
    VHDL development, the modern way: http://www.sigasi.com
    Analog design automation: http://www.mephisto-da.com
    World-class digital design: http://www.easics.com

[myhdl-list] always_comb sensitivity list bug?

[Felton C. <chr...@gm...>]

if you have a simple always_comb generator

     @always_comb
     def rtl_addr():
         addr.next = concat(addr_hi, addr_lo)

you will get an error (in simulation) that the sensitivity list is  
empty.  The analyze (??) code must not be able to determine the  
signals inside of a function?

Chris

Re: [myhdl-list] Combinational Logic Modeling

[Joseph C. <ca...@au...>]

You are correct that Example 2 can be solved with an MSB detector 
(not only solved, but solved more efficiently) and in that sense it is  
not an ideal example.  The general form of the question is how to write 
large combinational encoders and decoders in myhdl where neither the 
input nor the output are binary.  I will look at the EnumItem suggestion 
in the coming days.

I am more than willing to provide examples that show other design 
problems not directly addressed in the existing examples.  The
examples provided on the myhdl site are excellent but having 
extra examples cannot hurt.  

I intended to preface my first e-mail by stating that I would be 
traveling early this week and not have Internet access.

Thanks for the help,
Joseph


>>> Jan Decaluwe <ja...@ja...> 07/14/09 4:46 AM >>>
Your examples clearly have a logic structure. In such cases, I think it's
often better to use that structure instead of look-up tables.
Look-up tables are ideal for unstructured logic values.

Example 1 is apparently nothing else than  (1 << address) - 1.

Example 2 is interesting, it can be solved with an msb detector. It is in example
I would consider putting on the website, because it may show some interesting
convertor features.

Just loop over de bit indices from high to low. As soon as a 1 is found,
assign the current index to the result and break out of the loop.

In Verilog, this is awkward, because you need to use named blocks and
disable statements. However, the MyHDL convertor can do this automatically.
Many people probably don't realize that this is perfectly
synthesizable (expecially because of the awkwardness in Verilog) so
it may be a good example of how MyHDL can help.

Jan


Joseph Cali wrote:
> I understand how to implement the following in MyHDL (this was generated using toVerilog):
> 
> ----------------------------------------------------------------------------------
> module binary2thermometer (
>     value,
>     address
> );
> 
> output [30:0] value;
> reg [30:0] value;
> input [4:0] address;
> 
> always @(address) begin: BINARY2THERMOMETER_READ
>     // synthesis parallel_case full_case
>     case (address)
>         0: value <= 1;
>         1: value <= 3;
>         3: value <= 15;
>         4: value <= 31;
>         5: value <= 63;
>         6: value <= 127;
>         7: value <= 255;
>         8: value <= 511;
>         9: value <= 1023;
>         10: value <= 2047;
>         11: value <= 4095;
>         12: value <= 8191;
>         13: value <= 16383;
>         14: value <= 32767;
>         15: value <= 65535;
> 	.
> 	.
> 	.
> 	endcase
> end
> endmodule
> ----------------------------------------------------------------------------------
> 
> But how would I model the inverse in MyHDL (this was not done through MyHDL):
> 
> ----------------------------------------------------------------------------------
> module thermometer2binary (
>     value,
>     address
> );
> 
> output [4:0] value;
> reg [4:0] value;
> input [30:0] address;
> 
> always @(address) begin: BINARY2THERMOMETER_READ
>     // synthesis parallel_case full_case
>     case (address)
>         1: value <= 1;
>         3: value <= 2;
>         15: value <= 3;
>         31: value <= 4;
>         63: value <= 5;
>         127: value <= 6;
>         255: value <= 7;
>         511: value <= 8;
>         1023: value <= 9;
>         2047: value <= 10;
>         4095: value <= 11;
>         8191: value <= 12;
>         16383: value <= 13;
>         32767: value <= 14;
>         65535: value <= 15;
> 	.
> 	.
> 	.
> 	endcase
> end
> endmodule
> ----------------------------------------------------------------------------------
> 
> Also, have you considered using Python dictionaries to infer ROMs and other large combinational logic instead of tuples?  I recently stumbled upon MyHDL and I immediately connected with the idea.
> 
> Thanks for the help.
> 
> ------------------------------------------------------------------------------
> Enter the BlackBerry Developer Challenge  
> This is your chance to win up to $100,000 in prizes! For a limited time, 
> vendors submitting new applications to BlackBerry App World(TM) will have
> the opportunity to enter the BlackBerry Developer Challenge. See full prize  
> details at: http://p.sf.net/sfu/Challenge


-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
    Python as a HDL: http://www.myhdl.org
    VHDL development, the modern way: http://www.sigasi.com
    Analog design automation: http://www.mephisto-da.com
    World-class digital design: http://www.easics.com


------------------------------------------------------------------------------
Enter the BlackBerry Developer Challenge  
This is your chance to win up to $100,000 in prizes! For a limited time, 
vendors submitting new applications to BlackBerry App World(TM) will have
the opportunity to enter the BlackBerry Developer Challenge. See full prize  
details at: http://p.sf.net/sfu/Challenge
_______________________________________________
myhdl-list mailing list
myh...@li...
https://lists.sourceforge.net/lists/listinfo/myhdl-list

Re: [myhdl-list] simulation semantics

[Geoffrey B. <geo...@in...>]

Sorry, Moore should be Mealy

On Thu, Jul 16, 2009 at 10:17 AM, Geoffrey Brown <geo...@in...>wrote:

> I've been creating little examples to see if I understand the semantics of
> myhdl.
>  I came across one where the behavior differs completely depending
> upon the initial value of a signal (no problem there), but the generated
> verilog
> is identical  -- see the attached and consider two alternatives:
>
>     t = Signal(bool(not state))
>     t = Signal(bool(0))
>
> In the first case, the simulation does what I expected -- the state
> alternates while in
> the second case its frozen at its initial value.  I can understand why this
> might happen,
> I'm just not sure it should.  The fundamental issue has to do with
> initialization of the
> simulation.   In the second case, the state is inconsistent with the
> combinational
> logic, but there is no event to trigger the necessary change.
>
> I was trying to understand how a Moore machine might be coded
> and simulated in myhdl.   I know this isn't always the design pattern of
> choice,
> but if you want to implement the handshake of communicating processes, this
> is what falls out.
>
> Geoffrey Brown
>
>

[myhdl-list] CoSimulation

[Amway I. <i....@ya...>]

Hi
Does Co-simulation with iverilog work in Fedora 10 ? make fails in fedora 10.

Vimal



      Yahoo! recommends that you upgrade to the new and safer Internet Explorer 8. http://downloads.yahoo.com/in/internetexplorer/

Re: [myhdl-list] int(EnumItem)

[Jan D. <ja...@ja...>]

Felton Christopher wrote:
> On Jul 14, 2009, at 4:36 AM, Jan Decaluwe wrote:
> 
>> Felton Christopher wrote:
>>> Does it make sense to add the following to the EnumItem class?
>>>
>>>        def __int__(self):
>>>            return int(self._val)
>>>
>>>        def __long__(self):
>>>            return long(self._val)
>>>
>>>        def __float__(self):
>>>            return float(self._val)
>> Probably, unless you also expect this to be easily convertible?
> 
> Yeah, I guess that would of been part of it as well.  I had a design I  
> was converting from Verilog.  In this particular case I had a packet  
> decoder.  The first part of the packet was some command structure the  
> last part data.  To decode the command portion the "state" variable is  
> assigned to state and compared to state.  Later the same variable  
> counts through the rest of the packet.  Essentially the "state" was a  
> simple byte counter.
> 
> In that case, I would do something like >>> state.next = state + 1
> 
> This probably does not make sense.  When using the enum it should only  
> be used with strictly with a state variable.  Such that the underlying  
> value is not known or directly needed.

Yes - if the value is needed I suggest to use symbolic constants
instead.


-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
    Python as a HDL: http://www.myhdl.org
    VHDL development, the modern way: http://www.sigasi.com
    Analog design automation: http://www.mephisto-da.com
    World-class digital design: http://www.easics.com

Re: [myhdl-list] int(EnumItem)

[Felton C. <chr...@gm...>]

On Jul 14, 2009, at 4:36 AM, Jan Decaluwe wrote:

> Felton Christopher wrote:
>>
>> Does it make sense to add the following to the EnumItem class?
>>
>>        def __int__(self):
>>            return int(self._val)
>>
>>        def __long__(self):
>>            return long(self._val)
>>
>>        def __float__(self):
>>            return float(self._val)
>
> Probably, unless you also expect this to be easily convertible?

Yeah, I guess that would of been part of it as well.  I had a design I  
was converting from Verilog.  In this particular case I had a packet  
decoder.  The first part of the packet was some command structure the  
last part data.  To decode the command portion the "state" variable is  
assigned to state and compared to state.  Later the same variable  
counts through the rest of the packet.  Essentially the "state" was a  
simple byte counter.

In that case, I would do something like >>> state.next = state + 1

This probably does not make sense.  When using the enum it should only  
be used with strictly with a state variable.  Such that the underlying  
value is not known or directly needed.

Thanks

Re: [myhdl-list] Combinational Logic Modeling

[Jan D. <ja...@ja...>]

Your examples clearly have a logic structure. In such cases, I think it's
often better to use that structure instead of look-up tables.
Look-up tables are ideal for unstructured logic values.

Example 1 is apparently nothing else than  (1 << address) - 1.

Example 2 is interesting, it can be solved with an msb detector. It is in example
I would consider putting on the website, because it may show some interesting
convertor features.

Just loop over de bit indices from high to low. As soon as a 1 is found,
assign the current index to the result and break out of the loop.

In Verilog, this is awkward, because you need to use named blocks and
disable statements. However, the MyHDL convertor can do this automatically.
Many people probably don't realize that this is perfectly
synthesizable (expecially because of the awkwardness in Verilog) so
it may be a good example of how MyHDL can help.

Jan


Joseph Cali wrote:
> I understand how to implement the following in MyHDL (this was generated using toVerilog):
> 
> ----------------------------------------------------------------------------------
> module binary2thermometer (
>     value,
>     address
> );
> 
> output [30:0] value;
> reg [30:0] value;
> input [4:0] address;
> 
> always @(address) begin: BINARY2THERMOMETER_READ
>     // synthesis parallel_case full_case
>     case (address)
>         0: value <= 1;
>         1: value <= 3;
>         3: value <= 15;
>         4: value <= 31;
>         5: value <= 63;
>         6: value <= 127;
>         7: value <= 255;
>         8: value <= 511;
>         9: value <= 1023;
>         10: value <= 2047;
>         11: value <= 4095;
>         12: value <= 8191;
>         13: value <= 16383;
>         14: value <= 32767;
>         15: value <= 65535;
> 	.
> 	.
> 	.
> 	endcase
> end
> endmodule
> ----------------------------------------------------------------------------------
> 
> But how would I model the inverse in MyHDL (this was not done through MyHDL):
> 
> ----------------------------------------------------------------------------------
> module thermometer2binary (
>     value,
>     address
> );
> 
> output [4:0] value;
> reg [4:0] value;
> input [30:0] address;
> 
> always @(address) begin: BINARY2THERMOMETER_READ
>     // synthesis parallel_case full_case
>     case (address)
>         1: value <= 1;
>         3: value <= 2;
>         15: value <= 3;
>         31: value <= 4;
>         63: value <= 5;
>         127: value <= 6;
>         255: value <= 7;
>         511: value <= 8;
>         1023: value <= 9;
>         2047: value <= 10;
>         4095: value <= 11;
>         8191: value <= 12;
>         16383: value <= 13;
>         32767: value <= 14;
>         65535: value <= 15;
> 	.
> 	.
> 	.
> 	endcase
> end
> endmodule
> ----------------------------------------------------------------------------------
> 
> Also, have you considered using Python dictionaries to infer ROMs and other large combinational logic instead of tuples?  I recently stumbled upon MyHDL and I immediately connected with the idea.
> 
> Thanks for the help.
> 
> ------------------------------------------------------------------------------
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> This is your chance to win up to $100,000 in prizes! For a limited time, 
> vendors submitting new applications to BlackBerry App World(TM) will have
> the opportunity to enter the BlackBerry Developer Challenge. See full prize  
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-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
    Python as a HDL: http://www.myhdl.org
    VHDL development, the modern way: http://www.sigasi.com
    Analog design automation: http://www.mephisto-da.com
    World-class digital design: http://www.easics.com

Re: [myhdl-list] int(EnumItem)

[Jan D. <ja...@ja...>]

Felton Christopher wrote:
> 
> Does it make sense to add the following to the EnumItem class?
> 
>         def __int__(self):
>             return int(self._val)
> 
>         def __long__(self):
>             return long(self._val)
> 
>         def __float__(self):
>             return float(self._val)

Probably, unless you also expect this to be easily convertible?

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
    Python as a HDL: http://www.myhdl.org
    VHDL development, the modern way: http://www.sigasi.com
    Analog design automation: http://www.mephisto-da.com
    World-class digital design: http://www.easics.com

[myhdl-list] int(EnumItem)

[Felton C. <chr...@gm...>]

Does it make sense to add the following to the EnumItem class?

         def __int__(self):
             return int(self._val)

         def __long__(self):
             return long(self._val)

         def __float__(self):
             return float(self._val)

Thanks

[myhdl-list] Combinational Logic Modeling

[Joseph C. <ca...@au...>]

I understand how to implement the following in MyHDL (this was generated using toVerilog):

----------------------------------------------------------------------------------
module binary2thermometer (
    value,
    address
);

output [30:0] value;
reg [30:0] value;
input [4:0] address;

always @(address) begin: BINARY2THERMOMETER_READ
    // synthesis parallel_case full_case
    case (address)
        0: value <= 1;
        1: value <= 3;
        3: value <= 15;
        4: value <= 31;
        5: value <= 63;
        6: value <= 127;
        7: value <= 255;
        8: value <= 511;
        9: value <= 1023;
        10: value <= 2047;
        11: value <= 4095;
        12: value <= 8191;
        13: value <= 16383;
        14: value <= 32767;
        15: value <= 65535;
	.
	.
	.
	endcase
end
endmodule
----------------------------------------------------------------------------------

But how would I model the inverse in MyHDL (this was not done through MyHDL):

----------------------------------------------------------------------------------
module thermometer2binary (
    value,
    address
);

output [4:0] value;
reg [4:0] value;
input [30:0] address;

always @(address) begin: BINARY2THERMOMETER_READ
    // synthesis parallel_case full_case
    case (address)
        1: value <= 1;
        3: value <= 2;
        15: value <= 3;
        31: value <= 4;
        63: value <= 5;
        127: value <= 6;
        255: value <= 7;
        511: value <= 8;
        1023: value <= 9;
        2047: value <= 10;
        4095: value <= 11;
        8191: value <= 12;
        16383: value <= 13;
        32767: value <= 14;
        65535: value <= 15;
	.
	.
	.
	endcase
end
endmodule
----------------------------------------------------------------------------------

Also, have you considered using Python dictionaries to infer ROMs and other large combinational logic instead of tuples?  I recently stumbled upon MyHDL and I immediately connected with the idea.

Thanks for the help.

Re: [myhdl-list] dff

[Jan D. <ja...@ja...>]

Amway India wrote:
> Hello
> 
> test_dff.py is once again enclosed
> 
> from random import randrange
> 
> def test_dff():
>         q, d, clk = [Signal(bool(0)) for i in range(3)]
> 
>         dff_inst = dff(q,d,clk)
> 
>         @always (delay (10))
>         def clkgen():
>                 clk.next = not clk
> 
>         @always (clk.negedge)
>         def stimulus ():
>                 d.next = randrange(2)
> 
>         return dff_inst, clkgen, stimulus
> 
> 
> def simulate (timesteps):
>         tb = traceSignals(test_dff)
>         sim = Simulation(tb)
>         sim.run(timesteps)
> 
> simulate(2000)
> **********************************************
> The Above is the test_dff.py code.
> The following is the run result
> **********************************************
> [vimal@vlsiworkgroup cordichdl]$ python test_dff.py
> Traceback (most recent call last):
>   File "test_dff.py", line 24, in <module>
>     simulate(2000)
>   File "test_dff.py", line 20, in simulate
>     tb = traceSignals(test_dff)
> NameError: global name 'traceSignals' is not defined
> ***************************************************
> 
> I hope i used traceSignals. Where is the wrong?

The error is what is says: traceSignals is not defined.
Import it from package myhdl, or use 'from myhdl import *'
to import all identifiers from myhdl.

You may want to check how identifier definition and
imports work in python in general.

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
    Python as a HDL: http://www.myhdl.org
    VHDL development, the modern way: http://www.sigasi.com
    Analog design automation: http://www.mephisto-da.com
    World-class digital design: http://www.easics.com

Re: [myhdl-list] dff

[Amway I. <i....@ya...>]

Hello

test_dff.py is once again enclosed

from random import randrange

def test_dff():
        q, d, clk = [Signal(bool(0)) for i in range(3)]

        dff_inst = dff(q,d,clk)

        @always (delay (10))
        def clkgen():
                clk.next = not clk

        @always (clk.negedge)
        def stimulus ():
                d.next = randrange(2)

        return dff_inst, clkgen, stimulus


def simulate (timesteps):
        tb = traceSignals(test_dff)
        sim = Simulation(tb)
        sim.run(timesteps)

simulate(2000)
**********************************************
The Above is the test_dff.py code.
The following is the run result
**********************************************
[vimal@vlsiworkgroup cordichdl]$ python test_dff.py 
Traceback (most recent call last):
  File "test_dff.py", line 24, in <module>
    simulate(2000)
  File "test_dff.py", line 20, in simulate
    tb = traceSignals(test_dff)
NameError: global name 'traceSignals' is not defined
***************************************************

I hope i used traceSignals. Where is the wrong?



--- On Fri, 10/7/09, Jan Decaluwe <ja...@ja...> wrote:

From: Jan Decaluwe <ja...@ja...>
Subject: Re: [myhdl-list] dff
To: myh...@li...
Date: Friday, 10 July, 2009, 7:42 PM

Amway India wrote:
> Hello  Everybody
>  
> To day  tried to run dff model from myhdl documentation and it is giving 
> some errors which are enclosed.  I wrote two files 1.dff.py  and 2. 
> test_dff.py:
>  
> dff.py
> from myhdl import *
> def dff(q, d, clk):
> @always(clk.posedge)
> def logic():
> q.next = d
> return logic
>  
> test_dff.py
> from random import randrange
> def test_dff():
> q, d, clk = [Signal(bool(0)) for i in range(3)]
> dff_inst = dff(q, d, clk)
> @always(delay(10))
> def clkgen():
> clk.next = not clk
> @always(clk.negedge)
> def stimulus():
> d.next = randrange(2)
> return dff_inst, clkgen, stimulus
> def simulate(timesteps):
> tb = traceSignals(test_dff)
> sim = Simulation(tb)
> sim.run(timesteps)
> simulate(2000)
>  
> When i run
> $python test_dff.py gives
> traceSignal not defined
>  
> What is the reason?

traceSignal is indeed not defined in package myhdl.
traceSignals should be.


-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
    Python as a HDL: http://www.myhdl.org
    VHDL development, the modern way: http://www.sigasi.com
    Analog design automation: http://www.mephisto-da.com
    World-class digital design: http://www.easics.com


------------------------------------------------------------------------------
Enter the BlackBerry Developer Challenge  
This is your chance to win up to $100,000 in prizes! For a limited time, 
vendors submitting new applications to BlackBerry App World(TM) will have
the opportunity to enter the BlackBerry Developer Challenge. See full prize  
details at: http://p.sf.net/sfu/Challenge
_______________________________________________
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https://lists.sourceforge.net/lists/listinfo/myhdl-list



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Re: [myhdl-list] dff

[Jan D. <ja...@ja...>]

Amway India wrote:
> Hello  Everybody
>  
> To day  tried to run dff model from myhdl documentation and it is giving 
> some errors which are enclosed.  I wrote two files 1.dff.py  and 2. 
> test_dff.py:
>  
> dff.py
> from myhdl import *
> def dff(q, d, clk):
> @always(clk.posedge)
> def logic():
> q.next = d
> return logic
>  
> test_dff.py
> from random import randrange
> def test_dff():
> q, d, clk = [Signal(bool(0)) for i in range(3)]
> dff_inst = dff(q, d, clk)
> @always(delay(10))
> def clkgen():
> clk.next = not clk
> @always(clk.negedge)
> def stimulus():
> d.next = randrange(2)
> return dff_inst, clkgen, stimulus
> def simulate(timesteps):
> tb = traceSignals(test_dff)
> sim = Simulation(tb)
> sim.run(timesteps)
> simulate(2000)
>  
> When i run
> $python test_dff.py gives
> traceSignal not defined
>  
> What is the reason?

traceSignal is indeed not defined in package myhdl.
traceSignals should be.


-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
    Python as a HDL: http://www.myhdl.org
    VHDL development, the modern way: http://www.sigasi.com
    Analog design automation: http://www.mephisto-da.com
    World-class digital design: http://www.easics.com

[myhdl-list] dff

[Amway I. <i....@ya...>]

Hello  Everybody
 
To day  tried to run dff model from myhdl documentation and it is giving some errors which are enclosed.  I wrote two files 1.dff.py  and 2. test_dff.py:
 
dff.py

from myhdl import *
def dff(q, d, clk):
@always(clk.posedge)
def logic():
q.next = d
return logic
 
test_dff.py
from random import randrange
def test_dff():

q, d, clk = [Signal(bool(0)) for i in range(3)]

dff_inst = dff(q, d, clk)
@always(delay(10))
def clkgen():
clk.next = not clk
@always(clk.negedge)
def stimulus():
d.next = randrange(2)
return dff_inst, clkgen, stimulus
def simulate(timesteps):
tb = traceSignals(test_dff)
sim = Simulation(tb)
sim.run(timesteps)
simulate(2000)
 
When i run 
$python test_dff.py gives 
traceSignal not defined
 
What is the reason?
 
 
 
 
 


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Re: [myhdl-list] mercurial on SourceForge

[Jan D. <ja...@ja...>]

Christopher Felton wrote:
> 
>     I'm not changing anything in our current setup, but I have
>     enabled mercurial for MyHDL at SourceForge, and I will keep
>     the repository there up to date also. This can be useful
>     for people coming to MyHDL through SourceForge. It is
>     also an additional back-up.
> 
> 
> That is pretty interesting, it shows some of the flexibility and 
> features of a distributed version control system like mercurial.  Easily 
> keep different repositories in sync.

Indeed, with distributed version control all kinds of useful work
flows become easy and natural. It is easy to forget how complicated
things were with centralized systems. I don't want to go back.

I'm also happy with the particular choice of mercurial. It
fits my brain. Moreover, it seems more and more projects are
switching to it (or supporting it, like SourceForge). Python
itself, for example. Mercurial clearly is a winner.

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
    Python as a HDL: http://www.myhdl.org
    VHDL development, the modern way: http://www.sigasi.com
    Analog design automation: http://www.mephisto-da.com
    World-class digital design: http://www.easics.com

Re: [myhdl-list] mercurial on SourceForge

[Christopher F. <chr...@gm...>]

>
>
> I'm not changing anything in our current setup, but I have
> enabled mercurial for MyHDL at SourceForge, and I will keep
> the repository there up to date also. This can be useful
> for people coming to MyHDL through SourceForge. It is
> also an additional back-up.
>

That is pretty interesting, it shows some of the flexibility and features of
a distributed version control system like mercurial.  Easily keep different
repositories in sync.

Chris

[myhdl-list] mercurial on SourceForge

[Jan D. <ja...@ja...>]

Sourceforge has made some major changes lately.

In addition to a new interface, they offer a lot of new
services. In particular, there is now support for mercurial
hosting.

I'm not changing anything in our current setup, but I have
enabled mercurial for MyHDL at SourceForge, and I will keep
the repository there up to date also. This can be useful
for people coming to MyHDL through SourceForge. It is
also an additional back-up.

Jan

--
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
    Python as a HDL: http://www.myhdl.org
    VHDL development, the modern way: http://www.sigasi.com
    Analog design automation: http://www.mephisto-da.com
    World-class digital design: http://www.easics.com