myhdl-list — Mailing list for discussions on MyHDL

Re: [myhdl-list] Trouble setting up USBP

[Christopher F. <chr...@gm...>]

>
>
> Summary:
> - SF last release: Jan 16 2008
>   => doen't seem to work with users:cfelton:projects:usbp code
> - USBP project has been updated [08/2009], but code is not available
>
>
Daniel,

There isn't (yet) a release/installer for the latest code but the code is in
the sourceforge svn repository.

We have not been able to test the latest from a fresh install yet and time
has been the issue.  We can send you the latest installer in a separate
email and will upload the latest MyHDL and latest USBP to sourceforge svn.

.chris

[myhdl-list] Trouble setting up USBP

[Daniel G. <dan...@ie...>]

Hi,
I'm trying the USB FPGA code 
(http://www.myhdl.org/doku.php/users:cfelton:projects:usbp)

- MyHDL and usbp-0.5pre.zip setup done without problem (Win XP SP3)
   . Simulation => VCD file: OK
   . Verilog conversion: OK
   . VHDL conversion: temporarily disabled (broken)
     => no problem it' a work in progress project
- Trying to launch: test_usbp_hw.py
   => complain about missing usbp module
   . gone to SourceForge, downloaded and installed USBP:
     Setup.exe 8.6 MiB  	Release date: Wed Jan 16 2008 07:00
     => doesn't solve the problem
     no readme file found installed by Setup.exe
   . gone to USBP website (http://www.fpgaz.com/usbp/)
     One update says:
	Recent Changes [08/2009]
	* The host software is more Python centric. ...
           The python package latest installs can be downloaded "here".
     => Great news: former interface using C++/Boost Python
        was frightening to me, preventing me to do a try.
     BUT: "here" is a broken link to SourceForge !!!

Summary:
- SF last release: Jan 16 2008
   => doen't seem to work with users:cfelton:projects:usbp code
- USBP project has been updated [08/2009], but code is not available

Can someone help setting up USBP code to make all this work ?

PS:
- Many thanks to Jan Decaluwe for inventing MyHDL
   (I'm a big fan of Python and sometimes using tiresome VHDL...)
- Many thanks to Christopher Felton for his USB FPGA project:
   . It's a more exciting (for me) example of using MyHDL than
     coding a D flipflop or just making noise.
     It has changed MyHDL status in my mind
     from an "interesting initiative"
     to a "useful tool" that's worth mastering.
   . I'm using USB+FPGA boards for prototype work
     but don't enjoy writing VHDL

[myhdl-list] Interesting

[Christopher F. <chr...@gm...>]

Synopsys released a white paper on "coding guidelines for datapath
synthesis<http://techonline.com/learning/techpaper/193102987>".
 The paper is about using signed attribute for VHDL and Verilog.  States
that the QoR is better when signed is used versus handling signed manually
(I quickly perused the article might be more assertions).

This indirectly supports what Jan has already mentioned and discussed here
and in the "These Ints are made for
Counting"<http://www.jandecaluwe.com/hdldesign/counting.html>essay.

Thought I would share with the MyHDL community.

.chris

Re: [myhdl-list] delay/timing specification & constrains (setup/hold), asserts

[Jan D. <ja...@ja...>]

john smith wrote:
> Hi Jan,
>  
> Recently I started looking at myHDL/Python for HW 
> simulation/verification and I 'd like to know 
> if timing/delay specifications and checks (e.g. setup, hold), possibly 
> asserts (which should not be hard considering the python exceptions 
> support) related functionality is supported.
>  
> I looked through myHDL manual and examples but I couldn't find anything 
> related.
> If supported, I'd appreciate you (or others) mentioning the 
> document/sections/examples, if not, do you have any plans?

No plans.

Some considerations:

Obviously MyHDL is strongly inspired by my approach to
digital design. In that appproach, RTL design and higher
is the front-end, gate-level is part of the back-end and
only used for the verification of synthesis and physical
implementation.

I believe there are many things wrong with the traditional
tools for RTL design. However, little is wrong with the
gate-level stuff, hence not much can be done to improve things.
That's why MyHDL focusses on RTL and higher.

Also, my favourite approach to timing verification is not gate
level simulation, but timing analysis.

Finally, MyHDL is intrinsically much slower than compiled
simulations (although google is putting its weight behind
a substantial improvement.) I think this is acceptable at
the design front-end, given what you get back in expressive
power and flexibility. However, such a consideration doesn't
hold for gate-level verification: raw performance is all
what counts there.

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
    Python as a HDL: http://www.myhdl.org
    VHDL development, the modern way: http://www.sigasi.com
    Analog design automation: http://www.mephisto-da.com
    World-class digital design: http://www.easics.com

Re: [myhdl-list] bit string separators

[Jan D. <ja...@ja...>]

Felton Christopher wrote:
> I added a small simple change to add bit string separators like 
> Verilog.  I forget if there is a similar bit string separator for VHDL?  
> If so we might want to add it as well.

I think it's the same.
> 
> One liner change (actually two) so that one can enter a bit-string with 
> separators.

Ok, pushed to the public repo's. Thanks.

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
    Python as a HDL: http://www.myhdl.org
    VHDL development, the modern way: http://www.sigasi.com
    Analog design automation: http://www.mephisto-da.com
    World-class digital design: http://www.easics.com

Re: [myhdl-list] delay/timing specification & constrains (setup/hold), asserts

[Christopher L. F. <chr...@gm...>]

from myhdl import *


def simple_ex(clk, rd, wr, din, dout):
    _d = Signal(intbv(0)[8:])

    @always(clk.posedge)
    def rtl_data():
        if rd and wr:
            assert False, "Invalid Operation"
        if rd:
            dout.next = _d
        elif wr:
            _d.next = din

    return instances()


def test():

    clk  = Signal(False)
    rd   = Signal(False)
    wr   = Signal(False)
    din  = Signal(intbv(0)[8:])
    dout = Signal(intbv(0)[8:])

    dut = simple_ex(clk, rd, wr, din, dout)
    
    @always(delay(1))
    def tb_clk_gen():
        clk.next = not clk

    @instance
    def tb_main():
        din.next  = 0xCE
        rd.next   = False
        wr.next   = True
        yield delay(4)
        rd.next   = True
        wr.next   = False
        yield delay(4)
        assert dout == 0xCE, "Testbench FAILED, Expected dout == 0xCE got 0x%02X" % (dout)
        print "Data check OK"
        
        din.next  = 0xBA
        rd.next   = True
        wr.next   = True

        yield delay(4)
        assert False, "Should not get this far, module should assert and fail"
        # Alternative is to catch the assert and verify an assert occurred

    return instances()

if __name__ == '__main__':
    tb = test()
    sim = Simulation(tb)
    sim.run()

    
    

[myhdl-list] delay/timing specification & constrains (setup/hold), asserts

[john s. <wha...@ya...>]

Hi Jan,
 
Recently I started looking at myHDL/Python for HW simulation/verification and I 'd like to know if timing/delay specifications and checks (e.g. setup, hold), possibly asserts (which should not be hard considering the python exceptions support) related functionality is supported.
 
I looked through myHDL manual and examples but I couldn't find anything related.
If supported, I'd appreciate you (or others) mentioning the document/sections/examples, if not, do you have any plans?
 
thanks,
John

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[myhdl-list] bit string separators

[Felton C. <chr...@gm...>]

I added a small simple change to add bit string separators like  
Verilog.  I forget if there is a similar bit string separator for  
VHDL?  If so we might want to add it as well.

One liner change (actually two) so that one can enter a bit-string  
with separators.

Example
x = intbv("0_0110_0101")

[myhdl-list] Embedded Newsletter

[Christopher F. <chr...@gm...>]

Below I copied a portion of the Embedded.com Newsletter that was sent out on
10/15/2009.  It has a link to a MyHDL article, although the article is a
couple years old, it is nice to see the inclusion of MyHDL in the
newsletter.

~~~~~ Excerpt from Embedded.com Newsletter ~~~~~~~~~~~~~~
*TECH FOCUS - SCRIPTING LANGUAGES IN EMBEDDED SYSTEMS DESIGN* I had
forgotten how ubiquitous - and important - the many small and simple scripting
languages <http://en.wikipedia.org/wiki/Scripting_language> used in embedded
systems design are until I read the two articles by Matthew Scarpino and
Randy Melton that lead off this issue.

In "A brief introduction to the TCL scripting
language<http://newsletter.embedded.com/cgi-bin4/DM/y/hBUav0RueqL0FrY0HTJG0EK>,"
Matt provides a brief tutorial on TCL, used by IBM to tie together all the
disparate elements in its Cell Multicore Programming
environment<http://newsletter.embedded.com/cgi-bin4/DM/y/hBUav0RueqL0FrY0HTJR0EV>,
the subject of an earlier five part series. In "Using TCL to create a
virtual component in
Verilog<http://newsletter.embedded.com/cgi-bin4/DM/y/hBUav0RueqL0FrY0HTJH0EL>,"
Randy describes the use of TCL in the EDA environment.

Both authors are dedicated fans of interpretive scripting languages in
general and TCL<http://newsletter.embedded.com/cgi-bin4/DM/y/hBUav0RueqL0FrY0HRBU0EO>in
particular, and they convinced me to become a fan too. I searched the
Embedded.com design article archives and found about a dozen design features
on how scripting languages are used, including TCL,
Perl<http://newsletter.embedded.com/cgi-bin4/DM/y/hBUav0RueqL0FrY0HTJN0ER>,
Python Network Spaces<http://newsletter.embedded.com/cgi-bin4/DM/y/hBUav0RueqL0FrY0HTJI0EM>,
and the Turing-inspired Smart
Machine<http://newsletter.embedded.com/cgi-bin4/DM/y/hBUav0RueqL0FrY0HTJM0EQ>
.

In "TCL adds extensibility to design
tools<http://newsletter.embedded.com/cgi-bin4/DM/y/hBUav0RueqL0FrY0HTJL0EP>,"
TCL's creator John Ousterhaut describes why embedded developers need such
system integration languages. In "Implementing a processor independent
battery-powered wireless mesh
network<http://newsletter.embedded.com/cgi-bin4/DM/y/hBUav0RueqL0FrY0G8oH0ET>,"
David Ewing describes the use of Python to create a wireless mesh software
protocol stack. Jan Decaluwe's article on the use of Python as a hardware
description language<http://newsletter.embedded.com/cgi-bin4/DM/y/hBUav0RueqL0FrY0HTJO0ES>and
another article on the use
of Python to write parallel programs without specialized
tools<http://newsletter.embedded.com/cgi-bin4/DM/y/hBUav0RueqL0FrY0HTJI0EM>round
out the selection.

Given the distributed, wirelessly connected network environment in which
embedded systems now operate as well as the use of multicore processors, I
think the importance of such integrative languages will increase. I would
like to hear from you about your experiences, how you are using these
languages in your designs, and what kinds of articles you would like to read
- and write - on these topics. (Embedded.com Editor Bernard Cole,
bc...@ac...)


~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~`

Re: [myhdl-list] List of Signals in an always_comb

[Jan D. <ja...@ja...>]

Thanks, I have applied the patch and pushed it to the public repo's.


Felton Christopher wrote:
> I came across a possible issue.  I had created a design that had used a 
> list of signals in an always_comb generator.  The conversion determined 
> that the alway_comb generator was of type "SIMPLE" and the resulting 
> Verilog generated "assign" for signal array.  In short the generated 
> Verilog is not valid Verilog.
> 
> I have attached a simple example of the MyHDL and the generated Verilog 
> (example_fail.v).  I also attached a patch for a possible fix (if it is 
> determined this is an issue).  The fix uses the same method to determine 
> if a ROM is being generated (hasRom) and the generated Verilog with the 
> patch (example.v).
> 
> 
> 
> ------------------------------------------------------------------------
> 
>  
>  
>  
> 
> 
> 
> 
> Thanks
> 
> Chris
> 
> 
> ------------------------------------------------------------------------
> 
> ------------------------------------------------------------------------------
> Come build with us! The BlackBerry® Developer Conference in SF, CA
> is the only developer event you need to attend this year. Jumpstart your
> developing skills, take BlackBerry mobile applications to market and stay 
> ahead of the curve. Join us from November 9-12, 2009. Register now!
> http://p.sf.net/sfu/devconf
> 
> 
> ------------------------------------------------------------------------
> 
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list


-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
    Python as a HDL: http://www.myhdl.org
    VHDL development, the modern way: http://www.sigasi.com
    Analog design automation: http://www.mephisto-da.com
    World-class digital design: http://www.easics.com

[myhdl-list] List of Signals in an always_comb

[Felton C. <chr...@gm...>]

I came across a possible issue.  I had created a design that had used  
a list of signals in an always_comb generator.  The conversion  
determined that the alway_comb generator was of type "SIMPLE" and the  
resulting Verilog generated "assign" for signal array.  In short the  
generated Verilog is not valid Verilog.

I have attached a simple example of the MyHDL and the generated  
Verilog (example_fail.v).  I also attached a patch for a possible fix  
(if it is determined this is an issue).  The fix uses the same method  
to determine if a ROM is being generated (hasRom) and the generated  
Verilog with the patch (example.v).

Re: [myhdl-list] Bus Transaction Models and Testbenches

[Felton C. <chr...@gm...>]

On Sep 1, 2009, at 5:13 AM, Jan Decaluwe wrote:

> Felton Christopher wrote:
>>
>> I have created a simple bus model to interface to my design.  I  
>> have a
>> generator that will pull data from a FIFO (python list).  And a  
>> bunch of
>> functions that write and read to the FIFO.
>
> If I understand it well, your problem is the use of "sub" generators
> within other generators. This is actually an ongoing topic of
> developments and approaches in the Python world. But in MyHDL, this
> issue was recognized early on and solved by permitting a generator
> to yield another generator, with the same "waiting" semantics as
> for the other cases.
>
> It's probably not yet used very often, but isn't this
> what you are looking for?
>
> http://www.myhdl.org/doc/0.6/manual/modeling.html#modeling-with-bus-functional-procedures
>

That its, exactly what I was trying achieve.  Have not try it yet but  
will shortly.

Thanks!
Chris

> Jan
>
>>
>> My testbench uses the functions (and generators) to interface to the
>> DUT.  The following is an example:
>>
>> -----------
>>    gen = fx2Model.WriteAddress(0x0103, 0xAA)
>>    yld = gen.next()
>>    while yld is not None:
>>        yield yld
>>        yld = gen.next()
>> ...
>>    TracePrint('Wait for data in read fifo')
>>    while not fx2Model.IsData(fx2Model.EP8, 5):
>>        yield delay(2*fx2Model.IFCLK_TICK)
>>
>>    for dat in test_data1:
>>        rdata = fx2Model.Read(fx2Model.EP8)
>>        assert rdata == dat, \
>>        "Testbench FAILED return data %x expected %x" % (rdata, dat)
>>
>> ----------
>>
>> My questions (issue) is that the transactors have many steps (do
>> multiple "things") and need to "yield".  A yield, relinquish to the
>> simulation engine, can only be issued at the top testbench generator.
>> The functions (generators) that encapsulate the bus transactions only
>> return what to "wait for".  But I would like my testbenches to be  
>> read as:
>>
>> ----------
>>    fx2Model.WriteAddress(0x0103, 0xAA)
>>    fx2Model.Read(fx2Model.EP8, rdata)
>> ----------
>>
>> I don't know how to achieve the desired second example because the  
>> model
>> functions (generators) would need to yield.  If the yields are in the
>> model it will only yield to the top testbench function  
>> (generator).  Any
>> suggestions or ideas welcome.
>>
>> I have posted the project on the MyHDL website, more information is
>> available here, http://www.myhdl.org/doku.php/users:cfelton:projects:usbp
>>
>> Thanks
>> Chris
>>
>>
>> ------------------------------------------------------------------------
>>
>> ------------------------------------------------------------------------------
>> Let Crystal Reports handle the reporting - Free Crystal Reports  
>> 2008 30-Day
>> trial. Simplify your report design, integration and deployment -  
>> and focus on
>> what you do best, core application coding. Discover what's new with
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>>
>>
>> ------------------------------------------------------------------------
>>
>> _______________________________________________
>> myhdl-list mailing list
>> myh...@li...
>> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>
>
> -- 
> Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
>    Python as a HDL: http://www.myhdl.org
>    VHDL development, the modern way: http://www.sigasi.com
>    Analog design automation: http://www.mephisto-da.com
>    World-class digital design: http://www.easics.com
>
>
> ------------------------------------------------------------------------------
> Let Crystal Reports handle the reporting - Free Crystal Reports 2008  
> 30-Day
> trial. Simplify your report design, integration and deployment - and  
> focus on
> what you do best, core application coding. Discover what's new with
> Crystal Reports now.  http://p.sf.net/sfu/bobj-july
> _______________________________________________
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> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list

Re: [myhdl-list] Bus Transaction Models and Testbenches

[Jan D. <ja...@ja...>]

Felton Christopher wrote:
> 
> I have created a simple bus model to interface to my design.  I have a 
> generator that will pull data from a FIFO (python list).  And a bunch of 
> functions that write and read to the FIFO.

If I understand it well, your problem is the use of "sub" generators
within other generators. This is actually an ongoing topic of
developments and approaches in the Python world. But in MyHDL, this
issue was recognized early on and solved by permitting a generator
to yield another generator, with the same "waiting" semantics as
for the other cases.

It's probably not yet used very often, but isn't this
what you are looking for?

http://www.myhdl.org/doc/0.6/manual/modeling.html#modeling-with-bus-functional-procedures

Jan

> 
> My testbench uses the functions (and generators) to interface to the 
> DUT.  The following is an example:
> 
> -----------
>     gen = fx2Model.WriteAddress(0x0103, 0xAA)
>     yld = gen.next()
>     while yld is not None:
>         yield yld
>         yld = gen.next()
> ...
>     TracePrint('Wait for data in read fifo')
>     while not fx2Model.IsData(fx2Model.EP8, 5):
>         yield delay(2*fx2Model.IFCLK_TICK)
>         
>     for dat in test_data1:
>         rdata = fx2Model.Read(fx2Model.EP8)
>         assert rdata == dat, \
>         "Testbench FAILED return data %x expected %x" % (rdata, dat)
> 
> ----------
> 
> My questions (issue) is that the transactors have many steps (do 
> multiple "things") and need to "yield".  A yield, relinquish to the 
> simulation engine, can only be issued at the top testbench generator. 
>  The functions (generators) that encapsulate the bus transactions only 
> return what to "wait for".  But I would like my testbenches to be read as:
> 
> ----------
>     fx2Model.WriteAddress(0x0103, 0xAA)
>     fx2Model.Read(fx2Model.EP8, rdata)
> ----------
> 
> I don't know how to achieve the desired second example because the model 
> functions (generators) would need to yield.  If the yields are in the 
> model it will only yield to the top testbench function (generator).  Any 
> suggestions or ideas welcome.
> 
> I have posted the project on the MyHDL website, more information is 
> available here, http://www.myhdl.org/doku.php/users:cfelton:projects:usbp
> 
> Thanks
> Chris
> 
> 
> ------------------------------------------------------------------------
> 
> ------------------------------------------------------------------------------
> Let Crystal Reports handle the reporting - Free Crystal Reports 2008 30-Day 
> trial. Simplify your report design, integration and deployment - and focus on 
> what you do best, core application coding. Discover what's new with 
> Crystal Reports now.  http://p.sf.net/sfu/bobj-july
> 
> 
> ------------------------------------------------------------------------
> 
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list


-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
    Python as a HDL: http://www.myhdl.org
    VHDL development, the modern way: http://www.sigasi.com
    Analog design automation: http://www.mephisto-da.com
    World-class digital design: http://www.easics.com

[myhdl-list] Bus Transaction Models and Testbenches

[Felton C. <chr...@gm...>]

I have created a simple bus model to interface to my design.  I have a  
generator that will pull data from a FIFO (python list).  And a bunch  
of functions that write and read to the FIFO.

My testbench uses the functions (and generators) to interface to the  
DUT.  The following is an example:

-----------
     gen = fx2Model.WriteAddress(0x0103, 0xAA)
     yld = gen.next()
     while yld is not None:
         yield yld
         yld = gen.next()
...
     TracePrint('Wait for data in read fifo')
     while not fx2Model.IsData(fx2Model.EP8, 5):
         yield delay(2*fx2Model.IFCLK_TICK)

     for dat in test_data1:
         rdata = fx2Model.Read(fx2Model.EP8)
         assert rdata == dat, \
         "Testbench FAILED return data %x expected %x" % (rdata, dat)

----------

My questions (issue) is that the transactors have many steps (do  
multiple "things") and need to "yield".  A yield, relinquish to the  
simulation engine, can only be issued at the top testbench generator.   
The functions (generators) that encapsulate the bus transactions only  
return what to "wait for".  But I would like my testbenches to be read  
as:

----------
     fx2Model.WriteAddress(0x0103, 0xAA)
     fx2Model.Read(fx2Model.EP8, rdata)
----------

I don't know how to achieve the desired second example because the  
model functions (generators) would need to yield.  If the yields are  
in the model it will only yield to the top testbench function  
(generator).  Any suggestions or ideas welcome.

I have posted the project on the MyHDL website, more information is  
available here, http://www.myhdl.org/doku.php/users:cfelton:projects:usbp

Thanks
Chris

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Re: [myhdl-list] bit-wise or

[Christopher F. <chr...@gm...>]

On Wed, Jul 22, 2009 at 4:40 PM, Christopher Felton
<chr...@gm...>wrote:

>
>
> On Wed, Jul 22, 2009 at 3:42 PM, Patricio Kaplan <
> pat...@gm...> wrote:
>
>> Is there an easy way to do what this verilog code does with myhdl?
>> wire abc[11:0];
>> wire a_bit_set = |abc;
>>
>> ----------
>>
>>
> BOMK there isn't a similar 1 liner to do a reduction "or" (reduction
> anything) in MyHDL.  Since MyHDL uses Python operators there isn't
> an equivalent operator to override for such functionality.
>
> But you can use for loops to achieve the same functionality.  And you
> should be able to write a function that is synthesizable that can be used
> on variable bit-vectors.
>
> Is there a similar "one liner" in VHDL?  How would this be done in VHDL?  I
> have always used loops in VHDL.
>

Answering my own question (after a quick google search) there isn't a
reduction operator in VHDL either.  In VHDL a function can be created to
achieve the functionality.  If it isn't obvious how to do this google "vhdl
reduction or" and there will be some examples.

Chris

Re: [myhdl-list] bit-wise or

[Christopher F. <chr...@gm...>]

On Wed, Jul 22, 2009 at 3:42 PM, Patricio Kaplan
<pat...@gm...>wrote:

> Is there an easy way to do what this verilog code does with myhdl?
> wire abc[11:0];
> wire a_bit_set = |abc;
>
> ----------
>
>
BOMK there isn't a similar 1 liner to do a reduction "or" (reduction
anything) in MyHDL.  Since MyHDL uses Python operators there isn't
an equivalent operator to override for such functionality.

But you can use for loops to achieve the same functionality.  And you should
be able to write a function that is synthesizable that can be used
on variable bit-vectors.

Is there a similar "one liner" in VHDL?  How would this be done in VHDL?  I
have always used loops in VHDL.

Chris

[myhdl-list] bit-wise or

[Patricio K. <pat...@gm...>]

Is there an easy way to do what this verilog code does with myhdl?
wire abc[11:0];
wire a_bit_set = |abc;

----------

thanks
-patricio

Re: [myhdl-list] Programmable LFSR

[Jan D. <ja...@ja...>]

Joseph Cali wrote:
> That worked perfectly.  I just added the "sbit = Signal(bitvector)"  
> and everything is converted with no problems.  The other cases where I  
> ran into the problem where identical.  Thanks for clearing that up for  
> me, I need to remember to wrap intbv with Signal before throwing it in  
> a generator.  Now I am off to see what Cadence tries to do with the  
> generated Verilog.

Ok. But at Chris suggested, you'll probably have to use an always_comb
to set up the "constant" signal explicitly. Initial values are
currently not supported, see

http://www.myhdl.org/doku.php/dev:tasks#initial_values_support

I realize this is all far from ideal. Ideally, it should be easier to use
indexed constants. This is a known issue with an open task:

http://www.myhdl.org/doku.php/dev:tasks#more_general_support_of_indexed_constants

Jan


> 
> Joseph
> 
> On Jul 20, 2009, at 9:40 AM, Christopher Felton wrote:
> 
>> You are now creating the constant / static bit-vector during the
>> elaboration phase (elaboration is great cause you can use all of
>> Python's power).  I think the issue is, the constant bit-vector exists
>> but what is the hardware representation of the "bitvector".  Kinda  
>> like
>> the RAM/ROM modules you posted about earlier.  I believe there still
>> needs to be some component for the bitvector, need a signal and  
>> possibly
>> addition generator that describes what bitvector (or corresponding
>> signal) is.
>>
>> First need a signal for the bitvector
>>
>> sbit = Signal(bitvector)
>>
>> Instead of if bitvectore[i], use if sbit[i]
>>
>> And possibly some behavioral definition that states what the sbit is  
>> in
>> hardware (register, combo constants, etc).  Example make it a register
>>
>> @always(clk.posedge)
>> def rtl_bitvector_reg():
>>    if rst:
>>        sbit.next = bitvector
>>
>>
>> I didn't test this but hopefully this will helps
>>
>> Chris
>>
>> Joseph Cali wrote:
>>> I tried to use the bitvector approach, but I am not getting a new
>>> error. I think that I am not using the intbv class correctly in some
>>> cases, as I have seen this error pop up several times in other MyHDL
>>> generators that I have written.  I also should note that I am using
>>> the most recent MyHDL from the mercurial repository.
>>>
>>> Here is the code
>>> ---------------------------------------------------------------------
>>>
>>> def Galois(out, clk, rst, width=32):
>>> '''
>>> Implement a Galois Linear Feedback Shift Register (LFSR).
>>>
>>> Parameters
>>> ----------
>>> width : integer
>>> The length of the LFSR
>>>
>>> Input Ports
>>> -----------
>>> clk : The clock
>>> rst : Active high reset
>>>
>>>
>>> Output Ports
>>> ------------
>>> out : Pseudo-Random word
>>> '''
>>> sel_table = width - 3
>>> polynomial = GALOIS_TABLE[sel_table]
>>> polynomial = polynomial[1:len(polynomial)-1]
>>> bitvector = intbv(0)[width:]
>>> for i in range(0, width):
>>> if i in polynomial:
>>> bitvector[i] = 1
>>> else:
>>> bitvector[i] = 0
>>>
>>>
>>>
>>> state = Signal(intbv(0)[width:])
>>>
>>> @always(clk.posedge, rst)
>>> def logic():
>>> if rst == 1:
>>> state.next[0] = 1
>>> else:
>>> state.next[width-1] = state[0]
>>> for i in downrange(width-1, 0):
>>> if bitvector[i]:
>>> state.next[i] = state[i+1] ^ state[0]
>>> else:
>>> state.next[i] = state[i+1]
>>>
>>> Joseph
>>>
>>>
>>>
>>> On Jul 20, 2009, at 4:16 AM, Jan Decaluwe wrote:
>>>
>>>> Syntax
>>>>
>>>>  if in ...
>>>>
>>>> is indeed not supported. This is currently not checked, hence the  
>>>> bad
>>>> stack trace instead of a clear error message.
>>>>
>>>> As a workaround, map the polynomial to a bitvector with the  
>>>> significant
>>>> bits set before using it inside a generator. Then you can use
>>>>
>>>>  if polynomial[i] ...
>>>>
>>>> as the check.
>>>>
>>>> Probably you mean state.next[i], not state[i].next.
>>>>
>>>> All code inside a generator is converted literally, so you will
>>>> get a for-loop in the output.
>>>>
>>>> Jan
>>>>
>>>>
>>>> Joseph Cali wrote:
>>>>> I am attempting to parameterize the creation of Galois LFSRs.  I
>>>>> have a table that contains Galois polynomials (a list of tuples
>>>>> named GALOIS_TABLE).  The following is my first attempt at a
>>>>> solution in MyHDL.
>>>>>
>>>>> def Galois(out, clk, rst, width=32):
>>>>> '''
>>>>> Implement a Galois Linear Feedback Shift Register (LFSR).
>>>>>
>>>>> Parameters
>>>>> ----------
>>>>> width : integer
>>>>> The length of the LFSR
>>>>>
>>>>> Input Ports
>>>>> -----------
>>>>> clk : The clock
>>>>> rst : Active high reset
>>>>>
>>>>> Output Ports
>>>>> ------------
>>>>> out : Pseudo-Random word
>>>>> '''
>>>>> sel_table = width - 3
>>>>> polynomial = GALOIS_TABLE[sel_table]
>>>>> polynomial = polynomial[1:len(polynomial)-1]  # Take the relevant
>>>>> part of the polynomial
>>>>>
>>>>> state = Signal(intbv(0)[width:])
>>>>>
>>>>> @always(clk.posedge, rst.negedge)
>>>>> def logic():
>>>>> if rst == 1:
>>>>> state.next[0] = 1
>>>>> else:
>>>>> state.next[width-1] = state[0]
>>>>> for i in downrange(width-1, 0):
>>>>> if i in polynomial:  # This is where the problem occurs, I believe
>>>>> state[i].next = state[i+1] ^ state[0]
>>>>> else:
>>>>> state[i].next = state[i+1]
>>>>>
>>>>> @always_comb
>>>>> def assignments():
>>>>> out.next = state
>>>>>
>>>>> return logic, assignments
>>>>>
>>>>>
>>>>> --------------------------------------------------------------------------------------------------------------------
>>>>> I do not think the "if i in whatever" syntax is convertible.  I was
>>>>> wondering if anyone had any
>>>>> suggestions on alternative Python code that would yield a
>>>>> convertible example.  Attempting
>>>>> to convert the above code gives the following stack trace using
>>>>> Python 2.6.2:
>>>>>
>>>>> File "galois.py", line 147, in <module>
>>>>>   galois = toVerilog(Galois, out, clk, rst, width=18)
>>>>> File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py",
>>>>> line 124, in __call__
>>>>>   _convertGens(genlist, vfile)
>>>>> File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py",
>>>>> line 321, in _convertGens
>>>>>   v.visit(tree)
>>>>> File "/usr/lib/python2.6/ast.py", line 231, in visit
>>>>>   return visitor(node)
>>>>> File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py",
>>>>> line 1248, in visit_Module
>>>>>   self.visit(stmt)
>>>>> File "/usr/lib/python2.6/ast.py", line 231, in visit
>>>>>   return visitor(node)
>>>>> File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py",
>>>>> line 1850, in visit_FunctionDef
>>>>>   self.visit_stmt(node.body)
>>>>> File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py",
>>>>> line 1599, in visit_stmt
>>>>>   self.visit(stmt)
>>>>> File "/usr/lib/python2.6/ast.py", line 231, in visit
>>>>>   return visitor(node)
>>>>> File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py",
>>>>> line 1177, in visit_If
>>>>>   self.mapToIf(node)
>>>>> File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py",
>>>>> line 1232, in mapToIf
>>>>>   self.visit_stmt(node.else_)
>>>>> File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py",
>>>>> line 1599, in visit_stmt
>>>>>   self.visit(stmt)
>>>>> File "/usr/lib/python2.6/ast.py", line 231, in visit
>>>>>   return visitor(node)
>>>>> File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py",
>>>>> line 1140, in visit_For
>>>>>   self.visit_stmt(node.body)
>>>>> File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py",
>>>>> line 1599, in visit_stmt
>>>>>   self.visit(stmt)
>>>>> File "/usr/lib/python2.6/ast.py", line 231, in visit
>>>>>   return visitor(node)
>>>>> File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py",
>>>>> line 1177, in visit_If
>>>>>   self.mapToIf(node)
>>>>> File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py",
>>>>> line 1221, in mapToIf
>>>>>   self.visit(test)
>>>>> File "/usr/lib/python2.6/ast.py", line 231, in visit
>>>>>   return visitor(node)
>>>>> File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py",
>>>>> line 969, in visit_Compare
>>>>>   self.write(" %s " % opmap[type(node.ops[0])])
>>>>> KeyError: <class '_ast.In'>
>>>>>
>>>>>
>>>>> --------------------------------------------------------------------------------------------------------------------
>>>>> For width=18,  a Galois polynomial is x^18 + x^11 + 1.  The target
>>>>> Verilog should behave as below:
>>>>>
>>>>> module galois18(state, clk, rst);
>>>>> input clk;
>>>>> input rst;
>>>>> output [17:0] state;
>>>>> reg [17:0] state;
>>>>>
>>>>> always @(posedge clk) begin
>>>>> if(~rst) begin
>>>>> state <= {state[0], state[17:12], state[11]^state[0], state[10:1]};
>>>>> end
>>>>> else begin
>>>>> state[0] <= 1;
>>>>> end
>>>>> end
>>>>> endmodule
>>>>>
>>>>>
>>>>>
>>>>> Joseph
>>>>>
>>>>> ------------------------------------------------------------------------------
>>>>> Enter the BlackBerry Developer Challenge
>>>>> This is your chance to win up to $100,000 in prizes! For a limited
>>>>> time,
>>>>> vendors submitting new applications to BlackBerry App World(TM)  
>>>>> will
>>>>> have
>>>>> the opportunity to enter the BlackBerry Developer Challenge. See
>>>>> full prize
>>>>> details at: http://p.sf.net/sfu/Challenge
>>>>
>>>> -- 
>>>> Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
>>>>   Python as a HDL: http://www.myhdl.org
>>>>   VHDL development, the modern way: http://www.sigasi.com
>>>>   Analog design automation: http://www.mephisto-da.com
>>>>   World-class digital design: http://www.easics.com
>>>>
>>>>
>>>> ------------------------------------------------------------------------------
>>>> Enter the BlackBerry Developer Challenge
>>>> This is your chance to win up to $100,000 in prizes! For a limited  
>>>> time,
>>>> vendors submitting new applications to BlackBerry App World(TM)  
>>>> will have
>>>> the opportunity to enter the BlackBerry Developer Challenge. See  
>>>> full
>>>> prize
>>>> details at: http://p.sf.net/sfu/Challenge
>>>> _______________________________________________
>>>> myhdl-list mailing list
>>>> myh...@li...
>>>> <mailto:myh...@li...>
>>>> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>>
>> ------------------------------------------------------------------------------
>> Enter the BlackBerry Developer Challenge
>> This is your chance to win up to $100,000 in prizes! For a limited  
>> time,
>> vendors submitting new applications to BlackBerry App World(TM) will  
>> have
>> the opportunity to enter the BlackBerry Developer Challenge. See  
>> full prize
>> details at: http://p.sf.net/sfu/Challenge
>> _______________________________________________
>> myhdl-list mailing list
>> myh...@li...
>> https://lists.sourceforge.net/lists/listinfo/myhdl-list
> 
> 
> 
> ------------------------------------------------------------------------------
> Enter the BlackBerry Developer Challenge  
> This is your chance to win up to $100,000 in prizes! For a limited time, 
> vendors submitting new applications to BlackBerry App World(TM) will have
> the opportunity to enter the BlackBerry Developer Challenge. See full prize  
> details at: http://p.sf.net/sfu/Challenge


-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
    Python as a HDL: http://www.myhdl.org
    VHDL development, the modern way: http://www.sigasi.com
    Analog design automation: http://www.mephisto-da.com
    World-class digital design: http://www.easics.com

Re: [myhdl-list] Programmable LFSR

[Christopher F. <chr...@gm...>]

Joseph Cali wrote:
> That worked perfectly.  I just added the "sbit = Signal(bitvector)"  
> and everything is converted with no problems.  The other cases where I  
> ran into the problem where identical.  Thanks for clearing that up for  
> me, I need to remember to wrap intbv with Signal before throwing it in  
> a generator.  Now I am off to see what Cadence tries to do with the  
> generated Verilog.
>
> Joseph
>   
MyHDL is more like VHDL in this sense.  You need to define the Signal 
and the Signal type.  Good luck with the rest of the adventure!  Let us 
know of your successes and problems (hopefully problems are limited).

Chris

> On Jul 20, 2009, at 9:40 AM, Christopher Felton wrote:
>
>   
>> You are now creating the constant / static bit-vector during the
>> elaboration phase (elaboration is great cause you can use all of
>> Python's power).  I think the issue is, the constant bit-vector exists
>> but what is the hardware representation of the "bitvector".  Kinda  
>> like
>> the RAM/ROM modules you posted about earlier.  I believe there still
>> needs to be some component for the bitvector, need a signal and  
>> possibly
>> addition generator that describes what bitvector (or corresponding
>> signal) is.
>>
>> First need a signal for the bitvector
>>
>> sbit = Signal(bitvector)
>>
>> Instead of if bitvectore[i], use if sbit[i]
>>
>> And possibly some behavioral definition that states what the sbit is  
>> in
>> hardware (register, combo constants, etc).  Example make it a register
>>
>> @always(clk.posedge)
>> def rtl_bitvector_reg():
>>    if rst:
>>        sbit.next = bitvector
>>
>>
>> I didn't test this but hopefully this will helps
>>
>> Chris
>>
>> Joseph Cali wrote:
>>     
>>> I tried to use the bitvector approach, but I am not getting a new
>>> error. I think that I am not using the intbv class correctly in some
>>> cases, as I have seen this error pop up several times in other MyHDL
>>> generators that I have written.  I also should note that I am using
>>> the most recent MyHDL from the mercurial repository.
>>>
>>> Here is the code
>>> ---------------------------------------------------------------------
>>>
>>> def Galois(out, clk, rst, width=32):
>>> '''
>>> Implement a Galois Linear Feedback Shift Register (LFSR).
>>>
>>> Parameters
>>> ----------
>>> width : integer
>>> The length of the LFSR
>>>
>>> Input Ports
>>> -----------
>>> clk : The clock
>>> rst : Active high reset
>>>
>>>
>>> Output Ports
>>> ------------
>>> out : Pseudo-Random word
>>> '''
>>> sel_table = width - 3
>>> polynomial = GALOIS_TABLE[sel_table]
>>> polynomial = polynomial[1:len(polynomial)-1]
>>> bitvector = intbv(0)[width:]
>>> for i in range(0, width):
>>> if i in polynomial:
>>> bitvector[i] = 1
>>> else:
>>> bitvector[i] = 0
>>>
>>>
>>>
>>> state = Signal(intbv(0)[width:])
>>>
>>> @always(clk.posedge, rst)
>>> def logic():
>>> if rst == 1:
>>> state.next[0] = 1
>>> else:
>>> state.next[width-1] = state[0]
>>> for i in downrange(width-1, 0):
>>> if bitvector[i]:
>>> state.next[i] = state[i+1] ^ state[0]
>>> else:
>>> state.next[i] = state[i+1]
>>>
>>>       
>>> Joseph
>>>
>>>
>>>
>>> On Jul 20, 2009, at 4:16 AM, Jan Decaluwe wrote:
>>>
>>>       
>>>> Syntax
>>>>
>>>>  if in ...
>>>>
>>>> is indeed not supported. This is currently not checked, hence the  
>>>> bad
>>>> stack trace instead of a clear error message.
>>>>
>>>> As a workaround, map the polynomial to a bitvector with the  
>>>> significant
>>>> bits set before using it inside a generator. Then you can use
>>>>
>>>>  if polynomial[i] ...
>>>>
>>>> as the check.
>>>>
>>>> Probably you mean state.next[i], not state[i].next.
>>>>
>>>> All code inside a generator is converted literally, so you will
>>>> get a for-loop in the output.
>>>>
>>>> Jan
>>>>
>>>>
>>>> Joseph Cali wrote:
>>>>         
>>>>> I am attempting to parameterize the creation of Galois LFSRs.  I
>>>>> have a table that contains Galois polynomials (a list of tuples
>>>>> named GALOIS_TABLE).  The following is my first attempt at a
>>>>> solution in MyHDL.
>>>>>
>>>>> def Galois(out, clk, rst, width=32):
>>>>> '''
>>>>> Implement a Galois Linear Feedback Shift Register (LFSR).
>>>>>
>>>>> Parameters
>>>>> ----------
>>>>> width : integer
>>>>> The length of the LFSR
>>>>>
>>>>> Input Ports
>>>>> -----------
>>>>> clk : The clock
>>>>> rst : Active high reset
>>>>>
>>>>> Output Ports
>>>>> ------------
>>>>> out : Pseudo-Random word
>>>>> '''
>>>>> sel_table = width - 3
>>>>> polynomial = GALOIS_TABLE[sel_table]
>>>>> polynomial = polynomial[1:len(polynomial)-1]  # Take the relevant
>>>>> part of the polynomial
>>>>>
>>>>> state = Signal(intbv(0)[width:])
>>>>>
>>>>> @always(clk.posedge, rst.negedge)
>>>>> def logic():
>>>>> if rst == 1:
>>>>> state.next[0] = 1
>>>>> else:
>>>>> state.next[width-1] = state[0]
>>>>> for i in downrange(width-1, 0):
>>>>> if i in polynomial:  # This is where the problem occurs, I believe
>>>>> state[i].next = state[i+1] ^ state[0]
>>>>> else:
>>>>> state[i].next = state[i+1]
>>>>>
>>>>> @always_comb
>>>>> def assignments():
>>>>> out.next = state
>>>>>
>>>>> return logic, assignments
>>>>>
>>>>>
>>>>> --------------------------------------------------------------------------------------------------------------------
>>>>> I do not think the "if i in whatever" syntax is convertible.  I was
>>>>> wondering if anyone had any
>>>>> suggestions on alternative Python code that would yield a
>>>>> convertible example.  Attempting
>>>>> to convert the above code gives the following stack trace using
>>>>> Python 2.6.2:
>>>>>
>>>>> File "galois.py", line 147, in <module>
>>>>>   galois = toVerilog(Galois, out, clk, rst, width=18)
>>>>> File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py",
>>>>> line 124, in __call__
>>>>>   _convertGens(genlist, vfile)
>>>>> File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py",
>>>>> line 321, in _convertGens
>>>>>   v.visit(tree)
>>>>> File "/usr/lib/python2.6/ast.py", line 231, in visit
>>>>>   return visitor(node)
>>>>> File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py",
>>>>> line 1248, in visit_Module
>>>>>   self.visit(stmt)
>>>>> File "/usr/lib/python2.6/ast.py", line 231, in visit
>>>>>   return visitor(node)
>>>>> File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py",
>>>>> line 1850, in visit_FunctionDef
>>>>>   self.visit_stmt(node.body)
>>>>> File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py",
>>>>> line 1599, in visit_stmt
>>>>>   self.visit(stmt)
>>>>> File "/usr/lib/python2.6/ast.py", line 231, in visit
>>>>>   return visitor(node)
>>>>> File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py",
>>>>> line 1177, in visit_If
>>>>>   self.mapToIf(node)
>>>>> File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py",
>>>>> line 1232, in mapToIf
>>>>>   self.visit_stmt(node.else_)
>>>>> File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py",
>>>>> line 1599, in visit_stmt
>>>>>   self.visit(stmt)
>>>>> File "/usr/lib/python2.6/ast.py", line 231, in visit
>>>>>   return visitor(node)
>>>>> File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py",
>>>>> line 1140, in visit_For
>>>>>   self.visit_stmt(node.body)
>>>>> File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py",
>>>>> line 1599, in visit_stmt
>>>>>   self.visit(stmt)
>>>>> File "/usr/lib/python2.6/ast.py", line 231, in visit
>>>>>   return visitor(node)
>>>>> File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py",
>>>>> line 1177, in visit_If
>>>>>   self.mapToIf(node)
>>>>> File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py",
>>>>> line 1221, in mapToIf
>>>>>   self.visit(test)
>>>>> File "/usr/lib/python2.6/ast.py", line 231, in visit
>>>>>   return visitor(node)
>>>>> File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py",
>>>>> line 969, in visit_Compare
>>>>>   self.write(" %s " % opmap[type(node.ops[0])])
>>>>> KeyError: <class '_ast.In'>
>>>>>
>>>>>
>>>>> --------------------------------------------------------------------------------------------------------------------
>>>>> For width=18,  a Galois polynomial is x^18 + x^11 + 1.  The target
>>>>> Verilog should behave as below:
>>>>>
>>>>> module galois18(state, clk, rst);
>>>>> input clk;
>>>>> input rst;
>>>>> output [17:0] state;
>>>>> reg [17:0] state;
>>>>>
>>>>> always @(posedge clk) begin
>>>>> if(~rst) begin
>>>>> state <= {state[0], state[17:12], state[11]^state[0], state[10:1]};
>>>>> end
>>>>> else begin
>>>>> state[0] <= 1;
>>>>> end
>>>>> end
>>>>> endmodule
>>>>>
>>>>>
>>>>>
>>>>> Joseph
>>>>>
>>>>> ------------------------------------------------------------------------------
>>>>> Enter the BlackBerry Developer Challenge
>>>>> This is your chance to win up to $100,000 in prizes! For a limited
>>>>> time,
>>>>> vendors submitting new applications to BlackBerry App World(TM)  
>>>>> will
>>>>> have
>>>>> the opportunity to enter the BlackBerry Developer Challenge. See
>>>>> full prize
>>>>> details at: http://p.sf.net/sfu/Challenge
>>>>>           
>>>> -- 
>>>> Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
>>>>   Python as a HDL: http://www.myhdl.org
>>>>   VHDL development, the modern way: http://www.sigasi.com
>>>>   Analog design automation: http://www.mephisto-da.com
>>>>   World-class digital design: http://www.easics.com
>>>>
>>>>
>>>> ------------------------------------------------------------------------------
>>>> Enter the BlackBerry Developer Challenge
>>>> This is your chance to win up to $100,000 in prizes! For a limited  
>>>> time,
>>>> vendors submitting new applications to BlackBerry App World(TM)  
>>>> will have
>>>> the opportunity to enter the BlackBerry Developer Challenge. See  
>>>> full
>>>> prize
>>>> details at: http://p.sf.net/sfu/Challenge
>>>> _______________________________________________
>>>> myhdl-list mailing list
>>>> myh...@li...
>>>> <mailto:myh...@li...>
>>>> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>>>>         
>> ------------------------------------------------------------------------------
>> Enter the BlackBerry Developer Challenge
>> This is your chance to win up to $100,000 in prizes! For a limited  
>> time,
>> vendors submitting new applications to BlackBerry App World(TM) will  
>> have
>> the opportunity to enter the BlackBerry Developer Challenge. See  
>> full prize
>> details at: http://p.sf.net/sfu/Challenge
>> _______________________________________________
>> myhdl-list mailing list
>> myh...@li...
>> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>>     
>
>
>
> ------------------------------------------------------------------------------
> Enter the BlackBerry Developer Challenge  
> This is your chance to win up to $100,000 in prizes! For a limited time, 
> vendors submitting new applications to BlackBerry App World(TM) will have
> the opportunity to enter the BlackBerry Developer Challenge. See full prize  
> details at: http://p.sf.net/sfu/Challenge
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>   

Re: [myhdl-list] Programmable LFSR

[Joseph C. <ca...@au...>]

That worked perfectly.  I just added the "sbit = Signal(bitvector)"  
and everything is converted with no problems.  The other cases where I  
ran into the problem where identical.  Thanks for clearing that up for  
me, I need to remember to wrap intbv with Signal before throwing it in  
a generator.  Now I am off to see what Cadence tries to do with the  
generated Verilog.

Joseph

On Jul 20, 2009, at 9:40 AM, Christopher Felton wrote:

> You are now creating the constant / static bit-vector during the
> elaboration phase (elaboration is great cause you can use all of
> Python's power).  I think the issue is, the constant bit-vector exists
> but what is the hardware representation of the "bitvector".  Kinda  
> like
> the RAM/ROM modules you posted about earlier.  I believe there still
> needs to be some component for the bitvector, need a signal and  
> possibly
> addition generator that describes what bitvector (or corresponding
> signal) is.
>
> First need a signal for the bitvector
>
> sbit = Signal(bitvector)
>
> Instead of if bitvectore[i], use if sbit[i]
>
> And possibly some behavioral definition that states what the sbit is  
> in
> hardware (register, combo constants, etc).  Example make it a register
>
> @always(clk.posedge)
> def rtl_bitvector_reg():
>    if rst:
>        sbit.next = bitvector
>
>
> I didn't test this but hopefully this will helps
>
> Chris
>
> Joseph Cali wrote:
>> I tried to use the bitvector approach, but I am not getting a new
>> error. I think that I am not using the intbv class correctly in some
>> cases, as I have seen this error pop up several times in other MyHDL
>> generators that I have written.  I also should note that I am using
>> the most recent MyHDL from the mercurial repository.
>>
>> Here is the code
>> ---------------------------------------------------------------------
>>
>> def Galois(out, clk, rst, width=32):
>> '''
>> Implement a Galois Linear Feedback Shift Register (LFSR).
>>
>> Parameters
>> ----------
>> width : integer
>> The length of the LFSR
>>
>> Input Ports
>> -----------
>> clk : The clock
>> rst : Active high reset
>>
>>
>> Output Ports
>> ------------
>> out : Pseudo-Random word
>> '''
>> sel_table = width - 3
>> polynomial = GALOIS_TABLE[sel_table]
>> polynomial = polynomial[1:len(polynomial)-1]
>> bitvector = intbv(0)[width:]
>> for i in range(0, width):
>> if i in polynomial:
>> bitvector[i] = 1
>> else:
>> bitvector[i] = 0
>>
>>
>>
>> state = Signal(intbv(0)[width:])
>>
>> @always(clk.posedge, rst)
>> def logic():
>> if rst == 1:
>> state.next[0] = 1
>> else:
>> state.next[width-1] = state[0]
>> for i in downrange(width-1, 0):
>> if bitvector[i]:
>> state.next[i] = state[i+1] ^ state[0]
>> else:
>> state.next[i] = state[i+1]
>>
>
>> Joseph
>>
>>
>>
>> On Jul 20, 2009, at 4:16 AM, Jan Decaluwe wrote:
>>
>>> Syntax
>>>
>>>  if in ...
>>>
>>> is indeed not supported. This is currently not checked, hence the  
>>> bad
>>> stack trace instead of a clear error message.
>>>
>>> As a workaround, map the polynomial to a bitvector with the  
>>> significant
>>> bits set before using it inside a generator. Then you can use
>>>
>>>  if polynomial[i] ...
>>>
>>> as the check.
>>>
>>> Probably you mean state.next[i], not state[i].next.
>>>
>>> All code inside a generator is converted literally, so you will
>>> get a for-loop in the output.
>>>
>>> Jan
>>>
>>>
>>> Joseph Cali wrote:
>>>> I am attempting to parameterize the creation of Galois LFSRs.  I
>>>> have a table that contains Galois polynomials (a list of tuples
>>>> named GALOIS_TABLE).  The following is my first attempt at a
>>>> solution in MyHDL.
>>>>
>>>> def Galois(out, clk, rst, width=32):
>>>> '''
>>>> Implement a Galois Linear Feedback Shift Register (LFSR).
>>>>
>>>> Parameters
>>>> ----------
>>>> width : integer
>>>> The length of the LFSR
>>>>
>>>> Input Ports
>>>> -----------
>>>> clk : The clock
>>>> rst : Active high reset
>>>>
>>>> Output Ports
>>>> ------------
>>>> out : Pseudo-Random word
>>>> '''
>>>> sel_table = width - 3
>>>> polynomial = GALOIS_TABLE[sel_table]
>>>> polynomial = polynomial[1:len(polynomial)-1]  # Take the relevant
>>>> part of the polynomial
>>>>
>>>> state = Signal(intbv(0)[width:])
>>>>
>>>> @always(clk.posedge, rst.negedge)
>>>> def logic():
>>>> if rst == 1:
>>>> state.next[0] = 1
>>>> else:
>>>> state.next[width-1] = state[0]
>>>> for i in downrange(width-1, 0):
>>>> if i in polynomial:  # This is where the problem occurs, I believe
>>>> state[i].next = state[i+1] ^ state[0]
>>>> else:
>>>> state[i].next = state[i+1]
>>>>
>>>> @always_comb
>>>> def assignments():
>>>> out.next = state
>>>>
>>>> return logic, assignments
>>>>
>>>>
>>>> --------------------------------------------------------------------------------------------------------------------
>>>> I do not think the "if i in whatever" syntax is convertible.  I was
>>>> wondering if anyone had any
>>>> suggestions on alternative Python code that would yield a
>>>> convertible example.  Attempting
>>>> to convert the above code gives the following stack trace using
>>>> Python 2.6.2:
>>>>
>>>> File "galois.py", line 147, in <module>
>>>>   galois = toVerilog(Galois, out, clk, rst, width=18)
>>>> File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py",
>>>> line 124, in __call__
>>>>   _convertGens(genlist, vfile)
>>>> File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py",
>>>> line 321, in _convertGens
>>>>   v.visit(tree)
>>>> File "/usr/lib/python2.6/ast.py", line 231, in visit
>>>>   return visitor(node)
>>>> File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py",
>>>> line 1248, in visit_Module
>>>>   self.visit(stmt)
>>>> File "/usr/lib/python2.6/ast.py", line 231, in visit
>>>>   return visitor(node)
>>>> File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py",
>>>> line 1850, in visit_FunctionDef
>>>>   self.visit_stmt(node.body)
>>>> File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py",
>>>> line 1599, in visit_stmt
>>>>   self.visit(stmt)
>>>> File "/usr/lib/python2.6/ast.py", line 231, in visit
>>>>   return visitor(node)
>>>> File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py",
>>>> line 1177, in visit_If
>>>>   self.mapToIf(node)
>>>> File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py",
>>>> line 1232, in mapToIf
>>>>   self.visit_stmt(node.else_)
>>>> File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py",
>>>> line 1599, in visit_stmt
>>>>   self.visit(stmt)
>>>> File "/usr/lib/python2.6/ast.py", line 231, in visit
>>>>   return visitor(node)
>>>> File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py",
>>>> line 1140, in visit_For
>>>>   self.visit_stmt(node.body)
>>>> File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py",
>>>> line 1599, in visit_stmt
>>>>   self.visit(stmt)
>>>> File "/usr/lib/python2.6/ast.py", line 231, in visit
>>>>   return visitor(node)
>>>> File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py",
>>>> line 1177, in visit_If
>>>>   self.mapToIf(node)
>>>> File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py",
>>>> line 1221, in mapToIf
>>>>   self.visit(test)
>>>> File "/usr/lib/python2.6/ast.py", line 231, in visit
>>>>   return visitor(node)
>>>> File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py",
>>>> line 969, in visit_Compare
>>>>   self.write(" %s " % opmap[type(node.ops[0])])
>>>> KeyError: <class '_ast.In'>
>>>>
>>>>
>>>> --------------------------------------------------------------------------------------------------------------------
>>>> For width=18,  a Galois polynomial is x^18 + x^11 + 1.  The target
>>>> Verilog should behave as below:
>>>>
>>>> module galois18(state, clk, rst);
>>>> input clk;
>>>> input rst;
>>>> output [17:0] state;
>>>> reg [17:0] state;
>>>>
>>>> always @(posedge clk) begin
>>>> if(~rst) begin
>>>> state <= {state[0], state[17:12], state[11]^state[0], state[10:1]};
>>>> end
>>>> else begin
>>>> state[0] <= 1;
>>>> end
>>>> end
>>>> endmodule
>>>>
>>>>
>>>>
>>>> Joseph
>>>>
>>>> ------------------------------------------------------------------------------
>>>> Enter the BlackBerry Developer Challenge
>>>> This is your chance to win up to $100,000 in prizes! For a limited
>>>> time,
>>>> vendors submitting new applications to BlackBerry App World(TM)  
>>>> will
>>>> have
>>>> the opportunity to enter the BlackBerry Developer Challenge. See
>>>> full prize
>>>> details at: http://p.sf.net/sfu/Challenge
>>>
>>>
>>> -- 
>>> Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
>>>   Python as a HDL: http://www.myhdl.org
>>>   VHDL development, the modern way: http://www.sigasi.com
>>>   Analog design automation: http://www.mephisto-da.com
>>>   World-class digital design: http://www.easics.com
>>>
>>>
>>> ------------------------------------------------------------------------------
>>> Enter the BlackBerry Developer Challenge
>>> This is your chance to win up to $100,000 in prizes! For a limited  
>>> time,
>>> vendors submitting new applications to BlackBerry App World(TM)  
>>> will have
>>> the opportunity to enter the BlackBerry Developer Challenge. See  
>>> full
>>> prize
>>> details at: http://p.sf.net/sfu/Challenge
>>> _______________________________________________
>>> myhdl-list mailing list
>>> myh...@li...
>>> <mailto:myh...@li...>
>>> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>>
>
>
> ------------------------------------------------------------------------------
> Enter the BlackBerry Developer Challenge
> This is your chance to win up to $100,000 in prizes! For a limited  
> time,
> vendors submitting new applications to BlackBerry App World(TM) will  
> have
> the opportunity to enter the BlackBerry Developer Challenge. See  
> full prize
> details at: http://p.sf.net/sfu/Challenge
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list

Re: [myhdl-list] Programmable LFSR

[Christopher F. <chr...@gm...>]

You are now creating the constant / static bit-vector during the 
elaboration phase (elaboration is great cause you can use all of 
Python's power).  I think the issue is, the constant bit-vector exists 
but what is the hardware representation of the "bitvector".  Kinda like 
the RAM/ROM modules you posted about earlier.  I believe there still 
needs to be some component for the bitvector, need a signal and possibly 
addition generator that describes what bitvector (or corresponding 
signal) is.

First need a signal for the bitvector

sbit = Signal(bitvector)

Instead of if bitvectore[i], use if sbit[i]

And possibly some behavioral definition that states what the sbit is in 
hardware (register, combo constants, etc).  Example make it a register

@always(clk.posedge)
def rtl_bitvector_reg():
    if rst:
        sbit.next = bitvector
  

I didn't test this but hopefully this will helps

Chris

Joseph Cali wrote:
> I tried to use the bitvector approach, but I am not getting a new 
> error. I think that I am not using the intbv class correctly in some 
> cases, as I have seen this error pop up several times in other MyHDL 
> generators that I have written.  I also should note that I am using 
> the most recent MyHDL from the mercurial repository.  
>
> Here is the code
> ---------------------------------------------------------------------
>
> def Galois(out, clk, rst, width=32):
> '''
> Implement a Galois Linear Feedback Shift Register (LFSR).
>
> Parameters
> ----------
> width : integer
> The length of the LFSR
>
> Input Ports
> -----------
> clk : The clock
> rst : Active high reset
>
>
> Output Ports
> ------------
> out : Pseudo-Random word
> '''
> sel_table = width - 3
> polynomial = GALOIS_TABLE[sel_table]
> polynomial = polynomial[1:len(polynomial)-1]
> bitvector = intbv(0)[width:]
> for i in range(0, width):
> if i in polynomial:
> bitvector[i] = 1
> else:
> bitvector[i] = 0
>
>
>
> state = Signal(intbv(0)[width:])
>
> @always(clk.posedge, rst)
> def logic():
> if rst == 1:
> state.next[0] = 1
> else:
> state.next[width-1] = state[0]
> for i in downrange(width-1, 0):
> if bitvector[i]:
> state.next[i] = state[i+1] ^ state[0]
> else:
> state.next[i] = state[i+1]
>

> Joseph
>
>
>
> On Jul 20, 2009, at 4:16 AM, Jan Decaluwe wrote:
>
>> Syntax
>>
>>   if in ...
>>
>> is indeed not supported. This is currently not checked, hence the bad
>> stack trace instead of a clear error message.
>>
>> As a workaround, map the polynomial to a bitvector with the significant
>> bits set before using it inside a generator. Then you can use
>>
>>   if polynomial[i] ...
>>
>> as the check.
>>
>> Probably you mean state.next[i], not state[i].next.
>>
>> All code inside a generator is converted literally, so you will
>> get a for-loop in the output.
>>
>> Jan
>>
>>
>> Joseph Cali wrote:
>>> I am attempting to parameterize the creation of Galois LFSRs.  I 
>>> have a table that contains Galois polynomials (a list of tuples 
>>> named GALOIS_TABLE).  The following is my first attempt at a 
>>> solution in MyHDL.
>>>
>>> def Galois(out, clk, rst, width=32):
>>> '''
>>> Implement a Galois Linear Feedback Shift Register (LFSR).
>>>
>>> Parameters
>>> ----------
>>> width : integer
>>> The length of the LFSR
>>>
>>> Input Ports
>>> -----------
>>> clk : The clock
>>> rst : Active high reset
>>>
>>> Output Ports
>>> ------------
>>> out : Pseudo-Random word
>>> '''
>>> sel_table = width - 3
>>> polynomial = GALOIS_TABLE[sel_table]
>>> polynomial = polynomial[1:len(polynomial)-1]  # Take the relevant 
>>> part of the polynomial
>>>
>>> state = Signal(intbv(0)[width:])
>>>
>>> @always(clk.posedge, rst.negedge)
>>> def logic():
>>> if rst == 1:
>>> state.next[0] = 1
>>> else:
>>> state.next[width-1] = state[0]
>>> for i in downrange(width-1, 0):
>>> if i in polynomial:  # This is where the problem occurs, I believe
>>> state[i].next = state[i+1] ^ state[0]
>>> else:
>>> state[i].next = state[i+1]
>>>
>>> @always_comb
>>> def assignments():
>>> out.next = state
>>>
>>> return logic, assignments
>>>
>>>
>>> --------------------------------------------------------------------------------------------------------------------
>>> I do not think the "if i in whatever" syntax is convertible.  I was 
>>> wondering if anyone had any
>>> suggestions on alternative Python code that would yield a 
>>> convertible example.  Attempting
>>> to convert the above code gives the following stack trace using 
>>> Python 2.6.2:
>>>
>>>  File "galois.py", line 147, in <module>
>>>    galois = toVerilog(Galois, out, clk, rst, width=18)
>>>  File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py", 
>>> line 124, in __call__
>>>    _convertGens(genlist, vfile)
>>>  File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py", 
>>> line 321, in _convertGens
>>>    v.visit(tree)
>>>  File "/usr/lib/python2.6/ast.py", line 231, in visit
>>>    return visitor(node)
>>>  File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py", 
>>> line 1248, in visit_Module
>>>    self.visit(stmt)
>>>  File "/usr/lib/python2.6/ast.py", line 231, in visit
>>>    return visitor(node)
>>>  File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py", 
>>> line 1850, in visit_FunctionDef
>>>    self.visit_stmt(node.body)
>>>  File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py", 
>>> line 1599, in visit_stmt
>>>    self.visit(stmt)
>>>  File "/usr/lib/python2.6/ast.py", line 231, in visit
>>>    return visitor(node)
>>>  File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py", 
>>> line 1177, in visit_If
>>>    self.mapToIf(node)
>>>  File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py", 
>>> line 1232, in mapToIf
>>>    self.visit_stmt(node.else_)
>>>  File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py", 
>>> line 1599, in visit_stmt
>>>    self.visit(stmt)
>>>  File "/usr/lib/python2.6/ast.py", line 231, in visit
>>>    return visitor(node)
>>>  File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py", 
>>> line 1140, in visit_For
>>>    self.visit_stmt(node.body)
>>>  File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py", 
>>> line 1599, in visit_stmt
>>>    self.visit(stmt)
>>>  File "/usr/lib/python2.6/ast.py", line 231, in visit
>>>    return visitor(node)
>>>  File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py", 
>>> line 1177, in visit_If
>>>    self.mapToIf(node)
>>>  File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py", 
>>> line 1221, in mapToIf
>>>    self.visit(test)
>>>  File "/usr/lib/python2.6/ast.py", line 231, in visit
>>>    return visitor(node)
>>>  File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py", 
>>> line 969, in visit_Compare
>>>    self.write(" %s " % opmap[type(node.ops[0])])
>>> KeyError: <class '_ast.In'>
>>>
>>>
>>> --------------------------------------------------------------------------------------------------------------------
>>> For width=18,  a Galois polynomial is x^18 + x^11 + 1.  The target
>>> Verilog should behave as below:
>>>
>>> module galois18(state, clk, rst);
>>> input clk;
>>> input rst;
>>> output [17:0] state;
>>> reg [17:0] state;
>>>
>>> always @(posedge clk) begin
>>> if(~rst) begin
>>> state <= {state[0], state[17:12], state[11]^state[0], state[10:1]};
>>> end
>>> else begin
>>> state[0] <= 1;
>>> end
>>> end
>>> endmodule
>>>
>>>
>>>
>>> Joseph
>>>
>>> ------------------------------------------------------------------------------
>>> Enter the BlackBerry Developer Challenge  
>>> This is your chance to win up to $100,000 in prizes! For a limited 
>>> time,
>>> vendors submitting new applications to BlackBerry App World(TM) will 
>>> have
>>> the opportunity to enter the BlackBerry Developer Challenge. See 
>>> full prize  
>>> details at: http://p.sf.net/sfu/Challenge
>>
>>
>> -- 
>> Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
>>    Python as a HDL: http://www.myhdl.org
>>    VHDL development, the modern way: http://www.sigasi.com
>>    Analog design automation: http://www.mephisto-da.com
>>    World-class digital design: http://www.easics.com
>>
>>
>> ------------------------------------------------------------------------------
>> Enter the BlackBerry Developer Challenge  
>> This is your chance to win up to $100,000 in prizes! For a limited time,
>> vendors submitting new applications to BlackBerry App World(TM) will have
>> the opportunity to enter the BlackBerry Developer Challenge. See full 
>> prize  
>> details at: http://p.sf.net/sfu/Challenge
>> _______________________________________________
>> myhdl-list mailing list
>> myh...@li... 
>> <mailto:myh...@li...>
>> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>
>
> Joseph Cali
> ca...@au... <mailto:ca...@au...>
> Graduate Research Assistant
> Auburn University
> Work:  334-844-8257

Re: [myhdl-list] Programmable LFSR

[Joseph C. <ca...@au...>]

I tried to use the bitvector approach, but I am not getting a new  
error. I think that I am not using the intbv class correctly in some  
cases, as I have seen this error pop up several times in other MyHDL  
generators that I have written.  I also should note that I am using  
the most recent MyHDL from the mercurial repository.

Here is the code
---------------------------------------------------------------------

def Galois(out, clk, rst, width=32):
	'''
	Implement a Galois Linear Feedback Shift Register (LFSR).

	Parameters
	----------
	width : integer
		The length of the LFSR

	Input Ports
	-----------
	clk : The clock
	rst : Active high reset
	
	Output Ports
	------------
	out : Pseudo-Random word
	'''
	sel_table = width - 3
	polynomial = GALOIS_TABLE[sel_table]
	polynomial = polynomial[1:len(polynomial)-1]
	bitvector = intbv(0)[width:]
	for i in range(0, width):
		if i in polynomial:
			bitvector[i] = 1
		else:
			bitvector[i] = 0
	

	state = Signal(intbv(0)[width:])

	@always(clk.posedge, rst)
	def logic():
		if rst == 1:
			state.next[0] = 1
		else:
			state.next[width-1] = state[0]
			for i in downrange(width-1, 0):
				if bitvector[i]:
					state.next[i] = state[i+1] ^ state[0]
				else:
					state.next[i] = state[i+1]



Here is the error (line 136 is the ``if bitvector[i]`` line)
---------------------------------------------------------------------
Traceback (most recent call last):
   File "galois.py", line 158, in <module>
     galois = toVerilog(Galois, out, clk, rst, width=18)
   File "/Users/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py",  
line 124, in __call__
     _convertGens(genlist, vfile)
   File "/Users/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py",  
line 321, in _convertGens
     v.visit(tree)
   File "/opt/local/Library/Frameworks/Python.framework/Versions/2.6/ 
lib/python2.6/ast.py", line 231, in visit
     return visitor(node)
   File "/Users/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py",  
line 1248, in visit_Module
     self.visit(stmt)
   File "/opt/local/Library/Frameworks/Python.framework/Versions/2.6/ 
lib/python2.6/ast.py", line 231, in visit
     return visitor(node)
   File "/Users/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py",  
line 1850, in visit_FunctionDef
     self.visit_stmt(node.body)
   File "/Users/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py",  
line 1599, in visit_stmt
     self.visit(stmt)
   File "/opt/local/Library/Frameworks/Python.framework/Versions/2.6/ 
lib/python2.6/ast.py", line 231, in visit
     return visitor(node)
   File "/Users/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py",  
line 1177, in visit_If
     self.mapToIf(node)
   File "/Users/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py",  
line 1232, in mapToIf
     self.visit_stmt(node.else_)
   File "/Users/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py",  
line 1599, in visit_stmt
     self.visit(stmt)
   File "/opt/local/Library/Frameworks/Python.framework/Versions/2.6/ 
lib/python2.6/ast.py", line 231, in visit
     return visitor(node)
   File "/Users/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py",  
line 1140, in visit_For
     self.visit_stmt(node.body)
   File "/Users/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py",  
line 1599, in visit_stmt
     self.visit(stmt)
   File "/opt/local/Library/Frameworks/Python.framework/Versions/2.6/ 
lib/python2.6/ast.py", line 231, in visit
     return visitor(node)
   File "/Users/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py",  
line 1177, in visit_If
     self.mapToIf(node)
   File "/Users/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py",  
line 1221, in mapToIf
     self.visit(test)
   File "/opt/local/Library/Frameworks/Python.framework/Versions/2.6/ 
lib/python2.6/ast.py", line 231, in visit
     return visitor(node)
   File "/Users/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py",  
line 1538, in visit_Subscript
     self.accessIndex(node)
   File "/Users/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py",  
line 1579, in accessIndex
     self.visit(node.value)
   File "/opt/local/Library/Frameworks/Python.framework/Versions/2.6/ 
lib/python2.6/ast.py", line 231, in visit
     return visitor(node)
   File "/Users/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py",  
line 1305, in visit_Name
     self.getName(node)
   File "/Users/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py",  
line 1346, in getName
     self.raiseError(node, _error.UnsupportedType, "%s, %s" % (n,  
type(obj)))
   File "/Users/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py",  
line 370, in raiseError
     raise ToVerilogError(kind, msg, info)
myhdl.ToVerilogError: in file galois.py, line 136:
     Object type is not supported in this context: bitvector, <class  
'myhdl._intbv.intbv'>

Joseph



On Jul 20, 2009, at 4:16 AM, Jan Decaluwe wrote:

> Syntax
>
>   if in ...
>
> is indeed not supported. This is currently not checked, hence the bad
> stack trace instead of a clear error message.
>
> As a workaround, map the polynomial to a bitvector with the  
> significant
> bits set before using it inside a generator. Then you can use
>
>   if polynomial[i] ...
>
> as the check.
>
> Probably you mean state.next[i], not state[i].next.
>
> All code inside a generator is converted literally, so you will
> get a for-loop in the output.
>
> Jan
>
>
> Joseph Cali wrote:
>> I am attempting to parameterize the creation of Galois LFSRs.  I  
>> have a table that contains Galois polynomials (a list of tuples  
>> named GALOIS_TABLE).  The following is my first attempt at a  
>> solution in MyHDL.
>>
>> def Galois(out, clk, rst, width=32):
>> 	'''
>> 	Implement a Galois Linear Feedback Shift Register (LFSR).
>>
>> 	Parameters
>> 	----------
>> 	width : integer
>> 		The length of the LFSR
>>
>> 	Input Ports
>> 	-----------
>> 	clk : The clock
>> 	rst : Active high reset
>> 	
>> 	Output Ports
>> 	------------
>> 	out : Pseudo-Random word
>> 	'''
>> 	sel_table = width - 3
>> 	polynomial = GALOIS_TABLE[sel_table]
>> 	polynomial = polynomial[1:len(polynomial)-1]  # Take the relevant  
>> part of the polynomial
>>
>> 	state = Signal(intbv(0)[width:])
>>
>> 	@always(clk.posedge, rst.negedge)
>> 	def logic():
>> 		if rst == 1:
>> 			state.next[0] = 1
>> 		else:
>> 			state.next[width-1] = state[0]
>> 			for i in downrange(width-1, 0):
>> 				if i in polynomial:  # This is where the problem occurs, I  
>> believe
>> 					state[i].next = state[i+1] ^ state[0]
>> 				else:
>> 					state[i].next = state[i+1]
>> 	
>> 	@always_comb
>> 	def assignments():
>> 		out.next = state		
>>
>> 	return logic, assignments
>>
>>
>> --------------------------------------------------------------------------------------------------------------------
>> I do not think the "if i in whatever" syntax is convertible.  I was  
>> wondering if anyone had any
>> suggestions on alternative Python code that would yield a  
>> convertible example.  Attempting
>> to convert the above code gives the following stack trace using  
>> Python 2.6.2:
>>
>>  File "galois.py", line 147, in <module>
>>    galois = toVerilog(Galois, out, clk, rst, width=18)
>>  File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py",  
>> line 124, in __call__
>>    _convertGens(genlist, vfile)
>>  File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py",  
>> line 321, in _convertGens
>>    v.visit(tree)
>>  File "/usr/lib/python2.6/ast.py", line 231, in visit
>>    return visitor(node)
>>  File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py",  
>> line 1248, in visit_Module
>>    self.visit(stmt)
>>  File "/usr/lib/python2.6/ast.py", line 231, in visit
>>    return visitor(node)
>>  File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py",  
>> line 1850, in visit_FunctionDef
>>    self.visit_stmt(node.body)
>>  File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py",  
>> line 1599, in visit_stmt
>>    self.visit(stmt)
>>  File "/usr/lib/python2.6/ast.py", line 231, in visit
>>    return visitor(node)
>>  File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py",  
>> line 1177, in visit_If
>>    self.mapToIf(node)
>>  File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py",  
>> line 1232, in mapToIf
>>    self.visit_stmt(node.else_)
>>  File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py",  
>> line 1599, in visit_stmt
>>    self.visit(stmt)
>>  File "/usr/lib/python2.6/ast.py", line 231, in visit
>>    return visitor(node)
>>  File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py",  
>> line 1140, in visit_For
>>    self.visit_stmt(node.body)
>>  File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py",  
>> line 1599, in visit_stmt
>>    self.visit(stmt)
>>  File "/usr/lib/python2.6/ast.py", line 231, in visit
>>    return visitor(node)
>>  File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py",  
>> line 1177, in visit_If
>>    self.mapToIf(node)
>>  File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py",  
>> line 1221, in mapToIf
>>    self.visit(test)
>>  File "/usr/lib/python2.6/ast.py", line 231, in visit
>>    return visitor(node)
>>  File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py",  
>> line 969, in visit_Compare
>>    self.write(" %s " % opmap[type(node.ops[0])])
>> KeyError: <class '_ast.In'>
>>
>>
>> --------------------------------------------------------------------------------------------------------------------
>> For width=18,  a Galois polynomial is x^18 + x^11 + 1.  The target
>> Verilog should behave as below:
>>
>> module galois18(state, clk, rst);
>> 	input clk;
>> 	input rst;
>> 	output [17:0] state;
>> 	reg [17:0] state;
>>
>> 	always @(posedge clk) begin
>> 		if(~rst) begin
>> 			state <= {state[0], state[17:12], state[11]^state[0],  
>> state[10:1]};
>> 		end
>> 		else begin
>> 			state[0] <= 1;
>> 		end
>> 	end
>> endmodule
>>
>>
>>
>> Joseph
>>
>> ------------------------------------------------------------------------------
>> Enter the BlackBerry Developer Challenge
>> This is your chance to win up to $100,000 in prizes! For a limited  
>> time,
>> vendors submitting new applications to BlackBerry App World(TM)  
>> will have
>> the opportunity to enter the BlackBerry Developer Challenge. See  
>> full prize
>> details at: http://p.sf.net/sfu/Challenge
>
>
> -- 
> Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
>    Python as a HDL: http://www.myhdl.org
>    VHDL development, the modern way: http://www.sigasi.com
>    Analog design automation: http://www.mephisto-da.com
>    World-class digital design: http://www.easics.com
>
>
> ------------------------------------------------------------------------------
> Enter the BlackBerry Developer Challenge
> This is your chance to win up to $100,000 in prizes! For a limited  
> time,
> vendors submitting new applications to BlackBerry App World(TM) will  
> have
> the opportunity to enter the BlackBerry Developer Challenge. See  
> full prize
> details at: http://p.sf.net/sfu/Challenge
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list


Joseph Cali
ca...@au...
Graduate Research Assistant
Auburn University
Work:  334-844-8257

Re: [myhdl-list] Programmable LFSR

[Jan D. <ja...@ja...>]

Syntax

   if in ...

is indeed not supported. This is currently not checked, hence the bad
stack trace instead of a clear error message.

As a workaround, map the polynomial to a bitvector with the significant
bits set before using it inside a generator. Then you can use

   if polynomial[i] ...

as the check.

Probably you mean state.next[i], not state[i].next.

All code inside a generator is converted literally, so you will
get a for-loop in the output.

Jan


Joseph Cali wrote:
> I am attempting to parameterize the creation of Galois LFSRs.  I have a table that contains Galois polynomials (a list of tuples named GALOIS_TABLE).  The following is my first attempt at a solution in MyHDL. 
> 
> def Galois(out, clk, rst, width=32):
> 	'''
> 	Implement a Galois Linear Feedback Shift Register (LFSR).
> 
> 	Parameters
> 	----------
> 	width : integer
> 		The length of the LFSR
> 
> 	Input Ports
> 	-----------
> 	clk : The clock
> 	rst : Active high reset
> 	
> 	Output Ports
> 	------------
> 	out : Pseudo-Random word
> 	'''
> 	sel_table = width - 3
> 	polynomial = GALOIS_TABLE[sel_table]
> 	polynomial = polynomial[1:len(polynomial)-1]  # Take the relevant part of the polynomial
> 
> 	state = Signal(intbv(0)[width:])
> 
> 	@always(clk.posedge, rst.negedge)
> 	def logic():
> 		if rst == 1:
> 			state.next[0] = 1
> 		else:
> 			state.next[width-1] = state[0]
> 			for i in downrange(width-1, 0):
> 				if i in polynomial:  # This is where the problem occurs, I believe
> 					state[i].next = state[i+1] ^ state[0]
> 				else:
> 					state[i].next = state[i+1]
> 	
> 	@always_comb
> 	def assignments():
> 		out.next = state		
> 
> 	return logic, assignments
> 
> 
> --------------------------------------------------------------------------------------------------------------------
> I do not think the "if i in whatever" syntax is convertible.  I was wondering if anyone had any
> suggestions on alternative Python code that would yield a convertible example.  Attempting
> to convert the above code gives the following stack trace using Python 2.6.2:
> 
>   File "galois.py", line 147, in <module>
>     galois = toVerilog(Galois, out, clk, rst, width=18)
>   File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py", line 124, in __call__
>     _convertGens(genlist, vfile)
>   File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py", line 321, in _convertGens
>     v.visit(tree)
>   File "/usr/lib/python2.6/ast.py", line 231, in visit
>     return visitor(node)
>   File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py", line 1248, in visit_Module
>     self.visit(stmt)
>   File "/usr/lib/python2.6/ast.py", line 231, in visit
>     return visitor(node)
>   File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py", line 1850, in visit_FunctionDef
>     self.visit_stmt(node.body)
>   File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py", line 1599, in visit_stmt
>     self.visit(stmt)
>   File "/usr/lib/python2.6/ast.py", line 231, in visit
>     return visitor(node)
>   File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py", line 1177, in visit_If
>     self.mapToIf(node)
>   File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py", line 1232, in mapToIf
>     self.visit_stmt(node.else_)
>   File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py", line 1599, in visit_stmt
>     self.visit(stmt)
>   File "/usr/lib/python2.6/ast.py", line 231, in visit
>     return visitor(node)
>   File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py", line 1140, in visit_For
>     self.visit_stmt(node.body)
>   File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py", line 1599, in visit_stmt
>     self.visit(stmt)
>   File "/usr/lib/python2.6/ast.py", line 231, in visit
>     return visitor(node)
>   File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py", line 1177, in visit_If
>     self.mapToIf(node)
>   File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py", line 1221, in mapToIf
>     self.visit(test)
>   File "/usr/lib/python2.6/ast.py", line 231, in visit
>     return visitor(node)
>   File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py", line 969, in visit_Compare
>     self.write(" %s " % opmap[type(node.ops[0])])
> KeyError: <class '_ast.In'>
> 
> 
> --------------------------------------------------------------------------------------------------------------------
> For width=18,  a Galois polynomial is x^18 + x^11 + 1.  The target 
> Verilog should behave as below:
> 
> module galois18(state, clk, rst);
> 	input clk;
> 	input rst;
> 	output [17:0] state;
> 	reg [17:0] state;
> 
> 	always @(posedge clk) begin
> 		if(~rst) begin
> 			state <= {state[0], state[17:12], state[11]^state[0], state[10:1]};
> 		end
> 		else begin
> 			state[0] <= 1;
> 		end
> 	end
> endmodule
> 
> 
> 
> Joseph
> 
> ------------------------------------------------------------------------------
> Enter the BlackBerry Developer Challenge  
> This is your chance to win up to $100,000 in prizes! For a limited time, 
> vendors submitting new applications to BlackBerry App World(TM) will have
> the opportunity to enter the BlackBerry Developer Challenge. See full prize  
> details at: http://p.sf.net/sfu/Challenge


-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
    Python as a HDL: http://www.myhdl.org
    VHDL development, the modern way: http://www.sigasi.com
    Analog design automation: http://www.mephisto-da.com
    World-class digital design: http://www.easics.com

[myhdl-list] Programmable LFSR

[Joseph C. <ca...@au...>]

I am attempting to parameterize the creation of Galois LFSRs.  I have a table that contains Galois polynomials (a list of tuples named GALOIS_TABLE).  The following is my first attempt at a solution in MyHDL. 

def Galois(out, clk, rst, width=32):
	'''
	Implement a Galois Linear Feedback Shift Register (LFSR).

	Parameters
	----------
	width : integer
		The length of the LFSR

	Input Ports
	-----------
	clk : The clock
	rst : Active high reset
	
	Output Ports
	------------
	out : Pseudo-Random word
	'''
	sel_table = width - 3
	polynomial = GALOIS_TABLE[sel_table]
	polynomial = polynomial[1:len(polynomial)-1]  # Take the relevant part of the polynomial

	state = Signal(intbv(0)[width:])

	@always(clk.posedge, rst.negedge)
	def logic():
		if rst == 1:
			state.next[0] = 1
		else:
			state.next[width-1] = state[0]
			for i in downrange(width-1, 0):
				if i in polynomial:  # This is where the problem occurs, I believe
					state[i].next = state[i+1] ^ state[0]
				else:
					state[i].next = state[i+1]
	
	@always_comb
	def assignments():
		out.next = state		

	return logic, assignments


--------------------------------------------------------------------------------------------------------------------
I do not think the "if i in whatever" syntax is convertible.  I was wondering if anyone had any
suggestions on alternative Python code that would yield a convertible example.  Attempting
to convert the above code gives the following stack trace using Python 2.6.2:

  File "galois.py", line 147, in <module>
    galois = toVerilog(Galois, out, clk, rst, width=18)
  File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py", line 124, in __call__
    _convertGens(genlist, vfile)
  File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py", line 321, in _convertGens
    v.visit(tree)
  File "/usr/lib/python2.6/ast.py", line 231, in visit
    return visitor(node)
  File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py", line 1248, in visit_Module
    self.visit(stmt)
  File "/usr/lib/python2.6/ast.py", line 231, in visit
    return visitor(node)
  File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py", line 1850, in visit_FunctionDef
    self.visit_stmt(node.body)
  File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py", line 1599, in visit_stmt
    self.visit(stmt)
  File "/usr/lib/python2.6/ast.py", line 231, in visit
    return visitor(node)
  File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py", line 1177, in visit_If
    self.mapToIf(node)
  File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py", line 1232, in mapToIf
    self.visit_stmt(node.else_)
  File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py", line 1599, in visit_stmt
    self.visit(stmt)
  File "/usr/lib/python2.6/ast.py", line 231, in visit
    return visitor(node)
  File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py", line 1140, in visit_For
    self.visit_stmt(node.body)
  File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py", line 1599, in visit_stmt
    self.visit(stmt)
  File "/usr/lib/python2.6/ast.py", line 231, in visit
    return visitor(node)
  File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py", line 1177, in visit_If
    self.mapToIf(node)
  File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py", line 1221, in mapToIf
    self.visit(test)
  File "/usr/lib/python2.6/ast.py", line 231, in visit
    return visitor(node)
  File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py", line 969, in visit_Compare
    self.write(" %s " % opmap[type(node.ops[0])])
KeyError: <class '_ast.In'>


--------------------------------------------------------------------------------------------------------------------
For width=18,  a Galois polynomial is x^18 + x^11 + 1.  The target 
Verilog should behave as below:

module galois18(state, clk, rst);
	input clk;
	input rst;
	output [17:0] state;
	reg [17:0] state;

	always @(posedge clk) begin
		if(~rst) begin
			state <= {state[0], state[17:12], state[11]^state[0], state[10:1]};
		end
		else begin
			state[0] <= 1;
		end
	end
endmodule



Joseph