Result of concat() is not resized in VHDL output

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#43 Result of concat() is not resized in VHDL output

Milestone: Development

Status: closed-fixed

Owner: Jan Decaluwe

Labels: None

Priority: 5

Updated: 2013-09-22

Created: 2013-08-25

Creator: Benjamin Berg

Private: No

See attached example.

In the first case
sigout <= unsigned'(sigin(0) & sigin(2));
is generated. In the second case:
tmp := unsigned'(sigin(0) & sigin(2));
sigout <= resize(tmp, 4);

I guess that it should become:
sigout <= resize(unsigned'(sigin(0) & sigin(2)), 4);

1 Attachments

test.py

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Jan Decaluwe - 2013-09-22

status: open --> closed-fixed

assigned_to: Jan Decaluwe
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Jan Decaluwe - 2013-09-22

Fixed in development.

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Result of concat() is not resized in VHDL output

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#43 Result of concat() is not resized in VHDL output

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