Conversion comparison incorrect

Brought to you by: jandecaluwe

#36 Conversion comparison incorrect

Milestone: MyHDL_0.7

Status: closed-fixed

Owner: Jan Decaluwe

Labels: Conversion to VHDL (7)

Priority: 5

Updated: 2013-02-17

Created: 2012-10-17

Private: No

In the attached testcase, where count and depth are both integer variables (not Signals) the line:

if count < depth:

is converted as:

if (to_std_logic(count) < '8') then

Jan Decaluwe - 2013-02-17

Fixed in 0.8-dev

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Jan Decaluwe - 2013-02-17

status: open --> closed-fixed
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Jan Decaluwe - 2013-02-17

assigned_to: nobody --> jandecaluwe
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