Incorrect generating of VHDL 'procedure' code

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#35 Incorrect generating of VHDL 'procedure' code

Milestone: MyHDL_0.7

Status: closed-fixed

Owner: Jan Decaluwe

Labels: Conversion to VHDL (7)

Priority: 5

Updated: 2013-02-17

Created: 2012-08-02

Creator: Anonymous

Private: No

VHDL generator glues together the procedure name and "is" word:

generated

> procedure MYHDLXXX_procnameis
> begin
> ...
> end procedure MYHDLXXX_procname;

instead of

> procedure MYHDLXXX_procname is
> begin
> ...
> end procedure MYHDLXXX_procname;

Jan Decaluwe - 2013-02-17

Fixed in 0.8-dev

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Jan Decaluwe - 2013-02-17

status: open --> closed-fixed
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