#29 elif not fully supported?

[Sjoerd Op 't Land]

Because I'm lazy, I often use elif: instead of else:if:. If I understood the manual correctly. this should be supported. However, the second architecture in the attached file does not convert. Maybe there is an essential difference that I overlooked.

Traceback (most recent call last):
File "/Users/sjoerd/Documents/Studie/VLSI/Arx-myHDL comparison/implementation/src/eliftest.py", line 41, in <module>
convertFlipFlop()
File "/Users/sjoerd/Documents/Studie/VLSI/Arx-myHDL comparison/implementation/src/eliftest.py", line 38, in convertFlipFlop
toVHDL(ElifFlipFlop,reset,clock,dataIn,qOut,enable)
File "/opt/local/Library/Frameworks/Python.framework/Versions/2.6/lib/python2.6/site-packages/myhdl/conversion/_toVHDL.py", line 165, in __call__
_convertGens(genlist, siglist, vfile)
File "/opt/local/Library/Frameworks/Python.framework/Versions/2.6/lib/python2.6/site-packages/myhdl/conversion/_toVHDL.py", line 376, in _convertGens
v.visit(tree)
File "/opt/local/Library/Frameworks/Python.framework/Versions/2.6/lib/python2.6/ast.py", line 231, in visit
return visitor(node)
File "/opt/local/Library/Frameworks/Python.framework/Versions/2.6/lib/python2.6/site-packages/myhdl/conversion/_toVHDL.py", line 1126, in visit_Module
self.visit(stmt)
File "/opt/local/Library/Frameworks/Python.framework/Versions/2.6/lib/python2.6/ast.py", line 231, in visit
return visitor(node)
File "/opt/local/Library/Frameworks/Python.framework/Versions/2.6/lib/python2.6/site-packages/myhdl/conversion/_toVHDL.py", line 1545, in visit_FunctionDef
senslist = self.manageEdges(node.body[-1], senslist)
File "/opt/local/Library/Frameworks/Python.framework/Versions/2.6/lib/python2.6/site-packages/myhdl/conversion/_toVHDL.py", line 1387, in manageEdges
self.raiseError(ifnode, "No separate else clause found")
File "/opt/local/Library/Frameworks/Python.framework/Versions/2.6/lib/python2.6/site-packages/myhdl/conversion/_misc.py", line 148, in raiseError
raise ConversionError(kind, msg, info)
myhdl.ConversionError: in file /Users/sjoerd/Documents/Studie/VLSI/Arx-myHDL comparison/implementation/src/eliftest.py, line 23:
No separate else clause found

[Sjoerd Op 't Land]

[Jan Decaluwe]

The problems is that this is a "special" elif, which implicitly also contains the clock condition. I have to do some special things to convert MyHDL templates for clocked processes to the VHDL equivalent, and this has some limitations. It may be possible to do this more generally, but currently the limitation is that there should be a separate "else" clause. I can see that the error message should be more descriptive though.

Inside "functional" code, elif is fully supported.