#27 no edge test error

[Sjoerd Op 't Land]

The example below fails to be converted to VHDL (with toVHDL()), but succeeds to be converted to Verilog (with toVerilog()). I could not find VHDL/Veriglog difference remarks on this basic example in the manual, so I suppose it is a bug. If not, maybe the error message (no edge test) should be more solution-suggesting?

I'm using the 0.7dev version (up to date to 28-05-2010, 11:37:24 CEST).

=== playground_test.py ===

from myhdl import *

def dffa(q, d, clk, rst):

@always(clk.posedge, rst.negedge)
def logic():
if rst == 0:
q.next = 0
else:
q.next = d

return logic

def convert():
q, d, clk, rst = [Signal(bool(0)) for i in range(4)]
toVHDL(dffa, q, d, clk, rst)

convert()

=== output ===
Traceback (most recent call last):
File "/Users/sjoerd/Documents/Studie/VLSI/Arx-myHDL comparison/implementation/src/playground_test.py", line 18, in <module>
convert()
File "/Users/sjoerd/Documents/Studie/VLSI/Arx-myHDL comparison/implementation/src/playground_test.py", line 16, in convert
toVHDL(dffa, q, d, clk, rst)
File "/opt/local/Library/Frameworks/Python.framework/Versions/2.6/lib/python2.6/site-packages/myhdl/conversion/_toVHDL.py", line 148, in __call__
_convertGens(genlist, siglist, vfile)
File "/opt/local/Library/Frameworks/Python.framework/Versions/2.6/lib/python2.6/site-packages/myhdl/conversion/_toVHDL.py", line 334, in _convertGens
v.visit(tree)
File "/opt/local/Library/Frameworks/Python.framework/Versions/2.6/lib/python2.6/ast.py", line 231, in visit
return visitor(node)
File "/opt/local/Library/Frameworks/Python.framework/Versions/2.6/lib/python2.6/site-packages/myhdl/conversion/_toVHDL.py", line 1669, in visit_Module
self.visit(stmt)
File "/opt/local/Library/Frameworks/Python.framework/Versions/2.6/lib/python2.6/ast.py", line 231, in visit
return visitor(node)
File "/opt/local/Library/Frameworks/Python.framework/Versions/2.6/lib/python2.6/site-packages/myhdl/conversion/_toVHDL.py", line 2454, in visit_FunctionDef
senslist = self.manageEdges(node.body[-1], senslist)
File "/opt/local/Library/Frameworks/Python.framework/Versions/2.6/lib/python2.6/site-packages/myhdl/conversion/_toVHDL.py", line 2179, in manageEdges
self.raiseError(ifnode, "no edge test")
File "/opt/local/Library/Frameworks/Python.framework/Versions/2.6/lib/python2.6/site-packages/myhdl/conversion/_misc.py", line 141, in raiseError
raise ConversionError(kind, msg, info)
myhdl.ConversionError: in file /Users/sjoerd/Documents/Studie/VLSI/Arx-myHDL comparison/implementation/src/playground_test.py, line 7:
no edge test
=== end ===

[Jan Decaluwe]

Thanks for debugging.

The bugs was related to the conversion from the old compiler package to the new ast package. The disturbing thing to me was why this wasn't revealed by the unit tests. It turns out that the bug only happens when one uses numeric literals in edge tests. But in the unit test I always did it "right", that is by using symbolic constants instead :-)

I have changed the unit tests to reveal this bug, and I have then solved the bug. The patch is already pushed to the development branch.