#20 concat and intbv

[h2opolo]

I'm fairly new to myhdl; but I've been using many mixed signal design tools for years. I use tools like ncverilog, vcs, etc. Myhdl looks very promising for mixed signal design. Anyway, I noticed that when I try to specify a bit width and assign it a value it seems like I have to use an additional bit. For example, if I try to do the following:

a = intbv(2)[2:]

It does not like it and I end up having to add additional bit (e.g. a = intbv(2)[3:] ). When converting Verilog code to Python, there are occasions where I have to concatenate signals like the following example:

b = {4'b1011,a[1:0]} and in this case I would create a 6 bit bus. It seems like I have to add a bit or I don't get the correct value. It almost seems like the upper bit gets chopped off. It doesn't look like this was fixed for the 0.6 development version. Is there a reason for this? Like dealing with signed integers or something. It makes conversion to and from Verilog a little cumbersome.

Jon

[Jan Decaluwe]

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I think you're confused about how slicing works in MyHDL (and Python). Have you read this:

http://www.jandecaluwe.com/Tools/MyHDL/manual/intro-slicing.html

Issues like this are better discussed on the mailing list/newsgroup first.

[SourceForge Robot]

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