Subfunctions do not have their on local namespace.
This code
===================================
def SubFunction(xout,yout,xin,yin):
@always_comb
def logic():
x = 4
y = 2
xout.next = xin
yout.next = yin
return instances()
def Function(xout,yout,x,y):
return SubFunction(xout,yout,x,y)
x = Signal(bool(0))
y = Signal(bool(0))
xout = Signal(bool(0))
yout = Signal(bool(0))
xin = Signal(bool(0))
yin = Signal(bool(0))
toVerilog(SubFunction,xout,yout,x,y)
toVerilog(Function,xout,yout,xin,yin)
=======================================
converts to
===========================================
always @(yin, xin) begin: SUBFUNCTION_LOGIC
integer y;
integer x;
x = 4;
y = 2;
xout <= xin;
yout <= yin;
end
============================================
in SubFunction.v
But Functions.v looks like this
============================================
always @(y, x) begin: FUNCTION_LOGIC
integer y;
integer x;
x = 4;
y = 2;
xout <= x;
yout <= y;
end
============================================
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The problem here is that the hierarchy is flattened during conversion. Signal names therefore
get a global, hierarchical name, that can potentially clash with local variable names.
Ideally, the names of local variables should be changed upon a clash. But this may be tricky.
As a workaround for now, I propose to detect this situation and to stop with a ConversionError to prevent illegal code being produced. The user can then change some names manually. I know it's not ideal.
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