Re: [MinGW-dvlpr] _M_IX86 predefines

[Danny S. <dan...@cl...>]

----- Original Message -----
From: "Oscar Fuentes" <of...@wa...>
To: <min...@li...>
Sent: Tuesday, 3 June 2003 17:43
Subject: Re: [MinGW-dvlpr] _M_IX86 predefines


> Danny Smith <dan...@cl...> writes:
>
> > I was going to submit a ptach to the MS style _M_IX86 defines as
> > builtins:

 ===snip===

> >
> >  MS docs say  their  /G7 switch applies to Athlon and P4

> Maybe I'm overlooking other factors, but at first sight Athlon's
> optimizations seems more related to the Pentium III.

Here is the MSDN ref:


http://msdn.microsoft.com/library/default.asp?url=/library/en-us/vccore/
html/vcrefCompilerOptionsListedAlphabetically.asp


PentiumPro.PII, and PII! are lumped together as /G6 (GCC lumps them
together too, but adds other MMX/SSE  arch options to qualify)

Athlon and P4 as /G7 (GCC handles these as distinct processors)

Danny
>
> [snip]
>
> --
> Oscar
>
>
>
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