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From: Steve L. <slo...@us...> - 2001-08-30 21:55:31
|
Update of /cvsroot/linux-mips/linux/arch/mips/au1000/pb1000
In directory usw-pr-cvs1:/tmp/cvs-serv27167
Modified Files:
setup.c
Log Message:
Moved sed1356 display-type selection from setup.c to fb driver.
Index: setup.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/au1000/pb1000/setup.c,v
retrieving revision 1.6
retrieving revision 1.7
diff -C2 -d -r1.6 -r1.7
*** setup.c 2001/08/28 07:23:54 1.6
--- setup.c 2001/08/30 21:55:28 1.7
***************
*** 130,138 ****
#endif
- #ifdef CONFIG_USB_OHCI
-
outl(usb_clocks, CLOCK_SOURCE_CNTRL);
udelay(1000);
// enable host controller and wait for reset done
outl(0x08, USB_HOST_CONFIG);
--- 130,137 ----
#endif
outl(usb_clocks, CLOCK_SOURCE_CNTRL);
udelay(1000);
+ #ifdef CONFIG_USB_OHCI
// enable host controller and wait for reset done
outl(0x08, USB_HOST_CONFIG);
***************
*** 156,160 ****
outl(0x2800, TSTATE_STATE_SET);
outl(0x0030, OUTPUT_STATE_CLEAR);
! #endif
/* make gpio 15 an input (interrupt line) */
--- 155,159 ----
outl(0x2800, TSTATE_STATE_SET);
outl(0x0030, OUTPUT_STATE_CLEAR);
! #endif // defined (CONFIG_USB_OHCI) || defined (CONFIG_AU1000_USB_DEVICE)
/* make gpio 15 an input (interrupt line) */
***************
*** 167,183 ****
#ifdef CONFIG_FB_E1356
- if ((argptr = strstr(argptr, "video=")) == NULL) {
- argptr = prom_getcmdline();
- #ifdef CONFIG_PB1000_CRT
- strcat(argptr, " video=e1356fb:system:pb1000-crt,font:SUN8x16");
- #elif defined (CONFIG_PB1000_NTSC)
- strcat(argptr, " video=e1356fb:system:pb1000-ntsc,font:SUN8x16");
- #elif defined (CONFIG_PB1000_TFT)
- strcat(argptr, " video=e1356fb:system:pb1000-tft,font:SUN8x16");
- #else
- strcat(argptr, " video=e1356fb:system:pb1000-crt,font:SUN8x16");
- #endif
- }
-
static_cfg0 = inl(STATIC_CONFIG_0) & (u32)(~0x1c00);
outl(static_cfg0, STATIC_CONFIG_0);
--- 166,169 ----
***************
*** 191,195 ****
// Set 32-bit base address decoding for RCE2*
outl(0x10003ff0, STATIC_ADDRESS_2);
! #endif
#ifdef CONFIG_PCI
--- 177,187 ----
// Set 32-bit base address decoding for RCE2*
outl(0x10003ff0, STATIC_ADDRESS_2);
!
! if ((argptr = strstr(argptr, "video=")) == NULL) {
! argptr = prom_getcmdline();
! strcat(argptr, " video=e1356fb:system:pb1000");
! }
! #endif // CONFIG_FB_E1356
!
#ifdef CONFIG_PCI
|
|
From: Steve L. <slo...@us...> - 2001-08-30 21:52:42
|
Update of /cvsroot/linux-mips/linux/arch/mips/au1000/common
In directory usw-pr-cvs1:/tmp/cvs-serv26386
Modified Files:
clocks.c time.c
Log Message:
Added functions to calculate and return the Au1000 LCD clock
frequency based on current CPU frequency.
Index: clocks.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/au1000/common/clocks.c,v
retrieving revision 1.1
retrieving revision 1.2
diff -C2 -d -r1.1 -r1.2
*** clocks.c 2001/08/28 07:23:54 1.1
--- clocks.c 2001/08/30 21:52:39 1.2
***************
*** 28,32 ****
*/
! static unsigned int au1000_clock;
static unsigned long uart_baud_base;
--- 28,35 ----
*/
! #include <asm/au1000.h>
!
! static unsigned int au1000_clock; // Hz
! static unsigned int lcd_clock; // KHz
static unsigned long uart_baud_base;
***************
*** 59,61 ****
--- 62,100 ----
{
uart_baud_base = new_baud_base;
+ }
+
+ /*
+ * Calculate the Au1000's LCD clock based on the current
+ * cpu clock and the system bus clock, and try to keep it
+ * below 40 MHz (the Pb1000 board can lock-up if the LCD
+ * clock is over 40 MHz).
+ */
+ void set_au1000_lcd_clock(void)
+ {
+ unsigned int static_cfg0;
+ unsigned int sys_busclk =
+ (get_au1000_speed()/1000) /
+ ((int)(inl(PM_POWERUP_CONTROL)&0x03) + 2);
+
+ static_cfg0 = inl(STATIC_CONFIG_0);
+ if (sys_busclk/4 > 40000) {
+ static_cfg0 |= (1<<11);
+ outl(static_cfg0, STATIC_CONFIG_0);
+ lcd_clock = sys_busclk / 5;
+ if (lcd_clock > 40000)
+ printk(__FUNCTION__
+ ": warning: LCD clock too high (%d KHz)\n",
+ lcd_clock);
+ } else {
+ static_cfg0 &= ~(1<<11);
+ outl(static_cfg0, STATIC_CONFIG_0);
+ lcd_clock = sys_busclk / 4;
+ }
+ // some time to allow LCD clock to settle
+ udelay(100);
+ }
+
+ unsigned int get_au1000_lcd_clock(void)
+ {
+ return lcd_clock;
}
Index: time.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/au1000/common/time.c,v
retrieving revision 1.5
retrieving revision 1.6
diff -C2 -d -r1.5 -r1.6
*** time.c 2001/08/28 07:23:54 1.5
--- time.c 2001/08/30 21:52:39 1.6
***************
*** 45,48 ****
--- 45,49 ----
extern void set_au1000_uart_baud_base(unsigned long new_baud_base);
extern void set_au1000_speed(unsigned int new_freq);
+ extern void set_au1000_lcd_clock(void);
extern volatile unsigned long wall_jiffies;
***************
*** 212,215 ****
--- 213,219 ----
(est_freq%1000000)*100/1000000);
set_au1000_speed(est_freq);
+ #ifdef CONFIG_FB_E1356
+ set_au1000_lcd_clock(); // program the LCD clock
+ #endif
r4k_cur = (read_32bit_cp0_register(CP0_COUNT) + r4k_offset);
|
|
From: Steve L. <slo...@us...> - 2001-08-30 21:50:52
|
Update of /cvsroot/linux-mips/linux/arch/mips/au1000/common
In directory usw-pr-cvs1:/tmp/cvs-serv25854
Modified Files:
dma.c usbdev.c
Log Message:
Indented to Linux kernel style.
Index: dma.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/au1000/common/dma.c,v
retrieving revision 1.2
retrieving revision 1.3
diff -C2 -d -r1.2 -r1.3
*** dma.c 2001/08/23 17:10:44 1.2
--- dma.c 2001/08/30 21:50:49 1.3
***************
*** 62,96 ****
struct dma_chan au1000_dma_table[NUM_AU1000_DMA_CHANNELS] = {
! {dev_id: -1,},
! {dev_id: -1,},
! {dev_id: -1,},
! {dev_id: -1,},
! {dev_id: -1,},
! {dev_id: -1,},
! {dev_id: -1,},
! {dev_id: -1,}
};
// Device FIFO addresses and default DMA modes
static const struct {
! unsigned int fifo_addr;
! unsigned int dma_mode;
} dma_dev_table[DMA_NUM_DEV] = {
! { UART0_ADDR + UART_TX, 0 },
! { UART0_ADDR + UART_RX, 0 },
! { 0, 0 },
! { 0, 0 },
! { AC97C_DATA, DMA_DW16 | DMA_NC },
! { AC97C_DATA, DMA_DR | DMA_DW16 | DMA_NC },
! { UART3_ADDR + UART_TX, DMA_DW8 | DMA_NC },
! { UART3_ADDR + UART_RX, DMA_DR | DMA_DW8 | DMA_NC },
! { USB_DEV_EP0_READ_FIFO, DMA_DR | DMA_DW8 | DMA_NC },
! { USB_DEV_EP0_WRITE_FIFO, DMA_DW8 | DMA_NC },
! { USB_DEV_EP2_WRITE_FIFO, DMA_DW8 | DMA_NC },
! { USB_DEV_EP3_WRITE_FIFO, DMA_DW8 | DMA_NC },
! { USB_DEV_EP4_READ_FIFO, DMA_DR | DMA_DW8 | DMA_NC },
! { USB_DEV_EP5_READ_FIFO, DMA_DR | DMA_DW8 | DMA_NC },
! { I2S_DATA, DMA_DW32 | DMA_NC },
! { I2S_DATA, DMA_DR | DMA_DW32 | DMA_NC }
};
--- 62,96 ----
struct dma_chan au1000_dma_table[NUM_AU1000_DMA_CHANNELS] = {
! {dev_id: -1,},
! {dev_id: -1,},
! {dev_id: -1,},
! {dev_id: -1,},
! {dev_id: -1,},
! {dev_id: -1,},
! {dev_id: -1,},
! {dev_id: -1,}
};
// Device FIFO addresses and default DMA modes
static const struct {
! unsigned int fifo_addr;
! unsigned int dma_mode;
} dma_dev_table[DMA_NUM_DEV] = {
! { UART0_ADDR + UART_TX, 0 },
! { UART0_ADDR + UART_RX, 0 },
! { 0, 0 },
! { 0, 0 },
! { AC97C_DATA, DMA_DW16 | DMA_NC },
! { AC97C_DATA, DMA_DR | DMA_DW16 | DMA_NC },
! { UART3_ADDR + UART_TX, DMA_DW8 | DMA_NC },
! { UART3_ADDR + UART_RX, DMA_DR | DMA_DW8 | DMA_NC },
! { USB_DEV_EP0_READ_FIFO, DMA_DR | DMA_DW8 | DMA_NC },
! { USB_DEV_EP0_WRITE_FIFO, DMA_DW8 | DMA_NC },
! { USB_DEV_EP2_WRITE_FIFO, DMA_DW8 | DMA_NC },
! { USB_DEV_EP3_WRITE_FIFO, DMA_DW8 | DMA_NC },
! { USB_DEV_EP4_READ_FIFO, DMA_DR | DMA_DW8 | DMA_NC },
! { USB_DEV_EP5_READ_FIFO, DMA_DR | DMA_DW8 | DMA_NC },
! { I2S_DATA, DMA_DW32 | DMA_NC },
! { I2S_DATA, DMA_DR | DMA_DW32 | DMA_NC }
};
***************
*** 99,121 ****
int length, int *eof, void *data)
{
! int i, len=0;
! struct dma_chan * chan;
!
! for (i = 0 ; i < NUM_AU1000_DMA_CHANNELS ; i++) {
! if ((chan = get_dma_chan(i)) != NULL) {
! len += sprintf(buf+len, "%2d: %s\n", i, chan->dev_str);
}
! }
!
! if (fpos >= len) {
! *start = buf;
! *eof = 1;
! return 0;
! }
! *start = buf + fpos;
! if ((len -= fpos) > length)
! return length;
! *eof = 1;
! return len;
}
--- 99,122 ----
int length, int *eof, void *data)
{
! int i, len=0;
! struct dma_chan * chan;
!
! for (i = 0 ; i < NUM_AU1000_DMA_CHANNELS ; i++) {
! if ((chan = get_dma_chan(i)) != NULL) {
! len += sprintf(buf+len, "%2d: %s\n",
! i, chan->dev_str);
! }
}
!
! if (fpos >= len) {
! *start = buf;
! *eof = 1;
! return 0;
! }
! *start = buf + fpos;
! if ((len -= fpos) > length)
! return length;
! *eof = 1;
! return len;
}
***************
*** 123,139 ****
void dump_au1000_dma_channel(unsigned int dmanr)
{
! struct dma_chan * chan;
! if (dmanr > NUM_AU1000_DMA_CHANNELS)
! return;
! chan = &au1000_dma_table[dmanr];
! printk(KERN_INFO "Au1000 DMA%d Register Dump:\n", dmanr);
! printk(KERN_INFO " mode = 0x%08x\n", inl(chan->io+DMA_MODE_SET));
! printk(KERN_INFO " addr = 0x%08x\n", inl(chan->io+DMA_PERIPHERAL_ADDR));
! printk(KERN_INFO " start0 = 0x%08x\n", inl(chan->io+DMA_BUFFER0_START));
! printk(KERN_INFO " start1 = 0x%08x\n", inl(chan->io+DMA_BUFFER1_START));
! printk(KERN_INFO " count0 = 0x%08x\n", inl(chan->io+DMA_BUFFER0_COUNT));
! printk(KERN_INFO " count1 = 0x%08x\n", inl(chan->io+DMA_BUFFER1_COUNT));
}
--- 124,146 ----
void dump_au1000_dma_channel(unsigned int dmanr)
{
! struct dma_chan * chan;
! if (dmanr > NUM_AU1000_DMA_CHANNELS)
! return;
! chan = &au1000_dma_table[dmanr];
! printk(KERN_INFO "Au1000 DMA%d Register Dump:\n", dmanr);
! printk(KERN_INFO " mode = 0x%08x\n",
! inl(chan->io+DMA_MODE_SET));
! printk(KERN_INFO " addr = 0x%08x\n",
! inl(chan->io+DMA_PERIPHERAL_ADDR));
! printk(KERN_INFO " start0 = 0x%08x\n",
! inl(chan->io+DMA_BUFFER0_START));
! printk(KERN_INFO " start1 = 0x%08x\n",
! inl(chan->io+DMA_BUFFER1_START));
! printk(KERN_INFO " count0 = 0x%08x\n",
! inl(chan->io+DMA_BUFFER0_COUNT));
! printk(KERN_INFO " count1 = 0x%08x\n",
! inl(chan->io+DMA_BUFFER1_COUNT));
}
***************
*** 145,172 ****
int request_au1000_dma(int dev_id, const char * dev_str)
{
! struct dma_chan * chan;
! int i;
! if (dev_id < 0 || dev_id >= DMA_NUM_DEV)
! return -EINVAL;
! for (i = 0 ; i < NUM_AU1000_DMA_CHANNELS ; i++) {
! if (au1000_dma_table[i].dev_id < 0)
! break;
! }
! if (i == NUM_AU1000_DMA_CHANNELS)
! return -ENODEV;
! chan = &au1000_dma_table[i];
! // fill it in
! chan->io = DMA_CHANNEL_BASE + i*DMA_CHANNEL_LEN;
! chan->irq = AU1000_DMA_INT_BASE + i;
! chan->dev_id = dev_id;
! chan->dev_str = dev_str;
! chan->fifo_addr = dma_dev_table[dev_id].fifo_addr;
! chan->mode = dma_dev_table[dev_id].dma_mode;
! return i;
}
--- 152,179 ----
int request_au1000_dma(int dev_id, const char * dev_str)
{
! struct dma_chan * chan;
! int i;
! if (dev_id < 0 || dev_id >= DMA_NUM_DEV)
! return -EINVAL;
! for (i = 0 ; i < NUM_AU1000_DMA_CHANNELS ; i++) {
! if (au1000_dma_table[i].dev_id < 0)
! break;
! }
! if (i == NUM_AU1000_DMA_CHANNELS)
! return -ENODEV;
! chan = &au1000_dma_table[i];
! // fill it in
! chan->io = DMA_CHANNEL_BASE + i*DMA_CHANNEL_LEN;
! chan->irq = AU1000_DMA_INT_BASE + i;
! chan->dev_id = dev_id;
! chan->dev_str = dev_str;
! chan->fifo_addr = dma_dev_table[dev_id].fifo_addr;
! chan->mode = dma_dev_table[dev_id].dma_mode;
! return i;
}
***************
*** 174,185 ****
void free_au1000_dma(unsigned int dmanr)
{
! struct dma_chan * chan = get_dma_chan(dmanr);
! if (!chan) {
! printk("Trying to free DMA%d\n", dmanr);
! return;
! }
! disable_dma(dmanr);
! chan->dev_id = -1;
} /* free_dma */
--- 181,192 ----
void free_au1000_dma(unsigned int dmanr)
{
! struct dma_chan * chan = get_dma_chan(dmanr);
! if (!chan) {
! printk("Trying to free DMA%d\n", dmanr);
! return;
! }
! disable_dma(dmanr);
! chan->dev_id = -1;
} /* free_dma */
Index: usbdev.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/au1000/common/usbdev.c,v
retrieving revision 1.2
retrieving revision 1.3
diff -C2 -d -r1.2 -r1.3
*** usbdev.c 2001/08/23 17:10:44 1.2
--- usbdev.c 2001/08/30 21:50:49 1.3
***************
*** 83,91 ****
typedef enum {
! ATTACHED = 0,
! POWERED,
! DEFAULT,
! ADDRESS,
! CONFIGURED
} dev_state_t;
--- 83,91 ----
[...3288 lines suppressed...]
! struct usb_serial_port * port = &usbserial.port[i];
! endpoint_flush(&port->ep_bulkin);
! endpoint_flush(&port->ep_bulkout);
! // start packet reception on bulk OUT endpoint
! kickstart_receive_packet(&port->ep_bulkout);
! }
! /*
! * Enable Receive FIFO Complete interrupts only. Transmit
! * complete is being handled by the DMA done interrupts.
! */
! outl_sync(0x31, USB_DEV_INT_ENABLE);
! return 0;
err_out:
! usbdev_serial_exit();
! return -1;
}
|
|
From: Steve L. <slo...@us...> - 2001-08-30 21:41:54
|
Update of /cvsroot/linux-mips/linux/include/linux
In directory usw-pr-cvs1:/tmp/cvs-serv22581
Added Files:
e1356fb.h
Log Message:
Initial version.
--- NEW FILE: e1356fb.h ---
/*
* e1356fb.h -- Epson SED1356 Framebuffer Driver IOCTL Interface
*
* Copyright 2001 MontaVista Software Inc.
* Author: MontaVista Software, Inc.
* st...@mv... or so...@mv...
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
/*
* IOCTLs to SED1356 fb driver. 0x45 is 'E' for Epson.
*/
#define FBIO_SED1356_BITBLT 0x4500
typedef struct {
int operation;
int rop;
int src_y;
int src_x;
int src_width;
int src_height;
int dst_y;
int dst_x;
int dst_width;
int dst_height;
int pattern_x;
int pattern_y;
int attribute;
unsigned int bg_color;
unsigned int fg_color;
unsigned short* src;
int srcsize;
int srcstride;
} blt_info_t;
enum blt_attribute_t {
BLT_ATTR_TRANSPARENT = 1
};
enum blt_operation_t {
BLT_WRITE_ROP = 0,
BLT_READ,
BLT_MOVE_POS_ROP,
BLT_MOVE_NEG_ROP,
BLT_WRITE_TRANSP,
BLT_MOVE_POS_TRANSP,
BLT_PAT_FILL_ROP,
BLT_PAT_FILL_TRANSP,
BLT_COLOR_EXP,
BLT_COLOR_EXP_TRANSP,
BLT_MOVE_COLOR_EXP,
BLT_MOVE_COLOR_EXP_TRANSP,
BLT_SOLID_FILL
};
|
|
From: Steve L. <slo...@us...> - 2001-08-30 21:41:08
|
Update of /cvsroot/linux-mips/linux/drivers/video
In directory usw-pr-cvs1:/tmp/cvs-serv21704
Modified Files:
epson1356fb.c epson1356fb.h fbmem.c
Log Message:
Some changes to SED1356 driver:
- indent to Linux kernel style
- intentional 32-bit VA unaligning when mmap'ing.
Index: epson1356fb.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/drivers/video/epson1356fb.c,v
retrieving revision 1.3
retrieving revision 1.4
diff -C2 -d -r1.3 -r1.4
*** epson1356fb.c 2001/08/28 07:23:54 1.3
--- epson1356fb.c 2001/08/30 21:41:05 1.4
***************
*** 84,87 ****
--- 84,89 ----
* Frame buffer device API
*/
+ static int e1356fb_open(struct fb_info *fb, int user);
+ static int e1356fb_release(struct fb_info *fb, int user);
static int e1356fb_get_fix(struct fb_fix_screeninfo* fix,
int con,
***************
*** 186,199 ****
[...4906 lines suppressed...]
! info->reg.lcd_inkcurs : info->reg.crttv_inkcurs;
! fb_info.fb_size -= 1024;
! // program cursor base address
! writeb(0x00, &inkcurs->start_addr);
! printk("e1356fb: reserving 1024 bytes for the hwcursor at %p\n",
! fb_info.membase_virt + fb_info.fb_size);
}
--- 2820,2830 ----
e1356fb_hwcursor_init(struct fb_info_e1356* info)
{
! reg_inkcurs_t* inkcurs = (IS_PANEL(info->fix.disp_type)) ?
! info->reg.lcd_inkcurs : info->reg.crttv_inkcurs;
! fb_info.fb_size -= 1024;
! // program cursor base address
! writeb(0x00, &inkcurs->start_addr);
! printk("e1356fb: reserving 1024 bytes for the hwcursor at %p\n",
! fb_info.membase_virt + fb_info.fb_size);
}
Index: epson1356fb.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/drivers/video/epson1356fb.h,v
retrieving revision 1.2
retrieving revision 1.3
diff -C2 -d -r1.2 -r1.3
*** epson1356fb.h 2001/08/17 22:53:26 1.2
--- epson1356fb.h 2001/08/30 21:41:05 1.3
***************
*** 56,61 ****
#define REG_BASE_BASIC 0x00
typedef struct {
! u8 rev_code; // 00
! u8 misc; // 01
} reg_basic_t;
--- 56,61 ----
#define REG_BASE_BASIC 0x00
typedef struct {
! u8 rev_code; // 00
[...997 lines suppressed...]
! 40000, 40000, 14318, 14318,
! DISP_TYPE_TFT,
! 0, 0,
! 0, 16,
! 0, 0,
#ifdef CONFIG_MTRR
! 0,
#endif
! 0,
! {0},
! "640x480@85"
! },
! { // par
! 0, 0, 1024, 768, 16, 2,
! // timings will be set by modedb
! {0}, 0, 0, 0, 0, 0, 0, 0, 0,
! 16
! }
}
};
Index: fbmem.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/drivers/video/fbmem.c,v
retrieving revision 1.3
retrieving revision 1.4
diff -C2 -d -r1.3 -r1.4
*** fbmem.c 2001/08/25 02:19:28 1.3
--- fbmem.c 2001/08/30 21:41:05 1.4
***************
*** 130,133 ****
--- 130,135 ----
extern int e1355fb_init(void);
extern int e1355fb_setup(char*);
+ extern int e1356fb_init(void);
+ extern int e1356fb_setup(char*);
extern int pvr2fb_init(void);
extern int pvr2fb_setup(char*);
***************
*** 283,286 ****
--- 285,291 ----
#ifdef CONFIG_FB_E1355
{ "e1355fb", e1355fb_init, e1355fb_setup },
+ #endif
+ #ifdef CONFIG_FB_E1356
+ { "e1356fb", e1356fb_init, e1356fb_setup },
#endif
#ifdef CONFIG_FB_PVR2
|
|
From: Pete P. <pp...@us...> - 2001-08-30 18:13:33
|
Update of /cvsroot/linux-mips/linux/drivers/net
In directory usw-pr-cvs1:/tmp/cvs-serv28294/drivers/net
Modified Files:
au1000_eth.c
Log Message:
Converted eth driver to use module_init interface instead
of the old Space.c probing.
Index: au1000_eth.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/drivers/net/au1000_eth.c,v
retrieving revision 1.4
retrieving revision 1.5
diff -C2 -d -r1.4 -r1.5
*** au1000_eth.c 2001/08/28 07:23:54 1.4
--- au1000_eth.c 2001/08/30 18:13:31 1.5
***************
*** 91,96 ****
extern char * __init prom_getcmdline(void);
- static int next_dev;
-
/*
* Theory of operation
--- 91,94 ----
***************
*** 122,126 ****
static char version[] __devinitdata =
! "au1000eth.c:0.1 pp...@mv...\n";
/* These addresses are only used if yamon doesn't tell us what
--- 120,124 ----
static char version[] __devinitdata =
! "au1000eth.c:0.2 pp...@mv...\n";
/* These addresses are only used if yamon doesn't tell us what
***************
*** 519,551 ****
}
! /*
! * Probe for a AU1000 ethernet controller.
! */
! int __init au1000_probe(struct net_device *dev)
{
! int base_addr = au1000_iflist[next_dev].port;
! int irq = au1000_iflist[next_dev].irq;
!
! #ifndef CONFIG_MIPS_AU1000_ENET
! return -ENODEV;
! #endif
!
! if (au1000_debug > 4)
! printk(KERN_INFO "%s: au1000_probe base_addr %x\n",
! dev->name, base_addr);
! if (next_dev >= NUM_INTERFACES) {
! return -ENODEV;
! }
! if (au1000_probe1(dev, base_addr, irq, next_dev) == 0) {
! next_dev++;
! return 0;
}
! next_dev++;
! return -ENODEV;
}
-
-
static int __init
au1000_probe1(struct net_device *dev, long ioaddr, int irq, int port_num)
--- 517,535 ----
}
! static int __init au1000_init_module(void)
{
! int i;
! int base_addr, irq;
! for (i=0; i<NUM_INTERFACES; i++) {
! base_addr = au1000_iflist[i].port;
! irq = au1000_iflist[i].irq;
! if (au1000_probe1(NULL, base_addr, irq, i) != 0) {
! return -ENODEV;
! }
}
! return 0;
}
static int __init
au1000_probe1(struct net_device *dev, long ioaddr, int irq, int port_num)
***************
*** 878,881 ****
--- 862,869 ----
}
+ static void __exit au1000_cleanup_module(void)
+ {
+ }
+
static inline void update_tx_stats(struct net_device *dev, u32 status, u32 pkt_len)
***************
*** 1291,1292 ****
--- 1279,1283 ----
return 0;
}
+
+ module_init(au1000_init_module);
+ module_exit(au1000_cleanup_module);
|
|
From: Pete P. <pp...@us...> - 2001-08-30 17:52:58
|
Update of /cvsroot/linux-mips/linux/arch/mips/au1000/common
In directory usw-pr-cvs1:/tmp/cvs-serv22950/arch/mips/au1000/common
Modified Files:
irq.c
Log Message:
Use au1000 vec_0 that's now in head.S.
Index: irq.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/au1000/common/irq.c,v
retrieving revision 1.5
retrieving revision 1.6
diff -C2 -d -r1.5 -r1.6
*** irq.c 2001/08/28 07:23:54 1.5
--- irq.c 2001/08/30 17:52:50 1.6
***************
*** 384,387 ****
--- 384,388 ----
int i;
unsigned long cp0_status;
+ extern char except_vec0_au1000;
cp0_status = read_32bit_cp0_register(CP0_STATUS);
***************
*** 390,393 ****
--- 391,398 ----
init_generic_irq();
+
+ /* override the generic vec0 handler */
+ memcpy((void *)KSEG0, &except_vec0_au1000, 0x80);
+ flush_icache_range(KSEG0, KSEG0 + 0x200);
for (i = 0; i <= NR_IRQS; i++) {
|
|
From: Steve L. <slo...@us...> - 2001-08-29 22:31:01
|
Update of /cvsroot/linux-mips/linux/include/linux In directory usw-pr-cvs1:/tmp/cvs-serv26070 Added Files: ac97_codec.h Log Message: Added register bit defines for AC97_EXTENDED_ID and AC97_EXTENDED_STATUS registers. Also fixed a register name error (AC97_PCM_LR_ADC_RATE). |
|
From: Pete P. <pp...@us...> - 2001-08-29 00:12:44
|
Update of /cvsroot/linux-mips/linux/arch/mips/au1000/pb1000
In directory usw-pr-cvs1:/tmp/cvs-serv6289/arch/mips/au1000/pb1000
Modified Files:
pci_fixup.c
Log Message:
Added a pci fixup function stub.
Index: pci_fixup.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/au1000/pb1000/pci_fixup.c,v
retrieving revision 1.2
retrieving revision 1.3
diff -C2 -d -r1.2 -r1.3
*** pci_fixup.c 2001/08/17 22:53:26 1.2
--- pci_fixup.c 2001/08/29 00:12:29 1.3
***************
*** 84,86 ****
--- 84,90 ----
}
}
+ unsigned int pcibios_assign_all_busses(void)
+ {
+ return 0;
+ }
#endif
|
|
From: Pete P. <pp...@us...> - 2001-08-28 23:57:30
|
Update of /cvsroot/linux-mips/linux/arch/mips/kernel
In directory usw-pr-cvs1:/tmp/cvs-serv3276/arch/mips/kernel
Added Files:
reset.c
Log Message:
Imported new files from oss tree. These are needed because the
stock kernel versions are much too old.
--- NEW FILE: reset.c ---
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2001 by Ralf Baechle
* Copyright (C) 2001 MIPS Technologies, Inc.
*/
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/reboot.h>
#include <asm/reboot.h>
/*
* Urgs ... Too many MIPS machines to handle this in a generic way.
* So handle all using function pointers to machine specific
* functions.
*/
void (*_machine_restart)(char *command);
void (*_machine_halt)(void);
void (*_machine_power_off)(void);
void machine_restart(char *command)
{
_machine_restart(command);
}
void machine_halt(void)
{
_machine_halt();
}
void machine_power_off(void)
{
_machine_power_off();
}
|
|
From: Pete P. <pp...@us...> - 2001-08-28 23:57:30
|
Update of /cvsroot/linux-mips/linux/include/asm-mips In directory usw-pr-cvs1:/tmp/cvs-serv3276/include/asm-mips Added Files: reboot.h Log Message: Imported new files from oss tree. These are needed because the stock kernel versions are much too old. --- NEW FILE: reboot.h --- /* * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * * Copyright (C) 1997, 1999, 2001 by Ralf Baechle * Copyright (C) 2001 MIPS Technologies, Inc. */ #ifndef _ASM_REBOOT_H #define _ASM_REBOOT_H extern void (*_machine_restart)(char *command); extern void (*_machine_halt)(void); extern void (*_machine_power_off)(void); #endif /* _ASM_REBOOT_H */ |
|
From: Pete P. <pp...@us...> - 2001-08-28 23:12:19
|
Update of /cvsroot/linux-mips/linux/arch/mips
In directory usw-pr-cvs1:/tmp/cvs-serv28026/arch/mips
Modified Files:
config.in
Log Message:
* ev96100 new pci support
* fixed a compile problem
* it8172/ivr Makefile cleanup
* it8172 IDE driver bug fixes
Index: config.in
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/config.in,v
retrieving revision 1.18
retrieving revision 1.19
diff -C2 -d -r1.18 -r1.19
*** config.in 2001/08/28 07:23:53 1.18
--- config.in 2001/08/28 23:12:15 1.19
***************
*** 225,228 ****
--- 225,231 ----
if [ "$CONFIG_MIPS_IVR" = "y" ]; then
define_bool CONFIG_PCI y
+ define_bool CONFIG_PC_KEYB y
+ define_bool CONFIG_NEW_PCI y
+ define_bool CONFIG_PCI_AUTO y
fi
if [ "$CONFIG_MIPS_PB1000" = "y" ]; then
|
|
From: Pete P. <pp...@us...> - 2001-08-28 23:12:19
|
Update of /cvsroot/linux-mips/linux/drivers/ide
In directory usw-pr-cvs1:/tmp/cvs-serv28026/drivers/ide
Modified Files:
it8172.c
Log Message:
* ev96100 new pci support
* fixed a compile problem
* it8172/ivr Makefile cleanup
* it8172 IDE driver bug fixes
Index: it8172.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/drivers/ide/it8172.c,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -C2 -d -r1.1.1.1 -r1.2
*** it8172.c 2001/06/22 02:29:32 1.1.1.1
--- it8172.c 2001/08/28 23:12:15 1.2
***************
*** 51,55 ****
static byte it8172_dma_2_pio (byte xfer_rate);
static int it8172_tune_chipset (ide_drive_t *drive, byte speed);
! static int it8172_config_drive_for_dma (ide_drive_t *drive);
static int it8172_dmaproc(ide_dma_action_t func, ide_drive_t *drive);
#endif
--- 51,55 ----
static byte it8172_dma_2_pio (byte xfer_rate);
static int it8172_tune_chipset (ide_drive_t *drive, byte speed);
! static int it8172_config_chipset_for_dma (ide_drive_t *drive);
static int it8172_dmaproc(ide_dma_action_t func, ide_drive_t *drive);
#endif
***************
*** 61,73 ****
{
unsigned long flags;
! u16 master_data;
! u32 slave_data;
int is_slave = (&HWIF(drive)->drives[1] == drive);
- int master_port = 0x40;
- int slave_port = 0x44;
! pio = ide_get_best_pio_mode(drive, pio, 5, NULL);
! pci_read_config_word(HWIF(drive)->pci_dev, master_port, &master_data);
! pci_read_config_dword(HWIF(drive)->pci_dev, slave_port, &slave_data);
/*
--- 61,71 ----
{
unsigned long flags;
! u16 drive_enables;
! u32 drive_timing;
int is_slave = (&HWIF(drive)->drives[1] == drive);
! pio = ide_get_best_pio_mode(drive, pio, 4, NULL);
! pci_read_config_word(HWIF(drive)->pci_dev, 0x40, &drive_enables);
! pci_read_config_dword(HWIF(drive)->pci_dev, 0x44, &drive_timing);
/*
***************
*** 75,96 ****
* are being left at the default values of 8 PCI clocks (242 nsec
* for a 33 MHz clock). These can be safely shortened at higher
! * PIO modes.
*/
if (is_slave) {
! master_data |= 0x4000;
if (pio > 1)
! /* enable PPE and IE */
! master_data |= 0x0060;
} else {
! master_data &= 0xc060;
if (pio > 1)
! /* enable PPE and IE */
! master_data |= 0x0006;
}
save_flags(flags);
cli();
! pci_write_config_word(HWIF(drive)->pci_dev, master_port, master_data);
restore_flags(flags);
}
--- 73,102 ----
* are being left at the default values of 8 PCI clocks (242 nsec
* for a 33 MHz clock). These can be safely shortened at higher
! * PIO modes. The DIOR/DIOW pulse width and recovery times only
! * apply to PIO modes, not to the DMA modes.
*/
+ /*
+ * Enable port 0x44. The IT8172G spec is confused; it calls
+ * this register the "Slave IDE Timing Register", but in fact,
+ * it controls timing for both master and slave drives.
+ */
+ drive_enables |= 0x4000;
+
if (is_slave) {
! drive_enables &= 0xc006;
if (pio > 1)
! /* enable prefetch and IORDY sample-point */
! drive_enables |= 0x0060;
} else {
! drive_enables &= 0xc060;
if (pio > 1)
! /* enable prefetch and IORDY sample-point */
! drive_enables |= 0x0006;
}
save_flags(flags);
cli();
! pci_write_config_word(HWIF(drive)->pci_dev, 0x40, drive_enables);
restore_flags(flags);
}
***************
*** 161,164 ****
--- 167,171 ----
case XFER_MW_DMA_2:
case XFER_MW_DMA_1:
+ case XFER_MW_DMA_0:
case XFER_SW_DMA_2: break;
default: return -1;
***************
*** 183,187 ****
}
! static int it8172_config_drive_for_dma (ide_drive_t *drive)
{
struct hd_driveid *id = drive->id;
--- 190,194 ----
}
! static int it8172_config_chipset_for_dma (ide_drive_t *drive)
{
struct hd_driveid *id = drive->id;
***************
*** 202,209 ****
} else if (id->dma_mword & 0x0002) {
speed = XFER_MW_DMA_1;
} else if (id->dma_1word & 0x0004) {
speed = XFER_SW_DMA_2;
} else {
! speed = XFER_PIO_0 + ide_get_best_pio_mode(drive, 255, 5, NULL);
}
--- 209,218 ----
} else if (id->dma_mword & 0x0002) {
speed = XFER_MW_DMA_1;
+ } else if (id->dma_mword & 0x0001) {
+ speed = XFER_MW_DMA_0;
} else if (id->dma_1word & 0x0004) {
speed = XFER_SW_DMA_2;
} else {
! speed = XFER_PIO_0 + ide_get_best_pio_mode(drive, 255, 4, NULL);
}
***************
*** 221,225 ****
switch (func) {
case ide_dma_check:
! return ide_dmaproc((ide_dma_action_t)it8172_config_drive_for_dma(drive),
drive);
default :
--- 230,234 ----
switch (func) {
case ide_dma_check:
! return ide_dmaproc((ide_dma_action_t)it8172_config_chipset_for_dma(drive),
drive);
default :
|
|
From: Pete P. <pp...@us...> - 2001-08-28 23:12:19
|
Update of /cvsroot/linux-mips/linux/arch/mips/galileo-boards/generic In directory usw-pr-cvs1:/tmp/cvs-serv28026/arch/mips/galileo-boards/generic Modified Files: Makefile Log Message: * ev96100 new pci support * fixed a compile problem * it8172/ivr Makefile cleanup * it8172 IDE driver bug fixes Index: Makefile =================================================================== RCS file: /cvsroot/linux-mips/linux/arch/mips/galileo-boards/generic/Makefile,v retrieving revision 1.3 retrieving revision 1.4 diff -C2 -d -r1.3 -r1.4 *** Makefile 2001/07/09 19:28:47 1.3 --- Makefile 2001/08/28 23:12:15 1.4 *************** *** 35,39 **** O_TARGET:= galboards.o ! obj-y := reset.o cmdline.o include $(TOPDIR)/Rules.make --- 35,39 ---- O_TARGET:= galboards.o ! obj-y := reset.o include $(TOPDIR)/Rules.make |
|
From: Pete P. <pp...@us...> - 2001-08-28 23:12:18
|
Update of /cvsroot/linux-mips/linux/arch/mips/ite-boards/ivr In directory usw-pr-cvs1:/tmp/cvs-serv28026/arch/mips/ite-boards/ivr Modified Files: Makefile Log Message: * ev96100 new pci support * fixed a compile problem * it8172/ivr Makefile cleanup * it8172 IDE driver bug fixes Index: Makefile =================================================================== RCS file: /cvsroot/linux-mips/linux/arch/mips/ite-boards/ivr/Makefile,v retrieving revision 1.1.1.1 retrieving revision 1.2 diff -C2 -d -r1.1.1.1 -r1.2 *** Makefile 2001/06/22 02:29:31 1.1.1.1 --- Makefile 2001/08/28 23:12:15 1.2 *************** *** 23,28 **** obj-y := init.o ! obj-CONFIG_PCI += pci_fixup.o ! obj-CONFIG_BLK_DEV_INITRD += le_ramdisk.o include $(TOPDIR)/Rules.make --- 23,27 ---- obj-y := init.o ! obj-$(CONFIG_PCI) += pci_fixup.o include $(TOPDIR)/Rules.make |
|
From: Pete P. <pp...@us...> - 2001-08-28 23:12:18
|
Update of /cvsroot/linux-mips/linux/arch/mips/ite-boards/generic In directory usw-pr-cvs1:/tmp/cvs-serv28026/arch/mips/ite-boards/generic Modified Files: Makefile Log Message: * ev96100 new pci support * fixed a compile problem * it8172/ivr Makefile cleanup * it8172 IDE driver bug fixes Index: Makefile =================================================================== RCS file: /cvsroot/linux-mips/linux/arch/mips/ite-boards/generic/Makefile,v retrieving revision 1.1.1.1 retrieving revision 1.2 diff -C2 -d -r1.1.1.1 -r1.2 *** Makefile 2001/06/22 02:29:31 1.1.1.1 --- Makefile 2001/08/28 23:12:15 1.2 *************** *** 22,36 **** obj-y := it8172_rtc.o it8172_setup.o irq.o int-handler.o pmon_prom.o time.o lpc.o puts.o reset.o ! ifdef CONFIG_PCI ! obj-y += it8172_pci.o ! endif ! ! ifdef CONFIG_IT8172_CIR ! obj-y += it8172_cir.o ! endif ! ! ifdef CONFIG_REMOTE_DEBUG ! obj-y += dbg_io.o ! endif include $(TOPDIR)/Rules.make --- 22,28 ---- obj-y := it8172_rtc.o it8172_setup.o irq.o int-handler.o pmon_prom.o time.o lpc.o puts.o reset.o ! obj-$(CONFIG_PCI) += it8172_pci.o ! obj-$(CONFIG_IT8172_CIR) += it8172_cir.o ! obj-$(CONFIG_REMOTE_DEBUG) += dbg_io.o include $(TOPDIR)/Rules.make |
|
From: Pete P. <pp...@us...> - 2001-08-28 23:12:18
|
Update of /cvsroot/linux-mips/linux/arch/mips/galileo-boards/ev96100
In directory usw-pr-cvs1:/tmp/cvs-serv28026/arch/mips/galileo-boards/ev96100
Modified Files:
init.c
Log Message:
* ev96100 new pci support
* fixed a compile problem
* it8172/ivr Makefile cleanup
* it8172 IDE driver bug fixes
Index: init.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/galileo-boards/ev96100/init.c,v
retrieving revision 1.3
retrieving revision 1.4
diff -C2 -d -r1.3 -r1.4
*** init.c 2001/08/25 02:19:27 1.3
--- init.c 2001/08/28 23:12:15 1.4
***************
*** 53,58 ****
--- 53,87 ----
int prom_argc;
char **prom_argv, **prom_envp;
+ char arcs_cmdline[COMMAND_LINE_SIZE];
int init_debug = 0;
+
+ char * __init prom_getcmdline(void)
+ {
+ return &(arcs_cmdline[0]);
+ }
+
+ void prom_free_prom_memory (void)
+ {
+ }
+
+ void __init prom_init_cmdline(void)
+ {
+ char *cp;
+ int actr;
+
+ actr = 1; /* Always ignore argv[0] */
+
+ cp = &(arcs_cmdline[0]);
+ while(actr < prom_argc) {
+ strcpy(cp, prom_argv[actr]);
+ cp += strlen(prom_argv[actr]);
+ *cp++ = ' ';
+ actr++;
+ }
+ if (cp != &(arcs_cmdline[0])) /* get rid of trailing space */
+ --cp;
+ *cp = '\0';
+ }
char *prom_getenv(char *envname)
|
|
From: Pete P. <pp...@us...> - 2001-08-28 21:03:46
|
Update of /cvsroot/linux-mips/linux/arch/mips/kernel
In directory usw-pr-cvs1:/tmp/cvs-serv28632/arch/mips/kernel
Modified Files:
pci.c
Log Message:
Backed out one fixup function which is board dependent and
should be included in the board's pci_fixup.c file instead.
Index: pci.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/kernel/pci.c,v
retrieving revision 1.3
retrieving revision 1.4
diff -C2 -d -r1.3 -r1.4
*** pci.c 2001/08/28 07:23:54 1.3
--- pci.c 2001/08/28 21:03:44 1.4
***************
*** 173,179 ****
/* this should not be called */
}
-
- unsigned int pcibios_assign_all_busses(void)
- {
- return 1;
- }
--- 173,174 ----
|
|
From: Pete P. <pp...@us...> - 2001-08-28 07:23:58
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Update of /cvsroot/linux-mips/linux/include/asm-mips
In directory usw-pr-cvs1:/tmp/cvs-serv14591/include/asm-mips
Modified Files:
au1000.h
Log Message:
Added preliminary power management supuport:
* turn off the clocks to the uarts when not used
* turn off the clocks to the ethernets when not used
* adhoc /proc interface for putting the cpu to sleep and
dynamically scaling the cpu frequency.
* fixed a pci compile problem
Index: au1000.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/au1000.h,v
retrieving revision 1.4
retrieving revision 1.5
diff -C2 -d -r1.4 -r1.5
*** au1000.h 2001/08/25 02:19:28 1.4
--- au1000.h 2001/08/28 07:23:54 1.5
***************
*** 29,32 ****
--- 29,33 ----
*/
+
#ifndef _AU1000_H_
#define _AU1000_H_
***************
*** 68,254 ****
au_sync();
}
-
- /* SDRAM Controller */
- #define CS_MODE_0 0x14000000
- #define CS_MODE_1 0x14000004
- #define CS_MODE_2 0x14000008
-
- #define CS_CONFIG_0 0x1400000C
- #define CS_CONFIG_1 0x14000010
- #define CS_CONFIG_2 0x14000014
-
- #define REFRESH_CONFIG 0x14000018
- #define PRECHARGE_CMD 0x1400001C
- #define AUTO_REFRESH_CMD 0x14000020
-
- #define WRITE_EXTERN_0 0x14000024
- #define WRITE_EXTERN_1 0x14000028
- #define WRITE_EXTERN_2 0x1400002C
-
- #define SDRAM_SLEEP 0x14000030
- #define TOGGLE_CKE 0x14000034
-
- /* Static Bus Controller */
- #define STATIC_CONFIG_0 0x14001000
- #define STATIC_TIMING_0 0x14001004
- #define STATIC_ADDRESS_0 0x14001008
! #define STATIC_CONFIG_1 0x14001010
! #define STATIC_TIMING_1 0x14001014
! #define STATIC_ADDRESS_1 0x14001018
! #define STATIC_CONFIG_2 0x14001020
! #define STATIC_TIMING_2 0x14001024
! #define STATIC_ADDRESS_2 0x14001028
! #define STATIC_CONFIG_3 0x14001030
! #define STATIC_TIMING_3 0x14001034
! #define STATIC_ADDRESS_3 0x14001038
! /* DMA Controller 0 */
! #define DMA0_MODE_SET 0x14002000
! #define DMA0_MODE_CLEAR 0x14002004
! #define DMA0_PERIPHERAL_ADDR 0x14002008
! #define DMA0_BUFFER0_START 0x1400200C
! #define DMA0_BUFFER0_COUNT 0x14002010
! #define DMA0_BUFFER1_START 0x14002014
! #define DMA0_BUFFER1_COUNT 0x14002018
! /* DMA Controller 1 */
! #define DMA1_MODE_SET 0x14002100
! #define DMA1_MODE_CLEAR 0x14002104
! #define DMA1_PERIPHERAL_ADDR 0x14002108
! #define DMA1_BUFFER0_START 0x1400210C
! #define DMA1_BUFFER0_COUNT 0x14002110
! #define DMA1_BUFFER1_START 0x14002114
! #define DMA1_BUFFER1_COUNT 0x14002118
! /* DMA Controller 2 */
! #define DMA2_MODE_SET 0x14002200
! #define DMA2_MODE_CLEAR 0x14002204
! #define DMA2_PERIPHERAL_ADDR 0x14002208
! #define DMA2_BUFFER0_START 0x1400220C
! #define DMA2_BUFFER0_COUNT 0x14002210
! #define DMA2_BUFFER1_START 0x14002214
! #define DMA2_BUFFER1_COUNT 0x14002218
! /* DMA Controller 3 */
! #define DMA3_MODE_SET 0x14002300
! #define DMA3_MODE_CLEAR 0x14002304
! #define DMA3_PERIPHERAL_ADDR 0x14002308
! #define DMA3_BUFFER0_START 0x1400230C
! #define DMA3_BUFFER0_COUNT 0x14002310
! #define DMA3_BUFFER1_START 0x14002314
! #define DMA3_BUFFER1_COUNT 0x14002318
! /* DMA Controller 4 */
! #define DMA4_MODE_SET 0x14002400
! #define DMA4_MODE_CLEAR 0x14002404
! #define DMA4_PERIPHERAL_ADDR 0x14002408
! #define DMA4_BUFFER0_START 0x1400240C
! #define DMA4_BUFFER0_COUNT 0x14002410
! #define DMA4_BUFFER1_START 0x14002414
! #define DMA4_BUFFER1_COUNT 0x14002418
! /* DMA Controller 5 */
! #define DMA5_MODE_SET 0x14002500
! #define DMA5_MODE_CLEAR 0x14002504
! #define DMA5_PERIPHERAL_ADDR 0x14002508
! #define DMA5_BUFFER0_START 0x1400250C
! #define DMA5_BUFFER0_COUNT 0x14002510
! #define DMA5_BUFFER1_START 0x14002514
! #define DMA5_BUFFER1_COUNT 0x14002518
! /* DMA Controller 6 */
! #define DMA6_MODE_SET 0x14002600
! #define DMA6_MODE_CLEAR 0x14002604
! #define DMA6_PERIPHERAL_ADDR 0x14002608
! #define DMA6_BUFFER0_START 0x1400260C
! #define DMA6_BUFFER0_COUNT 0x14002610
! #define DMA6_BUFFER1_START 0x14002614
! #define DMA6_BUFFER1_COUNT 0x14002618
! /* DMA Controller 7 */
! #define DMA7_MODE_SET 0x14002700
! #define DMA7_MODE_CLEAR 0x14002704
! #define DMA7_PERIPHERAL_ADDR 0x14002708
! #define DMA7_BUFFER0_START 0x1400270C
! #define DMA7_BUFFER0_COUNT 0x14002710
! #define DMA7_BUFFER1_START 0x14002714
! #define DMA7_BUFFER1_COUNT 0x14002718
/* Interrupt Controller 0 */
! #define INTC0_CONFIG0_READ 0x10400040
! #define INTC0_CONFIG0_SET 0x10400040
! #define INTC0_CONFIG0_CLEAR 0x10400044
! #define INTC0_CONFIG1_READ 0x10400048
! #define INTC0_CONFIG1_SET 0x10400048
! #define INTC0_CONFIG1_CLEAR 0x1040004C
! #define INTC0_CONFIG2_READ 0x10400050
! #define INTC0_CONFIG2_SET 0x10400050
! #define INTC0_CONFIG2_CLEAR 0x10400054
! #define INTC0_REQ0_INT 0x10400054
! #define INTC0_SOURCE_READ 0x10400058
! #define INTC0_SOURCE_SET 0x10400058
! #define INTC0_SOURCE_CLEAR 0x1040005C
! #define INTC0_REQ1_INT 0x1040005C
! #define INTC0_ASSIGN_REQ_READ 0x10400060
! #define INTC0_ASSIGN_REQ_SET 0x10400060
! #define INTC0_ASSIGN_REQ_CLEAR 0x10400064
! #define INTC0_WAKEUP_READ 0x10400068
! #define INTC0_WAKEUP_SET 0x10400068
! #define INTC0_WAKEUP_CLEAR 0x1040006C
! #define INTC0_MASK_READ 0x10400070
! #define INTC0_MASK_SET 0x10400070
! #define INTC0_MASK_CLEAR 0x10400074
! #define INTC0_R_EDGE_DETECT 0x10400078
! #define INTC0_R_EDGE_DETECT_CLEAR 0x10400078
! #define INTC0_F_EDGE_DETECT_CLEAR 0x1040007C
! #define INTC0_TEST_BIT 0x10400080
/* Interrupt Controller 1 */
! #define INTC1_CONFIG0_READ 0x11800040
! #define INTC1_CONFIG0_SET 0x11800040
! #define INTC1_CONFIG0_CLEAR 0x11800044
! #define INTC1_CONFIG1_READ 0x11800048
! #define INTC1_CONFIG1_SET 0x11800048
! #define INTC1_CONFIG1_CLEAR 0x1180004C
! #define INTC1_CONFIG2_READ 0x11800050
! #define INTC1_CONFIG2_SET 0x11800050
! #define INTC1_CONFIG2_CLEAR 0x11800054
! #define INTC1_REQ0_INT 0x11800054
! #define INTC1_SOURCE_READ 0x11800058
! #define INTC1_SOURCE_SET 0x11800058
! #define INTC1_SOURCE_CLEAR 0x1180005C
! #define INTC1_REQ1_INT 0x1180005C
! #define INTC1_ASSIGN_REQ_READ 0x11800060
! #define INTC1_ASSIGN_REQ_SET 0x11800060
! #define INTC1_ASSIGN_REQ_CLEAR 0x11800064
! #define INTC1_WAKEUP_READ 0x11800068
! #define INTC1_WAKEUP_SET 0x11800068
! #define INTC1_WAKEUP_CLEAR 0x1180006C
! #define INTC1_MASK_READ 0x11800070
! #define INTC1_MASK_SET 0x11800070
! #define INTC1_MASK_CLEAR 0x11800074
! #define INTC1_R_EDGE_DETECT 0x11800078
! #define INTC1_R_EDGE_DETECT_CLEAR 0x11800078
! #define INTC1_F_EDGE_DETECT_CLEAR 0x1180007C
! #define INTC1_TEST_BIT 0x11800080
/* Interrupt Configuration Modes */
--- 69,193 ----
au_sync();
}
! extern void set_au1000_speed(unsigned int new_freq);
! extern unsigned int get_au1000_speed(void);
! #ifdef CONFIG_PM
! /* no CP0 timer irq */
! #define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4)
! #else
! #define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
! #endif
! /* SDRAM Controller */
! #define CS_MODE_0 0xB4000000
! #define CS_MODE_1 0xB4000004
! #define CS_MODE_2 0xB4000008
! #define CS_CONFIG_0 0xB400000C
! #define CS_CONFIG_1 0xB4000010
! #define CS_CONFIG_2 0xB4000014
! #define REFRESH_CONFIG 0xB4000018
! #define PRECHARGE_CMD 0xB400001C
! #define AUTO_REFRESH_CMD 0xB4000020
! #define WRITE_EXTERN_0 0xB4000024
! #define WRITE_EXTERN_1 0xB4000028
! #define WRITE_EXTERN_2 0xB400002C
! #define SDRAM_SLEEP 0xB4000030
! #define TOGGLE_CKE 0xB4000034
! /* Static Bus Controller */
! #define STATIC_CONFIG_0 0xB4001000
! #define STATIC_TIMING_0 0xB4001004
! #define STATIC_ADDRESS_0 0xB4001008
! #define STATIC_CONFIG_1 0xB4001010
! #define STATIC_TIMING_1 0xB4001014
! #define STATIC_ADDRESS_1 0xB4001018
! #define STATIC_CONFIG_2 0xB4001020
! #define STATIC_TIMING_2 0xB4001024
! #define STATIC_ADDRESS_2 0xB4001028
! #define STATIC_CONFIG_3 0xB4001030
! #define STATIC_TIMING_3 0xB4001034
! #define STATIC_ADDRESS_3 0xB4001038
/* Interrupt Controller 0 */
! #define INTC0_CONFIG0_READ 0xB0400040
! #define INTC0_CONFIG0_SET 0xB0400040
! #define INTC0_CONFIG0_CLEAR 0xB0400044
! #define INTC0_CONFIG1_READ 0xB0400048
! #define INTC0_CONFIG1_SET 0xB0400048
! #define INTC0_CONFIG1_CLEAR 0xB040004C
! #define INTC0_CONFIG2_READ 0xB0400050
! #define INTC0_CONFIG2_SET 0xB0400050
! #define INTC0_CONFIG2_CLEAR 0xB0400054
! #define INTC0_REQ0_INT 0xB0400054
! #define INTC0_SOURCE_READ 0xB0400058
! #define INTC0_SOURCE_SET 0xB0400058
! #define INTC0_SOURCE_CLEAR 0xB040005C
! #define INTC0_REQ1_INT 0xB040005C
! #define INTC0_ASSIGN_REQ_READ 0xB0400060
! #define INTC0_ASSIGN_REQ_SET 0xB0400060
! #define INTC0_ASSIGN_REQ_CLEAR 0xB0400064
! #define INTC0_WAKEUP_READ 0xB0400068
! #define INTC0_WAKEUP_SET 0xB0400068
! #define INTC0_WAKEUP_CLEAR 0xB040006C
! #define INTC0_MASK_READ 0xB0400070
! #define INTC0_MASK_SET 0xB0400070
! #define INTC0_MASK_CLEAR 0xB0400074
! #define INTC0_R_EDGE_DETECT 0xB0400078
! #define INTC0_R_EDGE_DETECT_CLEAR 0xB0400078
! #define INTC0_F_EDGE_DETECT_CLEAR 0xB040007C
! #define INTC0_TEST_BIT 0xB0400080
/* Interrupt Controller 1 */
! #define INTC1_CONFIG0_READ 0xB1800040
! #define INTC1_CONFIG0_SET 0xB1800040
! #define INTC1_CONFIG0_CLEAR 0xB1800044
! #define INTC1_CONFIG1_READ 0xB1800048
! #define INTC1_CONFIG1_SET 0xB1800048
! #define INTC1_CONFIG1_CLEAR 0xB180004C
! #define INTC1_CONFIG2_READ 0xB1800050
! #define INTC1_CONFIG2_SET 0xB1800050
! #define INTC1_CONFIG2_CLEAR 0xB1800054
! #define INTC1_REQ0_INT 0xB1800054
! #define INTC1_SOURCE_READ 0xB1800058
! #define INTC1_SOURCE_SET 0xB1800058
! #define INTC1_SOURCE_CLEAR 0xB180005C
! #define INTC1_REQ1_INT 0xB180005C
! #define INTC1_ASSIGN_REQ_READ 0xB1800060
! #define INTC1_ASSIGN_REQ_SET 0xB1800060
! #define INTC1_ASSIGN_REQ_CLEAR 0xB1800064
! #define INTC1_WAKEUP_READ 0xB1800068
! #define INTC1_WAKEUP_SET 0xB1800068
! #define INTC1_WAKEUP_CLEAR 0xB180006C
! #define INTC1_MASK_READ 0xB1800070
! #define INTC1_MASK_SET 0xB1800070
! #define INTC1_MASK_CLEAR 0xB1800074
! #define INTC1_R_EDGE_DETECT 0xB1800078
! #define INTC1_R_EDGE_DETECT_CLEAR 0xB1800078
! #define INTC1_F_EDGE_DETECT_CLEAR 0xB180007C
! #define INTC1_TEST_BIT 0xB1800080
/* Interrupt Configuration Modes */
***************
*** 268,279 ****
#define AU1000_SSI0_INT 4
#define AU1000_SSI1_INT 5
! #define AU1000_DMA0_INT 6
! #define AU1000_DMA1_INT 7
! #define AU1000_DMA2_INT 8
! #define AU1000_DMA3_INT 9
! #define AU1000_DMA4_INT 10
! #define AU1000_DMA5_INT 11
! #define AU1000_DMA6_INT 12
! #define AU1000_DMA7_INT 13
#define AU1000_PC0_INT 14
#define AU1000_PC0_MATCH0_INT 15
--- 207,211 ----
#define AU1000_SSI0_INT 4
#define AU1000_SSI1_INT 5
! #define AU1000_DMA_INT_BASE 6
#define AU1000_PC0_INT 14
#define AU1000_PC0_MATCH0_INT 15
***************
*** 331,335 ****
/* Programmable Counters 0 and 1 */
! #define PC_BASE 0x11900000
#define PC_COUNTER_CNTRL (PC_BASE + 0x14)
#define PC_CNTRL_E1S (1<<23)
--- 263,267 ----
/* Programmable Counters 0 and 1 */
! #define PC_BASE 0xB1900000
#define PC_COUNTER_CNTRL (PC_BASE + 0x14)
#define PC_CNTRL_E1S (1<<23)
***************
*** 371,377 ****
/* I2S Controller */
! #define I2S_DATA 0x11000000
! #define I2S_CONFIG_STATUS 0x11000001
! #define I2S_CONTROL 0x11000002
/* USB Host Controller */
--- 303,309 ----
/* I2S Controller */
! #define I2S_DATA 0xB1000000
! #define I2S_CONFIG_STATUS 0xB1000001
! #define I2S_CONTROL 0xB1000002
/* USB Host Controller */
***************
*** 424,429 ****
/* Ethernet Controllers */
! #define AU1000_ETH0_BASE 0x10500000
! #define AU1000_ETH1_BASE 0x10510000
/* 4 byte offsets from AU1000_ETH_BASE */
--- 356,361 ----
/* Ethernet Controllers */
! #define AU1000_ETH0_BASE 0xB0500000
! #define AU1000_ETH1_BASE 0xB0510000
/* 4 byte offsets from AU1000_ETH_BASE */
***************
*** 470,478 ****
/* Ethernet Controller Enable */
! #define MAC0_ENABLE 0x10520000
! #define MAC1_ENABLE 0x10520004
#define MAC_EN_CLOCK_ENABLE (1<<0)
#define MAC_EN_RESET0 (1<<1)
! #define MAC_EN_TOSS (1<<2)
#define MAC_EN_CACHEABLE (1<<3)
#define MAC_EN_RESET1 (1<<4)
--- 402,410 ----
/* Ethernet Controller Enable */
! #define MAC0_ENABLE 0xB0520000
! #define MAC1_ENABLE 0xB0520004
#define MAC_EN_CLOCK_ENABLE (1<<0)
#define MAC_EN_RESET0 (1<<1)
! #define MAC_EN_TOSS (0<<2)
#define MAC_EN_CACHEABLE (1<<3)
#define MAC_EN_RESET1 (1<<4)
***************
*** 482,487 ****
/* Ethernet Controller DMA Channels */
! #define MAC0_TX_DMA_ADDR 0x14004000
! #define MAC1_TX_DMA_ADDR 0x14004200
/* offsets from MAC_TX_RING_ADDR address */
#define MAC_TX_BUFF0_STATUS 0x0
--- 414,419 ----
/* Ethernet Controller DMA Channels */
! #define MAC0_TX_DMA_ADDR 0xB4004000
! #define MAC1_TX_DMA_ADDR 0xB4004200
/* offsets from MAC_TX_RING_ADDR address */
#define MAC_TX_BUFF0_STATUS 0x0
***************
*** 513,518 ****
#define MAC_TX_BUFF3_LEN 0x38
! #define MAC0_RX_DMA_ADDR 0x14004100
! #define MAC1_RX_DMA_ADDR 0x14004300
/* offsets from MAC_RX_RING_ADDR */
#define MAC_RX_BUFF0_STATUS 0x0
--- 445,450 ----
#define MAC_TX_BUFF3_LEN 0x38
! #define MAC0_RX_DMA_ADDR 0xB4004100
! #define MAC1_RX_DMA_ADDR 0xB4004300
/* offsets from MAC_RX_RING_ADDR */
#define MAC_RX_BUFF0_STATUS 0x0
***************
*** 554,561 ****
/* UARTS 0-3 */
! #define UART0_ADDR 0x11100000
! #define UART1_ADDR 0x11200000
! #define UART2_ADDR 0x11300000
! #define UART3_ADDR 0x11400000
#define UART_RX 0 /* Receive buffer */
--- 486,494 ----
/* UARTS 0-3 */
! #define UART_BASE 0xB1100000
! #define UART0_ADDR 0xB1100000
! #define UART1_ADDR 0xB1200000
! #define UART2_ADDR 0xB1300000
! #define UART3_ADDR 0xB1400000
#define UART_RX 0 /* Receive buffer */
***************
*** 568,572 ****
#define UART_LSR 0x1C /* Line Status Register */
#define UART_MSR 0x20 /* Modem Status Register */
! #define UART_CLK 0x28 /* Baud Rat4e Clock Divider */
#define UART_MOD_CNTRL 0x100 /* Module Control */
--- 501,505 ----
#define UART_LSR 0x1C /* Line Status Register */
#define UART_MSR 0x20 /* Modem Status Register */
! #define UART_CLK 0x28 /* Baud Rate Clock Divider */
#define UART_MOD_CNTRL 0x100 /* Module Control */
***************
*** 652,716 ****
/* SSIO */
! #define SSI0_STATUS 0x11600000
! #define SSI0_INT 0x11600004
! #define SSI0_INT_ENABLE 0x11600008
! #define SSI0_CONFIG 0x11600020
! #define SSI0_ADATA 0x11600024
! #define SSI0_CLKDIV 0x11600028
! #define SSI0_CONTROL 0x11600100
/* SSI1 */
! #define SSI1_STATUS 0x11680000
! #define SSI1_INT 0x11680004
! #define SSI1_INT_ENABLE 0x11680008
! #define SSI1_CONFIG 0x11680020
! #define SSI1_ADATA 0x11680024
! #define SSI1_CLKDIV 0x11680028
! #define SSI1_CONTROL 0x11680100
/* IrDA Controller */
! #define IR_RING_PTR_STATUS 0x11500000
! #define IR_RING_BASE_ADDR_H 0x11500004
! #define IR_RING_BASE_ADDR_L 0x11500008
! #define IR_RING_SIZE 0x1150000C
! #define IR_RING_PROMPT 0x11500010
! #define IR_RING_ADDR_CMPR 0x11500014
! #define IR_CONFIG_1 0x11500020
! #define IR_SIR_FLAGS 0x11500024
! #define IR_ENABLE 0x11500028
! #define IR_READ_PHY_CONFIG 0x1150002C
! #define IR_WRITE_PHY_CONFIG 0x11500030
! #define IR_MAX_PKT_LEN 0x11500034
! #define IR_RX_BYTE_CNT 0x11500038
! #define IR_CONFIG_2 0x1150003C
! #define IR_INTERFACE_CONFIG 0x11500040
/* GPIO */
! #define TSTATE_STATE_READ 0x11900100
! #define TSTATE_STATE_SET 0x11900100
! #define OUTPUT_STATE_READ 0x11900108
! #define OUTPUT_STATE_SET 0x11900108
! #define OUTPUT_STATE_CLEAR 0x1190010C
! #define PIN_STATE 0x11900110
/* Power Management */
! #define PM_SCRATCH_0 0x11900018
! #define PM_SCRATCH_1 0x1190001C
! #define PM_WAKEUP_SOURCE_MASK 0x11900034
! #define PM_ENDIANESS 0x11900038
! #define PM_POWERUP_CONTROL 0x1190003C
! #define PM_WAKEUP_CAUSE 0x1190005C
! #define PM_SLEEP_POWER 0x11900078
! #define PM_SLEEP 0x1190007C
/* Clock Controller */
! #define FQ_CNTRL_1 0x11900020
! #define FQ_CNTRL_2 0x11900024
! #define CLOCK_SOURCE_CNTRL 0x11900028
! #define CPU_PLL_CNTRL 0x11900060
! #define AUX_PLL_CNTRL 0x11900064
/* AC97 Controller */
! #define AC97C_CONFIG 0x10000000
#define AC97C_RECV_SLOTS_BIT 13
#define AC97C_RECV_SLOTS_MASK (0x3ff << AC97C_RECV_SLOTS_BIT)
--- 585,650 ----
/* SSIO */
! #define SSI0_STATUS 0xB1600000
! #define SSI0_INT 0xB1600004
! #define SSI0_INT_ENABLE 0xB1600008
! #define SSI0_CONFIG 0xB1600020
! #define SSI0_ADATA 0xB1600024
! #define SSI0_CLKDIV 0xB1600028
! #define SSI0_CONTROL 0xB1600100
/* SSI1 */
! #define SSI1_STATUS 0xB1680000
! #define SSI1_INT 0xB1680004
! #define SSI1_INT_ENABLE 0xB1680008
! #define SSI1_CONFIG 0xB1680020
! #define SSI1_ADATA 0xB1680024
! #define SSI1_CLKDIV 0xB1680028
! #define SSI1_CONTROL 0xB1680100
/* IrDA Controller */
! #define IR_RING_PTR_STATUS 0xB1500000
! #define IR_RING_BASE_ADDR_H 0xB1500004
! #define IR_RING_BASE_ADDR_L 0xB1500008
! #define IR_RING_SIZE 0xB150000C
! #define IR_RING_PROMPT 0xB1500010
! #define IR_RING_ADDR_CMPR 0xB1500014
! #define IR_CONFIG_1 0xB1500020
! #define IR_SIR_FLAGS 0xB1500024
! #define IR_ENABLE 0xB1500028
! #define IR_READ_PHY_CONFIG 0xB150002C
! #define IR_WRITE_PHY_CONFIG 0xB1500030
! #define IR_MAX_PKT_LEN 0xB1500034
! #define IR_RX_BYTE_CNT 0xB1500038
! #define IR_CONFIG_2 0xB150003C
! #define IR_INTERFACE_CONFIG 0xB1500040
/* GPIO */
! #define PIN_FUNCTION 0xB190002C
! #define TSTATE_STATE_READ 0xB1900100
! #define TSTATE_STATE_SET 0xB1900100
! #define OUTPUT_STATE_READ 0xB1900108
! #define OUTPUT_STATE_SET 0xB1900108
! #define OUTPUT_STATE_CLEAR 0xB190010C
! #define PIN_STATE 0xB1900110
/* Power Management */
! #define PM_SCRATCH_0 0xB1900018
! #define PM_SCRATCH_1 0xB190001C
! #define PM_WAKEUP_SOURCE_MASK 0xB1900034
! #define PM_ENDIANESS 0xB1900038
! #define PM_POWERUP_CONTROL 0xB190003C
! #define PM_WAKEUP_CAUSE 0xB190005C
! #define PM_SLEEP_POWER 0xB1900078
! #define PM_SLEEP 0xB190007C
/* Clock Controller */
! #define FQ_CNTRL_1 0xB1900020
! #define FQ_CNTRL_2 0xB1900024
! #define CLOCK_SOURCE_CNTRL 0xB1900028
! #define CPU_PLL_CNTRL 0xB1900060
! #define AUX_PLL_CNTRL 0xB1900064
/* AC97 Controller */
! #define AC97C_CONFIG 0xB0000000
#define AC97C_RECV_SLOTS_BIT 13
#define AC97C_RECV_SLOTS_MASK (0x3ff << AC97C_RECV_SLOTS_BIT)
***************
*** 720,724 ****
#define AC97C_SYNC (1<<1)
#define AC97C_RESET (1<<0)
! #define AC97C_STATUS 0x10000004
#define AC97C_XU (1<<11)
#define AC97C_XO (1<<10)
--- 654,658 ----
#define AC97C_SYNC (1<<1)
#define AC97C_RESET (1<<0)
! #define AC97C_STATUS 0xB0000004
#define AC97C_XU (1<<11)
#define AC97C_XO (1<<10)
***************
*** 733,742 ****
#define AC97C_RE (1<<1)
#define AC97C_RF (1<<0)
! #define AC97C_DATA 0x10000008
! #define AC97C_CMD 0x1000000C
#define AC97C_WD_BIT 16
#define AC97C_READ (1<<7)
#define AC97C_INDEX_MASK 0x7f
! #define AC97C_CNTRL 0x10000010
#define AC97C_RS (1<<1)
#define AC97C_CE (1<<0)
--- 667,676 ----
#define AC97C_RE (1<<1)
#define AC97C_RF (1<<0)
! #define AC97C_DATA 0xB0000008
! #define AC97C_CMD 0xB000000C
#define AC97C_WD_BIT 16
#define AC97C_READ (1<<7)
#define AC97C_INDEX_MASK 0x7f
! #define AC97C_CNTRL 0xB0000010
#define AC97C_RS (1<<1)
#define AC97C_CE (1<<0)
|
|
From: Pete P. <pp...@us...> - 2001-08-28 07:23:57
|
Update of /cvsroot/linux-mips/linux/arch/mips/au1000/pb1000
In directory usw-pr-cvs1:/tmp/cvs-serv14591/arch/mips/au1000/pb1000
Modified Files:
init.c setup.c
Log Message:
Added preliminary power management supuport:
* turn off the clocks to the uarts when not used
* turn off the clocks to the ethernets when not used
* adhoc /proc interface for putting the cpu to sleep and
dynamically scaling the cpu frequency.
* fixed a pci compile problem
Index: init.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/au1000/pb1000/init.c,v
retrieving revision 1.2
retrieving revision 1.3
diff -C2 -d -r1.2 -r1.3
*** init.c 2001/08/17 22:53:26 1.2
--- init.c 2001/08/28 07:23:54 1.3
***************
*** 43,50 ****
char **prom_argv, **prom_envp;
extern void __init prom_init_cmdline(void);
int __init prom_init(int argc, char **argv, char **envp, int *prom_vec)
{
- char *env;
unsigned char *memsize_str;
unsigned long memsize;
--- 43,50 ----
char **prom_argv, **prom_envp;
extern void __init prom_init_cmdline(void);
+ extern char *prom_getenv(char *envname);
int __init prom_init(int argc, char **argv, char **envp, int *prom_vec)
{
unsigned char *memsize_str;
unsigned long memsize;
Index: setup.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/au1000/pb1000/setup.c,v
retrieving revision 1.5
retrieving revision 1.6
diff -C2 -d -r1.5 -r1.6
*** setup.c 2001/08/25 02:19:27 1.5
--- setup.c 2001/08/28 07:23:54 1.6
***************
*** 60,84 ****
extern struct rtc_ops no_rtc_ops;
extern char * __init prom_getcmdline(void);
! extern void au1000_restart(void);
extern void au1000_halt(void);
extern void au1000_power_off(void);
- struct {
- struct resource ram;
- struct resource io;
- struct resource sram;
- struct resource flash;
- struct resource boot;
- struct resource pcmcia;
- struct resource lcd;
- } au1000_resources = {
- { "RAM", 0, 0x3FFFFFF, IORESOURCE_MEM },
- { "I/O", 0x10000000, 0x119FFFFF },
- { "SRAM", 0x1e000000, 0x1E03FFFF },
- { "System Flash", 0x1F800000, 0x1FBFFFFF },
- { "Boot ROM", 0x1FC00000, 0x1FFFFFFF },
- { "PCMCIA", 0x20000000, 0x27FFFFFF },
- { "LCD", 0x60000000, 0x603FFFFF },
- };
void au1000_wbflush(void)
--- 60,69 ----
extern struct rtc_ops no_rtc_ops;
extern char * __init prom_getcmdline(void);
! extern void au1000_restart(char *);
extern void au1000_halt(void);
extern void au1000_power_off(void);
+ extern struct resource ioport_resource;
+ extern struct resource iomem_resource;
void au1000_wbflush(void)
***************
*** 95,99 ****
#ifdef CONFIG_AU1000_SERIAL_CONSOLE
! if ((argptr = strstr(argptr, "console=ttyS0")) == NULL) {
argptr = prom_getcmdline();
strcat(argptr, " console=ttyS0,115200");
--- 80,84 ----
#ifdef CONFIG_AU1000_SERIAL_CONSOLE
! if ((argptr = strstr(argptr, "console=")) == NULL) {
argptr = prom_getcmdline();
strcat(argptr, " console=ttyS0,115200");
***************
*** 103,116 ****
rtc_ops = &no_rtc_ops;
__wbflush = au1000_wbflush;
! _machine_restart = au1000_restart;
! _machine_halt = au1000_halt;
! _machine_power_off = au1000_power_off;
/*
* IO/MEM resources.
*/
! mips_io_port_base = KSEG1;
! ioport_resource.start = au1000_resources.io.start;
! ioport_resource.end = au1000_resources.lcd.end;
#ifdef CONFIG_BLK_DEV_INITRD
--- 88,103 ----
rtc_ops = &no_rtc_ops;
__wbflush = au1000_wbflush;
! //_machine_restart = au1000_restart;
! //_machine_halt = au1000_halt;
! //_machine_power_off = au1000_power_off;
/*
* IO/MEM resources.
*/
! mips_io_port_base = 0;
! ioport_resource.start = 0;
! ioport_resource.end = 0xffffffff;
! iomem_resource.start = 0;
! ioport_resource.end = 0xffffffff;
#ifdef CONFIG_BLK_DEV_INITRD
***************
*** 143,150 ****
#endif
outl(usb_clocks, CLOCK_SOURCE_CNTRL);
udelay(1000);
- #ifdef CONFIG_USB_OHCI
// enable host controller and wait for reset done
outl(0x08, USB_HOST_CONFIG);
--- 130,138 ----
#endif
+ #ifdef CONFIG_USB_OHCI
+
outl(usb_clocks, CLOCK_SOURCE_CNTRL);
udelay(1000);
// enable host controller and wait for reset done
outl(0x08, USB_HOST_CONFIG);
***************
*** 217,223 ****
#endif
! outl(PC_CNTRL_E0 | PC_CNTRL_EN0 | PC_CNTRL_EN0, PC_COUNTER_CNTRL);
while (inl(PC_COUNTER_CNTRL) & PC_CNTRL_T0S);
! outl(0x8000-1, PC0_TRIM);
printk("Alchemy Semi PB1000 Board\n");
--- 205,221 ----
#endif
! #ifndef CONFIG_SERIAL_NONSTANDARD
! /* don't touch the default serial console */
! outl(0, UART0_ADDR + UART_CLK);
! #endif
! outl(0, UART1_ADDR + UART_CLK);
! outl(0, UART2_ADDR + UART_CLK);
! outl(0, UART3_ADDR + UART_CLK);
!
! while (inl(PC_COUNTER_CNTRL) & PC_CNTRL_E0S);
! outl(PC_CNTRL_E0 | PC_CNTRL_EN0, PC_COUNTER_CNTRL);
! au_sync();
while (inl(PC_COUNTER_CNTRL) & PC_CNTRL_T0S);
! outl(0, PC0_TRIM);
printk("Alchemy Semi PB1000 Board\n");
|
|
From: Pete P. <pp...@us...> - 2001-08-28 07:23:57
|
Update of /cvsroot/linux-mips/linux/drivers/video
In directory usw-pr-cvs1:/tmp/cvs-serv14591/drivers/video
Modified Files:
epson1356fb.c
Log Message:
Added preliminary power management supuport:
* turn off the clocks to the uarts when not used
* turn off the clocks to the ethernets when not used
* adhoc /proc interface for putting the cpu to sleep and
dynamically scaling the cpu frequency.
* fixed a pci compile problem
Index: epson1356fb.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/drivers/video/epson1356fb.c,v
retrieving revision 1.2
retrieving revision 1.3
diff -C2 -d -r1.2 -r1.3
*** epson1356fb.c 2001/08/17 22:53:26 1.2
--- epson1356fb.c 2001/08/28 07:23:54 1.3
***************
*** 1975,1982 ****
#ifdef CONFIG_MIPS_PB1000
if (epfix->system >= SYS_PB1000_CRT && epfix->system <= SYS_PB1000_TFT) {
- extern unsigned int au1000_clock;
u32 static_cfg0;
unsigned int sys_busclk =
! (au1000_clock/1000) / ((int)(inl(PM_POWERUP_CONTROL)&0x03) + 2);
// The board locks-up if the LCD clock is over 40 MHz.
--- 1975,1981 ----
#ifdef CONFIG_MIPS_PB1000
if (epfix->system >= SYS_PB1000_CRT && epfix->system <= SYS_PB1000_TFT) {
u32 static_cfg0;
unsigned int sys_busclk =
! (get_au1000_speed()/1000) / ((int)(inl(PM_POWERUP_CONTROL)&0x03) + 2);
// The board locks-up if the LCD clock is over 40 MHz.
|
|
From: Pete P. <pp...@us...> - 2001-08-28 07:23:57
|
Update of /cvsroot/linux-mips/linux/drivers/net
In directory usw-pr-cvs1:/tmp/cvs-serv14591/drivers/net
Modified Files:
au1000_eth.c
Log Message:
Added preliminary power management supuport:
* turn off the clocks to the uarts when not used
* turn off the clocks to the ethernets when not used
* adhoc /proc interface for putting the cpu to sleep and
dynamically scaling the cpu frequency.
* fixed a pci compile problem
Index: au1000_eth.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/drivers/net/au1000_eth.c,v
retrieving revision 1.3
retrieving revision 1.4
diff -C2 -d -r1.3 -r1.4
*** au1000_eth.c 2001/08/25 02:19:28 1.3
--- au1000_eth.c 2001/08/28 07:23:54 1.4
***************
*** 65,68 ****
--- 65,69 ----
static void dma_free(void *, size_t);
static void hard_stop(struct net_device *);
+ static void enable_rx_tx(struct net_device *dev);
static int __init au1000_probe1(struct net_device *, long, int, int);
static int au1000_init(struct net_device *);
***************
*** 79,89 ****
static inline void update_rx_stats(struct net_device *, u32);
static void au1000_timer(unsigned long);
- static void cleanup_buffers(struct net_device *);
static int au1000_ioctl(struct net_device *, struct ifreq *, int);
static int mdio_read(struct net_device *, int, int);
static void mdio_write(struct net_device *, int, int, u16);
- static inline void sync(void);
extern void ack_rise_edge_irq(unsigned int);
static int next_dev;
--- 80,93 ----
static inline void update_rx_stats(struct net_device *, u32);
static void au1000_timer(unsigned long);
static int au1000_ioctl(struct net_device *, struct ifreq *, int);
static int mdio_read(struct net_device *, int, int);
static void mdio_write(struct net_device *, int, int, u16);
+ // externs
extern void ack_rise_edge_irq(unsigned int);
+ extern int get_ethernet_addr(char *ethernet_addr);
+ extern inline void str2eaddr(unsigned char *ea, unsigned char *str);
+ extern inline unsigned char str2hexnum(unsigned char c);
+ extern char * __init prom_getcmdline(void);
static int next_dev;
***************
*** 120,127 ****
"au1000eth.c:0.1 pp...@mv...\n";
! // FIX! Need real Ethernet addresses
! static unsigned char au1000_mac_addr[2][6] __devinitdata = {
! {0x00, 0x50, 0xc2, 0x0c, 0x30, 0x00},
! {0x00, 0x50, 0xc2, 0x0c, 0x40, 0x00}
};
--- 124,133 ----
"au1000eth.c:0.1 pp...@mv...\n";
! /* These addresses are only used if yamon doesn't tell us what
! * the mac address is, and the mac address is not passed on the
! * command line.
! */
! static unsigned char au1000_mac_addr[6] __devinitdata = {
! 0x00, 0x50, 0xc2, 0x0c, 0x30, 0x00
};
***************
*** 133,141 ****
#define dma32_to_cpu be32_to_cpu
- /* CPU pipeline flush */
- static inline void sync(void)
- {
- asm volatile ("sync");
- }
/* FIXME
--- 139,142 ----
***************
*** 169,172 ****
--- 170,174 ----
data |= MII_CNTL_RST_AUTO | MII_CNTL_AUTO;
mdio_write(dev, phy_addr, MII_CONTROL, data);
+
#ifdef AU1000_ETH_DEBUG
dump_mii(dev, phy_addr);
***************
*** 231,234 ****
--- 233,237 ----
*link = 0;
*speed = 0;
+ dev->if_port = IF_PORT_UNKNOWN;
}
return 0;
***************
*** 455,458 ****
--- 458,472 ----
+ static void enable_rx_tx(struct net_device *dev)
+ {
+ struct au1000_private *aup = (struct au1000_private *) dev->priv;
+
+ if (au1000_debug > 4)
+ printk(KERN_INFO "%s: enable_rx_tx\n", dev->name);
+
+ aup->mac->control |= (MAC_RX_ENABLE | MAC_TX_ENABLE);
+ au_sync_delay(10);
+ }
+
static void hard_stop(struct net_device *dev)
{
***************
*** 463,468 ****
aup->mac->control &= ~(MAC_RX_ENABLE | MAC_TX_ENABLE);
! sync();
! mdelay(10);
}
--- 477,481 ----
aup->mac->control &= ~(MAC_RX_ENABLE | MAC_TX_ENABLE);
! au_sync_delay(10);
}
***************
*** 480,509 ****
hard_stop(dev);
*aup->enable |= MAC_DMA_RESET;
! sync();
! mdelay(10);
aup->tx_full = 0;
spin_unlock_irqrestore(&aup->lock, flags);
}
- static void cleanup_buffers(struct net_device *dev)
- {
- int i;
- struct au1000_private *aup = (struct au1000_private *) dev->priv;
-
- for (i=0; i<NUM_RX_DMA; i++) {
- if (aup->rx_db_inuse[i]) {
- ReleaseDB(aup, aup->rx_db_inuse[i]);
- aup->rx_db_inuse[i] = 0;
- }
- }
-
- for (i=0; i<NUM_TX_DMA; i++) {
- if (aup->tx_db_inuse[i]) {
- ReleaseDB(aup, aup->tx_db_inuse[i]);
- aup->tx_db_inuse[i] = 0;
- }
- }
- }
-
/*
--- 493,503 ----
hard_stop(dev);
*aup->enable |= MAC_DMA_RESET;
! au_sync_delay(2);
! *aup->enable &= ~(MAC_EN_RESET0 | MAC_EN_RESET1 | MAC_EN_RESET2 | MAC_EN_CLOCK_ENABLE);
! au_sync_delay(2);
aup->tx_full = 0;
spin_unlock_irqrestore(&aup->lock, flags);
}
/*
***************
*** 518,527 ****
for (i=0; i<NUM_RX_DMA; i++) {
! aup->rx_dma_ring[i] = (volatile rx_dma_t *) ioremap_nocache((unsigned long)
! (rx_base + sizeof(rx_dma_t)*i), sizeof(rx_dma_t));
}
for (i=0; i<NUM_TX_DMA; i++) {
! aup->tx_dma_ring[i] = (volatile tx_dma_t *)ioremap_nocache((unsigned long)
! (tx_base + sizeof(tx_dma_t)*i), sizeof(tx_dma_t));
}
}
--- 512,519 ----
for (i=0; i<NUM_RX_DMA; i++) {
! aup->rx_dma_ring[i] = (volatile rx_dma_t *) (rx_base + sizeof(rx_dma_t)*i);
}
for (i=0; i<NUM_TX_DMA; i++) {
! aup->tx_dma_ring[i] = (volatile tx_dma_t *) (tx_base + sizeof(tx_dma_t)*i);
}
}
***************
*** 563,567 ****
int i, retval = 0;
db_dest_t *pDB, *pDBfree;
! u16 link, speed;
if ((ioaddr != AU1000_ETH0_BASE) && (ioaddr != AU1000_ETH1_BASE)) {
--- 555,560 ----
int i, retval = 0;
db_dest_t *pDB, *pDBfree;
! char *pmac, *argptr;
! char ethaddr[6];
if ((ioaddr != AU1000_ETH0_BASE) && (ioaddr != AU1000_ETH1_BASE)) {
***************
*** 609,624 ****
/* aup->mac is the base address of the MAC's registers */
! aup->mac = (volatile mac_reg_t *)ioremap_nocache((unsigned long)ioaddr, sizeof(*aup->mac));
/* Setup some variables for quick register address access */
if (ioaddr == AU1000_ETH0_BASE) {
! aup->enable = (volatile u32 *)
! ioremap_nocache((unsigned long)MAC0_ENABLE, sizeof(*aup->enable));
! memcpy(dev->dev_addr, au1000_mac_addr[0], sizeof(dev->dev_addr));
setup_hw_rings(aup, MAC0_RX_DMA_ADDR, MAC0_TX_DMA_ADDR);
}
else if (ioaddr == AU1000_ETH1_BASE) {
! aup->enable = (volatile u32 *)
! ioremap_nocache((unsigned long)MAC1_ENABLE, sizeof(*aup->enable));
! memcpy(dev->dev_addr, au1000_mac_addr[1], sizeof(dev->dev_addr));
setup_hw_rings(aup, MAC1_RX_DMA_ADDR, MAC1_TX_DMA_ADDR);
}
--- 602,631 ----
/* aup->mac is the base address of the MAC's registers */
! aup->mac = (volatile mac_reg_t *)((unsigned long)ioaddr);
/* Setup some variables for quick register address access */
if (ioaddr == AU1000_ETH0_BASE) {
! if (!get_ethernet_addr(ethaddr)) { /* check env variables first */
! memcpy(au1000_mac_addr, ethaddr, sizeof(dev->dev_addr));
! }
! else {
! /* Check command line */
! argptr = prom_getcmdline();
! if ((pmac = strstr(argptr, "ethaddr=")) == NULL) {
! printk(KERN_INFO "%s: No mac address found\n", dev->name);
! /* use the hard coded mac addresses */
! }
! else {
! str2eaddr(ethaddr, pmac + strlen("ethaddr="));
! memcpy(au1000_mac_addr, ethaddr, sizeof(dev->dev_addr));
! }
! }
! aup->enable = (volatile u32 *) ((unsigned long)MAC0_ENABLE);
! memcpy(dev->dev_addr, au1000_mac_addr, sizeof(dev->dev_addr));
setup_hw_rings(aup, MAC0_RX_DMA_ADDR, MAC0_TX_DMA_ADDR);
}
else if (ioaddr == AU1000_ETH1_BASE) {
! aup->enable = (volatile u32 *) ((unsigned long)MAC1_ENABLE);
! memcpy(dev->dev_addr, au1000_mac_addr, sizeof(dev->dev_addr));
! dev->dev_addr[4] += 0x10;
setup_hw_rings(aup, MAC1_RX_DMA_ADDR, MAC1_TX_DMA_ADDR);
}
***************
*** 633,651 ****
* will hang */
*aup->enable = MAC_EN_RESET0 | MAC_EN_RESET1 | MAC_EN_RESET2 |
! MAC_EN_CLOCK_ENABLE | MAC_EN_TOSS;
! sync();
! mdelay(2);
if (mii_probe(dev) != 0) {
goto free_region;
}
- aup->phy_ops->phy_status(dev, aup->phy_addr, &link, &speed);
- if (!link) {
- printk(KERN_INFO "%s: link down resetting...\n", dev->name);
- aup->phy_ops->phy_reset(dev, aup->phy_addr);
- aup->phy_ops->phy_init(dev, aup->phy_addr);
- }
- else {
- printk(KERN_INFO "%s: link up (%s)\n", dev->name, phy_link[speed]);
- }
pDBfree = NULL;
--- 640,648 ----
* will hang */
*aup->enable = MAC_EN_RESET0 | MAC_EN_RESET1 | MAC_EN_RESET2 |
! MAC_EN_CLOCK_ENABLE;
! au_sync_delay(2);
if (mii_probe(dev) != 0) {
goto free_region;
}
pDBfree = NULL;
***************
*** 697,701 ****
*/
reset_mac(dev);
-
return 0;
--- 694,697 ----
***************
*** 729,734 ****
int i;
u32 value, control;
! if (au1000_debug > 4) printk("%s: au1000_init", dev->name);
spin_lock_irqsave(&aup->lock, flags);
--- 725,731 ----
int i;
u32 value, control;
+ u16 link, speed;
! if (au1000_debug > 4) printk("%s: au1000_init\n", dev->name);
spin_lock_irqsave(&aup->lock, flags);
***************
*** 736,743 ****
/* bring the device out of reset */
value = MAC_EN_RESET0 | MAC_EN_RESET1 | MAC_EN_RESET2 |
! MAC_EN_CLOCK_ENABLE | MAC_EN_TOSS;
*aup->enable = value;
! sync();
! mdelay(200);
aup->mac->control = 0;
--- 733,739 ----
/* bring the device out of reset */
value = MAC_EN_RESET0 | MAC_EN_RESET1 | MAC_EN_RESET2 |
! MAC_EN_CLOCK_ENABLE;
*aup->enable = value;
! au_sync_delay(200);
aup->mac->control = 0;
***************
*** 753,763 ****
aup->rx_dma_ring[i]->buff_stat |= RX_DMA_ENABLE;
}
! sync();
control = MAC_DISABLE_RX_OWN | MAC_RX_ENABLE | MAC_TX_ENABLE;
#ifndef CONFIG_CPU_LITTLE_ENDIAN
control |= MAC_BIG_ENDIAN;
#endif
aup->mac->control = control;
spin_unlock_irqrestore(&aup->lock, flags);
--- 749,764 ----
aup->rx_dma_ring[i]->buff_stat |= RX_DMA_ENABLE;
}
+ au_sync();
! aup->phy_ops->phy_status(dev, aup->phy_addr, &link, &speed);
control = MAC_DISABLE_RX_OWN | MAC_RX_ENABLE | MAC_TX_ENABLE;
#ifndef CONFIG_CPU_LITTLE_ENDIAN
control |= MAC_BIG_ENDIAN;
#endif
+ if (link && (dev->if_port == IF_PORT_100BASEFX)) {
+ control |= MAC_FULL_DUPLEX;
+ }
aup->mac->control = control;
+ au_sync();
spin_unlock_irqrestore(&aup->lock, flags);
***************
*** 769,773 ****
struct net_device *dev = (struct net_device *)data;
struct au1000_private *aup = (struct au1000_private *) dev->priv;
! u16 mii_data, link, speed;
if (!dev) {
--- 770,775 ----
struct net_device *dev = (struct net_device *)data;
struct au1000_private *aup = (struct au1000_private *) dev->priv;
! unsigned char if_port;
! u16 link, speed;
if (!dev) {
***************
*** 776,783 ****
return;
}
- if (!(dev->flags & IFF_UP)) {
- goto set_timer;
- }
if (aup->phy_ops->phy_status(dev, aup->phy_addr, &link, &speed) == 0) {
if (link) {
--- 778,783 ----
return;
}
+ if_port = dev->if_port;
if (aup->phy_ops->phy_status(dev, aup->phy_addr, &link, &speed) == 0) {
if (link) {
***************
*** 785,789 ****
netif_carrier_on(dev);
dev->flags |= IFF_RUNNING;
! printk(KERN_DEBUG "%s: link up\n", dev->name);
}
}
--- 785,789 ----
netif_carrier_on(dev);
dev->flags |= IFF_RUNNING;
! printk(KERN_INFO "%s: link up\n", dev->name);
}
}
***************
*** 793,802 ****
dev->flags &= ~IFF_RUNNING;
dev->if_port = 0;
! printk(KERN_DEBUG "%s: link down\n", dev->name);
}
}
}
! set_timer:
aup->timer.expires = RUN_AT((1*HZ));
aup->timer.data = (unsigned long)dev;
--- 793,815 ----
dev->flags &= ~IFF_RUNNING;
dev->if_port = 0;
! printk(KERN_INFO "%s: link down\n", dev->name);
}
}
}
! if (link && (dev->if_port != if_port) && (dev->if_port != IF_PORT_UNKNOWN)) {
! hard_stop(dev);
! if (dev->if_port == IF_PORT_100BASEFX) {
! printk(KERN_INFO "%s: going to full duplex\n", dev->name);
! aup->mac->control |= MAC_FULL_DUPLEX;
! au_sync_delay(1);
! }
! else {
! aup->mac->control &= ~MAC_FULL_DUPLEX;
! au_sync_delay(1);
! }
! enable_rx_tx(dev);
! }
!
aup->timer.expires = RUN_AT((1*HZ));
aup->timer.data = (unsigned long)dev;
***************
*** 875,882 ****
if (status & TX_FRAME_ABORTED) {
! ps->tx_errors++;
! ps->tx_aborted_errors++;
! if (status & (TX_NO_CARRIER | TX_LOSS_CARRIER))
! ps->tx_carrier_errors++;
}
}
--- 888,905 ----
if (status & TX_FRAME_ABORTED) {
! if (dev->if_port == IF_PORT_100BASEFX) {
! if (status & (TX_JAB_TIMEOUT | TX_UNDERRUN)) {
! /* any other tx errors are only valid
! * in half duplex mode */
! ps->tx_errors++;
! ps->tx_aborted_errors++;
! }
! }
! else {
! ps->tx_errors++;
! ps->tx_aborted_errors++;
! if (status & (TX_NO_CARRIER | TX_LOSS_CARRIER))
! ps->tx_carrier_errors++;
! }
}
}
***************
*** 899,903 ****
ptxd->buff_stat &= ~TX_T_DONE;
ptxd->len = 0;
! sync();
aup->tx_tail = (aup->tx_tail + 1) & (NUM_TX_DMA - 1);
--- 922,926 ----
ptxd->buff_stat &= ~TX_T_DONE;
ptxd->len = 0;
! au_sync();
aup->tx_tail = (aup->tx_tail + 1) & (NUM_TX_DMA - 1);
***************
*** 962,966 ****
ptxd->buff_stat = pDB->dma_addr | TX_DMA_ENABLE;
! sync();
dev_kfree_skb(skb);
aup->tx_head = (aup->tx_head + 1) & (NUM_TX_DMA - 1);
--- 985,989 ----
ptxd->buff_stat = pDB->dma_addr | TX_DMA_ENABLE;
! au_sync();
dev_kfree_skb(skb);
aup->tx_head = (aup->tx_head + 1) & (NUM_TX_DMA - 1);
***************
*** 1061,1065 ****
prxd->buff_stat = (u32)(pDB->dma_addr | RX_DMA_ENABLE);
aup->rx_head = (aup->rx_head + 1) & (NUM_RX_DMA - 1);
! sync();
/* next descriptor */
--- 1084,1088 ----
prxd->buff_stat = (u32)(pDB->dma_addr | RX_DMA_ENABLE);
aup->rx_head = (aup->rx_head + 1) & (NUM_RX_DMA - 1);
! au_sync();
/* next descriptor */
***************
*** 1083,1088 ****
return;
}
- au1000_rx(dev);
au1000_tx_ack(dev);
}
--- 1106,1111 ----
return;
}
au1000_tx_ack(dev);
+ au1000_rx(dev);
}
***************
*** 1119,1125 ****
struct au1000_private *aup = (struct au1000_private *) dev->priv;
- /* fixme */
if (au1000_debug > 4)
! printk("%s: set_multicast: flags=%x\n", dev->name, dev->flags);
if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
--- 1142,1147 ----
struct au1000_private *aup = (struct au1000_private *) dev->priv;
if (au1000_debug > 4)
! printk("%s: set_rx_mode: flags=%x\n", dev->name, dev->flags);
if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
***************
*** 1143,1146 ****
--- 1165,1169 ----
aup->mac->multi_hash_high = mc_filter[1];
aup->mac->multi_hash_low = mc_filter[0];
+ aup->mac->control &= ~MAC_PROMISCUOUS;
aup->mac->control |= MAC_HASH_MODE;
}
***************
*** 1181,1185 ****
switch(map->port){
case IF_PORT_UNKNOWN: /* use auto here */
! printk("auto\\n");
dev->if_port = map->port;
/* Link Down: the timer will bring it up */
--- 1204,1208 ----
switch(map->port){
case IF_PORT_UNKNOWN: /* use auto here */
! printk(KERN_INFO "%s: config phy for aneg\n", dev->name);
dev->if_port = map->port;
/* Link Down: the timer will bring it up */
***************
*** 1197,1201 ****
case IF_PORT_10BASET: /* 10BaseT */
! printk("10baseT\n");
dev->if_port = map->port;
--- 1220,1224 ----
case IF_PORT_10BASET: /* 10BaseT */
! printk(KERN_INFO "%s: config phy for 10BaseT\n", dev->name);
dev->if_port = map->port;
***************
*** 1205,1209 ****
/* set Speed to 10Mbps, Half Duplex */
control = mdio_read(dev, aup->phy_addr, MII_CONTROL);
- printk("read control %x\n", control);
control &= ~(MII_CNTL_F100 | MII_CNTL_AUTO | MII_CNTL_FDX);
--- 1228,1231 ----
***************
*** 1214,1218 ****
case IF_PORT_100BASET: /* 100BaseT */
case IF_PORT_100BASETX: /* 100BaseTx */
! printk("100 base T/TX\n");
dev->if_port = map->port;
--- 1236,1240 ----
case IF_PORT_100BASET: /* 100BaseT */
case IF_PORT_100BASETX: /* 100BaseTx */
! printk(KERN_INFO "%s: config phy for 100BaseTX\n", dev->name);
dev->if_port = map->port;
***************
*** 1230,1234 ****
case IF_PORT_100BASEFX: /* 100BaseFx */
! printk("100 Base FX\n");
dev->if_port = map->port;
--- 1252,1256 ----
case IF_PORT_100BASEFX: /* 100BaseFx */
! printk(KERN_INFO "%s: config phy for 100BaseFX\n", dev->name);
dev->if_port = map->port;
***************
*** 1246,1255 ****
case IF_PORT_AUI: /* AUI */
/* These Modes are not supported (are they?)*/
! printk(KERN_INFO "Not supported");
return -EOPNOTSUPP;
break;
default:
! printk("Invalid");
return -EINVAL;
}
--- 1268,1277 ----
case IF_PORT_AUI: /* AUI */
/* These Modes are not supported (are they?)*/
! printk(KERN_ERR "%s: 10Base2/AUI not supported", dev->name);
return -EOPNOTSUPP;
break;
default:
! printk(KERN_ERR "%s: Invalid media selected", dev->name);
return -EINVAL;
}
|
|
From: Pete P. <pp...@us...> - 2001-08-28 07:23:57
|
Update of /cvsroot/linux-mips/linux/arch/mips/au1000/common
In directory usw-pr-cvs1:/tmp/cvs-serv14591/arch/mips/au1000/common
Modified Files:
Makefile irq.c prom.c reset.c serial.c time.c
Added Files:
clocks.c power.c
Log Message:
Added preliminary power management supuport:
* turn off the clocks to the uarts when not used
* turn off the clocks to the ethernets when not used
* adhoc /proc interface for putting the cpu to sleep and
dynamically scaling the cpu frequency.
* fixed a pci compile problem
--- NEW FILE: clocks.c ---
/*
* BRIEF MODULE DESCRIPTION
* Simple Au1000 clocks routines.
*
* Copyright 2001 MontaVista Software Inc.
* Author: MontaVista Software, Inc.
* pp...@mv... or so...@mv...
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
static unsigned int au1000_clock;
static unsigned long uart_baud_base;
/*
* Set the au1000_clock
*/
void set_au1000_speed(unsigned int new_freq)
{
au1000_clock = new_freq;
}
unsigned int get_au1000_speed(void)
{
return au1000_clock;
}
/*
* The UART baud base is not known at compile time ... if
* we want to be able to use the same code on different
* speed CPUs.
*/
unsigned long get_au1000_uart_baud_base(void)
{
return uart_baud_base;
}
void set_au1000_uart_baud_base(unsigned long new_baud_base)
{
uart_baud_base = new_baud_base;
}
--- NEW FILE: power.c ---
/*
* BRIEF MODULE DESCRIPTION
* Au1000 Power Management routines.
*
* Copyright 2001 MontaVista Software Inc.
* Author: MontaVista Software, Inc.
* pp...@mv... or so...@mv...
*
* Some of the routines are right out of init/main.c, whose
* copyrights apply here.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <linux/init.h>
#include <linux/pm.h>
#include <linux/malloc.h>
#include <linux/sysctl.h>
#include <linux/acpi.h>
#include <asm/string.h>
#include <asm/uaccess.h>
#include <asm/io.h>
#include <asm/system.h>
#include <asm/au1000.h>
#define DEBUG 1
#ifdef DEBUG
# define DPRINTK(fmt, args...) printk("%s: " fmt, __FUNCTION__ , ## args)
#else
# define DPRINTK(fmt, args...)
#endif
inline void au1_wait(void);
static void calibrate_delay(void);
extern void set_au1000_speed(unsigned int new_freq);
extern unsigned int get_au1000_speed(void);
extern unsigned long get_au1000_uart_baud_base(void);
extern void set_au1000_uart_baud_base(unsigned long new_baud_base);
extern unsigned long save_local_and_disable(int controller);
extern void restore_local_and_enable(int controller, unsigned long mask);
extern void local_enable_irq(unsigned int irq_nr);
#ifdef CONFIG_PM
unsigned long suspend_mode;
void wakeup_from_suspend(void)
{
suspend_mode = 0;
}
int au_sleep(void)
{
unsigned long wakeup, flags;
save_and_cli(flags);
flush_cache_all();
/* pin 6 is gpio */
writel(readl(PIN_STATE) & ~(1<<11), PIN_STATE);
/* gpio 6 can cause a wake up event */
wakeup = readl(PM_WAKEUP_SOURCE_MASK);
wakeup &= ~(1<<8); /* turn off match20 wakeup */
wakeup |= 1<<6; /* turn on gpio 6 wakeup */
writel(wakeup, PM_WAKEUP_SOURCE_MASK);
writel(1, PM_WAKEUP_CAUSE); /* clear cause */
writel(1, PM_SLEEP_POWER); /* prepare to sleep */
__asm__("la $4, 1f\n\t"
"lui $5, 0xb190\n\t"
"ori $5, 0x18\n\t"
"sw $4, 0($5)\n\t"
"li $4, 1\n\t"
"lui $5, 0xb190\n\t"
"ori $5, 0x7c\n\t"
"sw $4, 0($5)\n\t"
"sync\n\t"
"1:\t\n\t"
"nop\n\t");
/* after a wakeup, the cpu vectors back to 0x1fc00000 so
* it's up to the boot code to get us back here.
*/
restore_flags(flags);
return 0;
}
static int pm_do_sleep(ctl_table *ctl, int write, struct file *file, void *buffer, size_t *len)
{
int retval = 0;
if (!write) {
*len = 0;
}
else {
retval = pm_send_all(PM_SUSPEND, (void *)2);
if (retval)
return retval;
au_sleep();
retval = pm_send_all(PM_RESUME, (void *)0);
}
return retval;
}
static int pm_do_suspend(ctl_table *ctl, int write, struct file *file, void *buffer, size_t *len)
{
int retval = 0;
if (!write) {
*len = 0;
}
else {
retval = pm_send_all(PM_SUSPEND, (void *)2);
if (retval)
return retval;
suspend_mode = 1;
au1_wait();
retval = pm_send_all(PM_RESUME, (void *)0);
}
return retval;
}
static int pm_do_freq(ctl_table *ctl, int write, struct file *file, void *buffer, size_t *len)
{
int retval = 0, i;
unsigned long val, pll;
#define TMPBUFLEN 64
#define MAX_CPU_FREQ 396
char buf[8], *p;
unsigned long flags, intc0_mask, intc1_mask;
unsigned long old_baud_base, old_cpu_freq, baud_rate, old_clk, old_refresh;
unsigned long new_baud_base, new_cpu_freq, new_clk, new_refresh;
save_and_cli(flags);
if (!write) {
*len = 0;
}
else {
/* Parse the new frequency */
if (*len > TMPBUFLEN-1) {
restore_flags(flags);
return -EFAULT;
}
if(copy_from_user(buf, buffer, *len)) {
restore_flags(flags);
return -EFAULT;
}
buf[*len] = 0;
p = buf;
val = simple_strtoul(p, &p, 0);
if (val > MAX_CPU_FREQ) {
restore_flags(flags);
return -EFAULT;
}
pll = val/12;
if ((pll > 33) || (pll < 7)) { /* 396 MHz max, 84 MHz min */
/* revisit this for higher speed cpus */
restore_flags(flags);
return -EFAULT;
}
old_baud_base = get_au1000_uart_baud_base();
old_cpu_freq = get_au1000_speed();
new_cpu_freq = pll * 12 * 1000000;
new_baud_base = (new_cpu_freq / 4) / 16;
set_au1000_speed(new_cpu_freq);
set_au1000_uart_baud_base(new_baud_base);
old_refresh = readl(REFRESH_CONFIG) & 0x1ffffff;
new_refresh = ((old_refresh * new_cpu_freq)/old_cpu_freq) |
(readl(REFRESH_CONFIG) & ~0x1ffffff);
writel(pll, CPU_PLL_CNTRL);
au_sync_delay(1);
writel(new_refresh, REFRESH_CONFIG);
au_sync_delay(1);
for (i=0; i<4; i++) {
if (readl(UART_BASE + UART_MOD_CNTRL + i*0x00100000) == 3) {
old_clk = readl(UART_BASE + UART_CLK + i*0x00100000);
// baud_rate = baud_base/clk
baud_rate = old_baud_base / old_clk;
/* we won't get an exact baud rate and the error
* could be significant enough that our new
* calculation will result in a clock that will
* give us a baud rate that's too far off from
* what we really want.
*/
if (baud_rate > 100000)
baud_rate = 115200;
else if (baud_rate > 50000)
baud_rate = 57600;
else if(baud_rate > 30000)
baud_rate = 38400;
else if (baud_rate > 17000)
baud_rate = 19200;
else
(baud_rate = 9600);
// new_clk = new_baud_base/baud_rate
new_clk = new_baud_base/baud_rate;
writel(new_clk, UART_BASE + UART_CLK + i*0x00100000);
au_sync_delay(10);
}
}
}
/* We don't want _any_ interrupts other than
* match20. Otherwise our calibrate_delay()
* calculation will be off, potentially a lot.
*/
intc0_mask = save_local_and_disable(0);
intc1_mask = save_local_and_disable(1);
local_enable_irq(AU1000_PC0_MATCH2_INT);
restore_flags(flags);
calibrate_delay();
restore_local_and_enable(0, intc0_mask);
restore_local_and_enable(1, intc1_mask);
return retval;
}
static struct ctl_table pm_table[] =
{
{ACPI_S1_SLP_TYP, "suspend", NULL, 0, 0600, NULL, &pm_do_suspend},
{ACPI_SLEEP, "sleep", NULL, 0, 0600, NULL, &pm_do_sleep},
{CTL_ACPI, "freq", NULL, 0, 0600, NULL, &pm_do_freq},
{0}
};
static struct ctl_table pm_dir_table[] =
{
{CTL_ACPI, "pm", NULL, 0, 0555, pm_table},
{0}
};
/*
* Initialize power interface
*/
static int __init pm_init(void)
{
register_sysctl_table(pm_dir_table, 1);
return 0;
}
__initcall(pm_init);
inline void au1_wait(void)
{
__asm__(".set\tmips3\n\t"
"wait\n\t"
"nop\n\t"
"nop\n\t"
"nop\n\t"
"nop\n\t"
".set\tmips0");
}
/*
* This is right out of init/main.c
*/
/* This is the number of bits of precision for the loops_per_jiffy. Each
bit takes on average 1.5/HZ seconds. This (like the original) is a little
better than 1% */
#define LPS_PREC 8
static void calibrate_delay(void)
{
unsigned long ticks, loopbit;
int lps_precision = LPS_PREC;
loops_per_jiffy = (1<<12);
while (loops_per_jiffy <<= 1) {
/* wait for "start of" clock tick */
ticks = jiffies;
while (ticks == jiffies)
/* nothing */;
/* Go .. */
ticks = jiffies;
__delay(loops_per_jiffy);
ticks = jiffies - ticks;
if (ticks)
break;
}
/* Do a binary approximation to get loops_per_jiffy set to equal one clock
(up to lps_precision bits) */
loops_per_jiffy >>= 1;
loopbit = loops_per_jiffy;
while ( lps_precision-- && (loopbit >>= 1) ) {
loops_per_jiffy |= loopbit;
ticks = jiffies;
while (ticks == jiffies);
ticks = jiffies;
__delay(loops_per_jiffy);
if (jiffies != ticks) /* longer than 1 tick */
loops_per_jiffy &= ~loopbit;
}
}
#else /* CONFIG_PM */
void au1_wait(void)
{
__asm__("nop\n\t"
"nop\n\t");
}
#endif /* CONFIG_PM */
Index: Makefile
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/au1000/common/Makefile,v
retrieving revision 1.4
retrieving revision 1.5
diff -C2 -d -r1.4 -r1.5
*** Makefile 2001/08/25 02:19:27 1.4
--- Makefile 2001/08/28 07:23:54 1.5
***************
*** 20,32 ****
O_TARGET := au1000.o
! obj-y := prom.o dbg_io.o int-handler.o dma.o irq.o puts.o time.o reset.o
obj-$(CONFIG_AU1000_UART) += serial.o
obj-$(CONFIG_AU1000_USB_DEVICE) += usbdev.o
obj-$(CONFIG_REMOTE_DEBUG) += dbg_io.o
- obj-$(CONFIG_BLK_DEV_INITRD) += ramdisk.o
-
- ramdisk.o:
- mkramobj ramdisk ramdisk.o
include $(TOPDIR)/Rules.make
--- 20,28 ----
O_TARGET := au1000.o
! obj-y := prom.o dbg_io.o int-handler.o dma.o irq.o puts.o time.o reset.o power.o clocks.o
obj-$(CONFIG_AU1000_UART) += serial.o
obj-$(CONFIG_AU1000_USB_DEVICE) += usbdev.o
obj-$(CONFIG_REMOTE_DEBUG) += dbg_io.o
include $(TOPDIR)/Rules.make
Index: irq.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/au1000/common/irq.c,v
retrieving revision 1.4
retrieving revision 1.5
diff -C2 -d -r1.4 -r1.5
*** irq.c 2001/08/25 02:19:27 1.4
--- irq.c 2001/08/28 07:23:54 1.5
***************
*** 52,57 ****
#endif
- #define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
-
#undef DEBUG_IRQ
#ifdef DEBUG_IRQ
--- 52,55 ----
***************
*** 73,81 ****
extern asmlinkage void au1000_IRQ(void);
-
extern void set_debug_traps(void);
! extern irq_cpustat_t irq_stat [];
! extern irq_desc_t irq_desc[NR_IRQS];
!
unsigned int local_bh_count[NR_CPUS];
unsigned int local_irq_count[NR_CPUS];
--- 71,76 ----
extern asmlinkage void au1000_IRQ(void);
extern void set_debug_traps(void);
! extern irq_cpustat_t irq_stat [NR_CPUS];
unsigned int local_bh_count[NR_CPUS];
unsigned int local_irq_count[NR_CPUS];
***************
*** 87,143 ****
static inline void mask_and_ack_rise_edge_irq(unsigned int irq_nr);
static inline void mask_and_ack_fall_edge_irq(unsigned int irq_nr);
! static inline void local_enable_irq(unsigned int irq_nr);
! static inline void local_disable_irq(unsigned int irq_nr);
unsigned long spurious_interrupts;
extern unsigned int do_IRQ(int irq, struct pt_regs *regs);
extern void __init init_generic_irq(void);
-
- static inline void sync(void)
- {
- __asm volatile ("sync");
- }
-
-
- /* Function for careful CP0 interrupt mask access */
- static inline void modify_cp0_intmask(unsigned clr_mask, unsigned set_mask)
- {
- unsigned long status = read_32bit_cp0_register(CP0_STATUS);
- status &= ~((clr_mask & 0xFF) << 8);
- status |= (set_mask & 0xFF) << 8;
- write_32bit_cp0_register(CP0_STATUS, status);
- }
-
-
- static inline void mask_cpu_irq_input(unsigned int irq_nr)
- {
- modify_cp0_intmask(irq_nr, 0);
- }
-
-
- static inline void unmask_cpu_irq_input(unsigned int irq_nr)
- {
- modify_cp0_intmask(0, irq_nr);
- }
-
-
- static void disable_cpu_irq_input(unsigned int irq_nr)
- {
- unsigned long flags;
-
- save_and_cli(flags);
- mask_cpu_irq_input(irq_nr);
- restore_flags(flags);
- }
-
! static void enable_cpu_irq_input(unsigned int irq_nr)
! {
! unsigned long flags;
!
! save_and_cli(flags);
! unmask_cpu_irq_input(irq_nr);
! restore_flags(flags);
! }
--- 82,95 ----
static inline void mask_and_ack_rise_edge_irq(unsigned int irq_nr);
static inline void mask_and_ack_fall_edge_irq(unsigned int irq_nr);
! inline void local_enable_irq(unsigned int irq_nr);
! inline void local_disable_irq(unsigned int irq_nr);
unsigned long spurious_interrupts;
extern unsigned int do_IRQ(int irq, struct pt_regs *regs);
extern void __init init_generic_irq(void);
! #ifdef CONFIG_PM
! extern void counter0_irq(int irq, void *dev_id, struct pt_regs *regs);
! #endif
***************
*** 185,188 ****
--- 137,141 ----
outl(1<<irq_nr, INTC1_SOURCE_SET);
outl(1<<irq_nr, INTC1_MASK_CLEAR);
+ outl(1<<irq_nr, INTC1_WAKEUP_CLEAR);
}
else {
***************
*** 226,231 ****
outl(1<<irq_nr, INTC0_SOURCE_SET);
outl(1<<irq_nr, INTC0_MASK_CLEAR);
}
! sync();
}
--- 179,185 ----
outl(1<<irq_nr, INTC0_SOURCE_SET);
outl(1<<irq_nr, INTC0_MASK_CLEAR);
+ outl(1<<irq_nr, INTC0_WAKEUP_CLEAR);
}
! au_sync();
}
***************
*** 245,269 ****
! static inline void local_enable_irq(unsigned int irq_nr)
{
if (irq_nr > AU1000_LAST_INTC0_INT) {
outl(1<<irq_nr, INTC1_MASK_SET);
}
else {
outl(1<<irq_nr, INTC0_MASK_SET);
}
! sync();
}
! static inline void local_disable_irq(unsigned int irq_nr)
{
if (irq_nr > AU1000_LAST_INTC0_INT) {
outl(1<<irq_nr, INTC1_MASK_CLEAR);
}
else {
outl(1<<irq_nr, INTC0_MASK_CLEAR);
}
! sync();
}
--- 199,227 ----
! inline void local_enable_irq(unsigned int irq_nr)
{
if (irq_nr > AU1000_LAST_INTC0_INT) {
outl(1<<irq_nr, INTC1_MASK_SET);
+ outl(1<<irq_nr, INTC1_WAKEUP_SET);
}
else {
outl(1<<irq_nr, INTC0_MASK_SET);
+ outl(1<<irq_nr, INTC0_WAKEUP_SET);
}
! au_sync();
}
! inline void local_disable_irq(unsigned int irq_nr)
{
if (irq_nr > AU1000_LAST_INTC0_INT) {
outl(1<<irq_nr, INTC1_MASK_CLEAR);
+ outl(1<<irq_nr, INTC1_WAKEUP_CLEAR);
}
else {
outl(1<<irq_nr, INTC0_MASK_CLEAR);
+ outl(1<<irq_nr, INTC0_WAKEUP_CLEAR);
}
! au_sync();
}
***************
*** 279,283 ****
outl(1<<irq_nr, INTC0_MASK_CLEAR);
}
! sync();
}
--- 237,241 ----
outl(1<<irq_nr, INTC0_MASK_CLEAR);
}
! au_sync();
}
***************
*** 293,296 ****
--- 251,255 ----
outl(1<<irq_nr, INTC0_MASK_CLEAR);
}
+ au_sync();
}
***************
*** 309,313 ****
#endif
local_disable_irq(irq_nr);
! sync();
return;
}
--- 268,272 ----
#endif
local_disable_irq(irq_nr);
! au_sync();
return;
}
***************
*** 329,336 ****
local_enable_irq(irq_nr);
else
! printk("warning: end_irq %d did not enable\n", irq_nr);
}
static struct hw_interrupt_type rise_edge_irq_type = {
"Au1000 Rise Edge",
--- 288,340 ----
local_enable_irq(irq_nr);
else
! printk("warning: end_irq %d did not enable (%x)\n",
! irq_nr, irq_desc[irq_nr].status);
}
+ unsigned long save_local_and_disable(int controller)
+ {
+ int i;
+ unsigned long flags, mask;
+ save_and_cli(flags);
+
+ if (controller) {
+ mask = readl(INTC1_MASK_SET);
+ for (i=0; i<32; i++) {
+ local_disable_irq(i);
+ }
+ }
+ else {
+ mask = readl(INTC0_MASK_SET);
+ for (i=32; i<64; i++) {
+ local_disable_irq(i);
+ }
+ }
+ restore_flags(flags);
+ return mask;
+ }
+ void restore_local_and_enable(int controller, unsigned long mask)
+ {
+ int i;
+ unsigned long flags, new_mask;
+ save_and_cli(flags);
+
+ for (i=0; i<32; i++) {
+ if (mask & (1<<i)) {
+ if (controller)
+ local_enable_irq(i+32);
+ else
+ local_enable_irq(i);
+ }
+ }
+ if (controller)
+ new_mask = readl(INTC1_MASK_SET);
+ else
+ new_mask = readl(INTC0_MASK_SET);
+
+ restore_flags(flags);
+ }
+
+
static struct hw_interrupt_type rise_edge_irq_type = {
"Au1000 Rise Edge",
***************
*** 368,376 ****
};
!
! void enable_cpu_timer(void)
{
! enable_cpu_irq_input(1<<MIPS_TIMER_IP); /* timer interrupt */
}
--- 372,381 ----
};
! #ifdef CONFIG_PM
! void startup_match20_interrupt(void)
{
! local_enable_irq(AU1000_PC0_MATCH2_INT);
}
+ #endif
***************
*** 379,383 ****
int i;
unsigned long cp0_status;
- extern char except_vec0_au1000;
cp0_status = read_32bit_cp0_register(CP0_STATUS);
--- 384,387 ----
***************
*** 386,398 ****
init_generic_irq();
-
- /* overwrite vec0 with our own */
- memcpy((void *)KSEG0, &except_vec0_au1000, 0x80);
- flush_icache_range(KSEG0, KSEG0 + 0x200);
- /*
- * Setup high priority interrupts on int_request0; low priority on
- * int_request1
- */
for (i = 0; i <= NR_IRQS; i++) {
switch (i) {
--- 390,394 ----
***************
*** 423,428 ****
irq_desc[i].handler = &rise_edge_irq_type;
break;
default: /* active high, level interrupt */
! setup_local_irq(i, INTC_INT_HIGH_LEVEL, 1);
irq_desc[i].handler = &level_irq_type;
break;
--- 419,431 ----
irq_desc[i].handler = &rise_edge_irq_type;
break;
+ // Careful if you change match 2 request!
+ // The interrupt handler is called directly
+ // from the low level dispatch code.
+ case AU1000_PC0_MATCH2_INT:
+ setup_local_irq(i, INTC_INT_RISE_EDGE, 1);
+ irq_desc[i].handler = &rise_edge_irq_type;
+ break;
default: /* active high, level interrupt */
! setup_local_irq(i, INTC_INT_HIGH_LEVEL, 0);
irq_desc[i].handler = &level_irq_type;
break;
***************
*** 446,464 ****
void intc0_req0_irqdispatch(struct pt_regs *regs)
{
int irq = 0, i;
! unsigned long int_request;
! int_request = inl(INTC0_REQ0_INT);
! if (!int_request) return;
for (i=0; i<32; i++) {
! if ((int_request & 0x1)) {
do_IRQ(irq, regs);
}
irq++;
- int_request >>= 1;
}
}
--- 449,474 ----
+ /*
+ * Interrupts are nested. Even if an interrupt handler is registered
+ * as "fast", we might get another interrupt before we return from
+ * intcX_reqX_irqdispatch().
+ */
+
void intc0_req0_irqdispatch(struct pt_regs *regs)
{
int irq = 0, i;
! static unsigned long intc0_req0 = 0;
! intc0_req0 |= inl(INTC0_REQ0_INT);
! if (!intc0_req0) return;
for (i=0; i<32; i++) {
! if ((intc0_req0 & (1<<i))) {
! intc0_req0 &= ~(1<<i);
do_IRQ(irq, regs);
+ return;
}
irq++;
}
}
***************
*** 468,502 ****
{
int irq = 0, i;
! unsigned long int_request;
! int_request = inl(INTC0_REQ1_INT);
! if (!int_request) return;
for (i=0; i<32; i++) {
! if ((int_request & 0x1)) {
! do_IRQ(irq, regs);
}
irq++;
- int_request >>= 1;
}
}
void intc1_req0_irqdispatch(struct pt_regs *regs)
{
int irq = 0, i;
! unsigned long int_request;
! int_request = inl(INTC1_REQ0_INT);
! if (!int_request) return;
for (i=0; i<32; i++) {
! if ((int_request & 0x1)) {
! do_IRQ(irq, regs);
}
irq++;
- int_request >>= 1;
}
}
--- 478,528 ----
{
int irq = 0, i;
! static unsigned long intc0_req1 = 0;
! intc0_req1 = inl(INTC0_REQ1_INT);
! if (!intc0_req1) return;
for (i=0; i<32; i++) {
! if ((intc0_req1 & (1<<i))) {
! intc0_req1 &= ~(1<<i);
! #ifdef CONFIG_PM
! if (i == AU1000_PC0_MATCH2_INT) {
! mask_and_ack_rise_edge_irq(irq);
! counter0_irq(irq, NULL, regs);
! local_enable_irq(irq);
! }
! else
! #endif
! {
! do_IRQ(irq, regs);
! }
! return;
}
irq++;
}
}
+ /*
+ * Interrupt Controller 1:
+ * interrupts 32 - 63
+ */
void intc1_req0_irqdispatch(struct pt_regs *regs)
{
int irq = 0, i;
! static unsigned long intc1_req0 = 0;
! intc1_req0 |= inl(INTC1_REQ0_INT);
! if (!intc1_req0) return;
for (i=0; i<32; i++) {
! if ((intc1_req0 & (1<<i))) {
! intc1_req0 &= ~(1<<i);
! do_IRQ(irq+32, regs);
! return;
}
irq++;
}
}
***************
*** 506,521 ****
{
int irq = 0, i;
! unsigned long int_request;
! int_request = inl(INTC1_REQ1_INT);
! if (!int_request) return;
for (i=0; i<32; i++) {
! if ((int_request & 0x1)) {
! do_IRQ(irq, regs);
}
irq++;
- int_request >>= 1;
}
}
--- 532,548 ----
{
int irq = 0, i;
! static unsigned long intc1_req1 = 0;
! intc1_req1 |= inl(INTC1_REQ1_INT);
! if (!intc1_req1) return;
for (i=0; i<32; i++) {
! if ((intc1_req1 & (1<<i))) {
! intc1_req1 &= ~(1<<i);
! do_IRQ(irq+32, regs);
! return;
}
irq++;
}
}
Index: prom.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/au1000/common/prom.c,v
retrieving revision 1.3
retrieving revision 1.4
diff -C2 -d -r1.3 -r1.4
*** prom.c 2001/08/25 02:19:27 1.3
--- prom.c 2001/08/28 07:23:54 1.4
***************
*** 46,56 ****
char arcs_cmdline[COMMAND_LINE_SIZE];
! int prom_argc;
! char **prom_argv, **prom_envp;
! typedef struct {
! char *name;
! /* char *val; */
! } t_env_var;
--- 46,57 ----
char arcs_cmdline[COMMAND_LINE_SIZE];
! extern int prom_argc;
! extern char **prom_argv, **prom_envp;
! typedef struct
! {
! char *name;
! /* char *val; */
! }t_env_var;
***************
*** 102,106 ****
}
! static inline unsigned char str2hexnum(unsigned char c)
{
if(c >= '0' && c <= '9')
--- 103,107 ----
}
! inline unsigned char str2hexnum(unsigned char c)
{
if(c >= '0' && c <= '9')
***************
*** 111,120 ****
}
! int __init page_is_ram(unsigned long pagenr)
{
! return 1;
! }
! void prom_free_prom_memory (void)
{
}
--- 112,151 ----
}
! inline void str2eaddr(unsigned char *ea, unsigned char *str)
{
! int i;
! for(i = 0; i < 6; i++) {
! unsigned char num;
!
! if((*str == '.') || (*str == ':'))
! str++;
! num = str2hexnum(*str++) << 4;
! num |= (str2hexnum(*str++));
! ea[i] = num;
! }
! }
!
! int get_ethernet_addr(char *ethernet_addr)
{
+ int i;
+ char *ethaddr_str;
+
+ ethaddr_str = prom_getenv("ethaddr");
+ if (!ethaddr_str) {
+ printk("ethaddr not set in boot prom\n");
+ return -1;
+ }
+ str2eaddr(ethernet_addr, ethaddr_str);
+
+ #if 0
+ printk("get_ethernet_addr: ");
+ for (i=0; i<5; i++)
+ printk("%02x:", (unsigned char)*(ethernet_addr+i));
+ printk("%02x\n", *(ethernet_addr+i));
+ #endif
+
+ return 0;
}
+
+ void prom_free_prom_memory (void) {}
Index: reset.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/au1000/common/reset.c,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -C2 -d -r1.1.1.1 -r1.2
*** reset.c 2001/06/22 02:29:31 1.1.1.1
--- reset.c 2001/08/28 07:23:54 1.2
***************
*** 37,43 ****
#include <asm/system.h>
void au1000_restart(char *command)
{
! set_cp0_status(ST0_BEV | ST0_ERL);
set_cp0_config(CONF_CM_UNCACHED);
flush_cache_all();
--- 37,45 ----
#include <asm/system.h>
+ extern int au_sleep(void);
+
void au1000_restart(char *command)
{
! set_cp0_status((ST0_BEV | ST0_ERL));
set_cp0_config(CONF_CM_UNCACHED);
flush_cache_all();
***************
*** 49,56 ****
--- 51,66 ----
{
printk(KERN_NOTICE "\n** You can safely turn off the power\n");
+ #ifdef CONFIG_PM
+ au_sleep();
+
+ /* should not get here */
+ printk(KERN_ERR "Unable to put cpu in sleep mode\n");
+ while(1);
+ #else
while (1)
__asm__(".set\tmips3\n\t"
"wait\n\t"
".set\tmips0");
+ #endif
}
Index: serial.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/au1000/common/serial.c,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -C2 -d -r1.1.1.1 -r1.2
*** serial.c 2001/06/22 02:29:32 1.1.1.1
--- serial.c 2001/08/28 07:23:54 1.2
***************
*** 135,139 ****
static struct timer_list serial_timer;
! extern unsigned long get_au1000_uart_baud(void);
/* serial subtype definitions */
--- 135,139 ----
static struct timer_list serial_timer;
! extern unsigned long get_au1000_uart_baud_base(void);
/* serial subtype definitions */
***************
*** 756,759 ****
--- 756,760 ----
if (inl(UART_MOD_CNTRL + state->port) != 0x3) {
outl(3, UART_MOD_CNTRL + state->port);
+ au_sync_delay(10);
}
#ifdef SERIAL_DEBUG_OPEN
***************
*** 990,993 ****
--- 991,996 ----
info->flags &= ~ASYNC_INITIALIZED;
+ outl(0, UART_MOD_CNTRL + state->port);
+ au_sync_delay(10);
restore_flags(flags);
}
***************
*** 1041,1045 ****
baud = 9600; /* B0 transition handled in rs_set_termios */
}
! baud_base = info->state->baud_base;
//if (baud == 38400 &&
if (((info->flags & ASYNC_SPD_MASK) == ASYNC_SPD_CUST)) {
--- 1044,1049 ----
baud = 9600; /* B0 transition handled in rs_set_termios */
}
! baud_base = get_au1000_uart_baud_base();
!
//if (baud == 38400 &&
if (((info->flags & ASYNC_SPD_MASK) == ASYNC_SPD_CUST)) {
***************
*** 2515,2518 ****
--- 2519,2523 ----
if (inl(UART_MOD_CNTRL + state->port) != 0x3) {
outl(3, UART_MOD_CNTRL + state->port);
+ au_sync_delay(10);
}
***************
*** 2545,2548 ****
--- 2550,2556 ----
(void)serial_in(info, UART_RX);
serial_outp(info, UART_IER, 0);
+
+ outl(0, UART_MOD_CNTRL + state->port);
+ au_sync_delay(10);
restore_flags(flags);
***************
*** 2652,2656 ****
for (i = 0, state = rs_table; i < NR_PORTS; i++,state++) {
! state->baud_base = get_au1000_uart_baud();
state->magic = SSTATE_MAGIC;
state->line = i;
--- 2660,2664 ----
for (i = 0, state = rs_table; i < NR_PORTS; i++,state++) {
! state->baud_base = get_au1000_uart_baud_base();
state->magic = SSTATE_MAGIC;
state->line = i;
***************
*** 3048,3052 ****
info->iomem_base = state->iomem_base;
info->iomem_reg_shift = state->iomem_reg_shift;
! state->baud_base = get_au1000_uart_baud();
quot = state->baud_base / baud;
--- 3056,3060 ----
info->iomem_base = state->iomem_base;
info->iomem_reg_shift = state->iomem_reg_shift;
! state->baud_base = get_au1000_uart_baud_base();
quot = state->baud_base / baud;
Index: time.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/au1000/common/time.c,v
retrieving revision 1.4
retrieving revision 1.5
diff -C2 -d -r1.4 -r1.5
*** time.c 2001/08/25 02:19:27 1.4
--- time.c 2001/08/28 07:23:54 1.5
***************
*** 1,3 ****
--- 1,4 ----
/*
+ *
* Copyright (C) 2001 MontaVista Software, pp...@mv...
* Copied and modified Carsten Langgaard's time.c
***************
*** 24,28 ****
--- 25,31 ----
*
* Setting up the clock on the MIPS boards.
+ *
*/
+
#include <linux/config.h>
#include <linux/init.h>
***************
*** 39,45 ****
#include <linux/timex.h>
extern volatile unsigned long wall_jiffies;
unsigned long missed_heart_beats = 0;
- unsigned long uart_baud_base;
static unsigned long r4k_offset; /* Amount to increment compare reg each time */
--- 42,51 ----
#include <linux/timex.h>
+ extern void startup_match20_interrupt(void);
+ extern void set_au1000_uart_baud_base(unsigned long new_baud_base);
+ extern void set_au1000_speed(unsigned int new_freq);
+
extern volatile unsigned long wall_jiffies;
unsigned long missed_heart_beats = 0;
static unsigned long r4k_offset; /* Amount to increment compare reg each time */
***************
*** 47,56 ****
extern rwlock_t xtime_lock;
- unsigned int au1000_clock;
-
/* Cycle counter value at the previous timer interrupt.. */
static unsigned int timerhi = 0, timerlo = 0;
! #define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
static inline void ack_r4ktimer(unsigned long newval)
--- 53,64 ----
extern rwlock_t xtime_lock;
/* Cycle counter value at the previous timer interrupt.. */
static unsigned int timerhi = 0, timerlo = 0;
! #ifdef CONFIG_PM
! #define MATCH20_INC 328
! extern void startup_match20_interrupt(void);
! static unsigned long last_pc0, last_match20;
! #endif
static inline void ack_r4ktimer(unsigned long newval)
***************
*** 59,63 ****
}
-
/*
* There are a lot of conceptually broken versions of the MIPS timer interrupt
--- 67,70 ----
***************
*** 68,72 ****
void mips_timer_interrupt(struct pt_regs *regs)
{
! int irq = 7;
if (r4k_offset == 0)
--- 75,86 ----
void mips_timer_interrupt(struct pt_regs *regs)
{
! int irq = 63;
! unsigned long count;
!
! #ifdef CONFIG_PM
! printk(KERN_ERR "Unexpected CP0 interrupt\n");
! regs->cp0_status &= ~IE_IRQ5; /* disable CP0 interrupt */
! return;
! #endif
if (r4k_offset == 0)
***************
*** 74,77 ****
--- 88,95 ----
do {
+ count = read_32bit_cp0_register(CP0_COUNT);
+ timerhi += (count < timerlo); /* Wrap around */
+ timerlo = count;
+
kstat.irqs[0][irq]++;
do_timer(regs);
***************
*** 88,91 ****
--- 106,154 ----
}
+ #ifdef CONFIG_PM
+ void counter0_irq(int irq, void *dev_id, struct pt_regs *regs)
+ {
+ unsigned long pc0;
+ int time_elapsed;
+ static int jiffie_drift = 0;
+
+ kstat.irqs[0][irq]++;
+ if (readl(PC_COUNTER_CNTRL) & PC_CNTRL_M20) {
+ /* should never happen! */
+ printk(KERN_WARNING "counter 0 w status eror\n");
+ return;
+ }
+
+ pc0 = inl(PC0_COUNTER_READ);
+ if (pc0 < last_match20) {
+ /* counter overflowed */
+ time_elapsed = (0xffffffff - last_match20) + pc0;
+ }
+ else {
+ time_elapsed = pc0 - last_match20;
+ }
+
+ while (time_elapsed > 0) {
+ do_timer(regs);
+ time_elapsed -= MATCH20_INC;
+ last_match20 += MATCH20_INC;
+ jiffie_drift++;
+ }
+
+ last_pc0 = pc0;
+ outl(last_match20 + MATCH20_INC, PC0_MATCH2);
+ au_sync();
+
+ /* our counter ticks at 10.009765625 ms/tick, we we're running
+ * almost 10uS too slow per tick.
+ */
+
+ if (jiffie_drift >= 999) {
+ jiffie_drift -= 999;
+ do_timer(regs); /* increment jiffies by one */
+ }
+ }
+ #endif
+
/*
* Figure out the r4k offset, the amount to increment the compare
***************
*** 96,105 ****
{
unsigned long count;
- unsigned long cpu_pll;
unsigned long cpu_speed;
unsigned long start, end;
unsigned long counter;
- int i;
int trim_divide = 16;
counter = inl(PC_COUNTER_CNTRL);
--- 159,169 ----
{
unsigned long count;
unsigned long cpu_speed;
unsigned long start, end;
unsigned long counter;
int trim_divide = 16;
+ unsigned long flags;
+
+ save_and_cli(flags);
counter = inl(PC_COUNTER_CNTRL);
***************
*** 127,142 ****
count = read_32bit_cp0_register(CP0_COUNT);
cpu_speed = count * 2;
! uart_baud_base = (((cpu_speed) / 4) / 16);
return (cpu_speed / HZ);
}
- static unsigned long __init get_mips_time(void)
- {
- return inl(PC0_COUNTER_READ);
- }
void __init time_init(void)
{
! unsigned int est_freq, flags;
printk("calculating r4koff... ");
--- 191,203 ----
count = read_32bit_cp0_register(CP0_COUNT);
cpu_speed = count * 2;
! set_au1000_uart_baud_base(((cpu_speed) / 4) / 16);
! restore_flags(flags);
return (cpu_speed / HZ);
}
void __init time_init(void)
{
! unsigned int est_freq;
printk("calculating r4koff... ");
***************
*** 150,174 ****
printk("CPU frequency %d.%02d MHz\n", est_freq/1000000,
(est_freq%1000000)*100/1000000);
! au1000_clock = est_freq;
r4k_cur = (read_32bit_cp0_register(CP0_COUNT) + r4k_offset);
write_32bit_cp0_register(CP0_COMPARE, r4k_cur);
- set_cp0_status(ALLINTS);
! /* Read time from the RTC chipset. */
! write_lock_irqsave (&xtime_lock, flags);
! xtime.tv_sec = get_mips_time();
xtime.tv_usec = 0;
! write_unlock_irqrestore(&xtime_lock, flags);
}
/* This is for machines which generate the exact clock. */
#define USECS_PER_JIFFY (1000000/HZ)
! #define USECS_PER_JIFFY_FRAC ((1000000ULL << 32) / HZ & 0xffffffff)
- /* Cycle counter value at the previous timer interrupt.. */
- static unsigned int timerhi = 0, timerlo = 0;
-
static unsigned long
div64_32(unsigned long v1, unsigned long v2, unsigned long v3)
--- 211,259 ----
printk("CPU frequency %d.%02d MHz\n", est_freq/1000000,
(est_freq%1000000)*100/1000000);
! set_au1000_speed(est_freq);
r4k_cur = (read_32bit_cp0_register(CP0_COUNT) + r4k_offset);
write_32bit_cp0_register(CP0_COMPARE, r4k_cur);
! /* no RTC on the pb1000 */
! xtime.tv_sec = 0;
xtime.tv_usec = 0;
!
! #ifdef CONFIG_PM
! /*
! * setup counter 0, since it keeps ticking after a
! * 'wait' instruction has been executed. The CP0 timer and
! * counter 1 do NOT continue running after 'wait'
! *
! * It's too early to call request_irq() here, so we handle
! * counter 0 interrupt as a special irq and it doesn't show
! * up under /proc/interrupts.
! */
! while (readl(PC_COUNTER_CNTRL) & PC_CNTRL_C0S);
! writel(0, PC0_COUNTER_WRITE);
! while (readl(PC_COUNTER_CNTRL) & PC_CNTRL_C0S);
!
! writel(readl(PM_WAKEUP_SOURCE_MASK) | (1<<8), PM_WAKEUP_SOURCE_MASK);
! writel(~0, PM_WAKEUP_CAUSE);
! au_sync();
! while (readl(PC_COUNTER_CNTRL) & PC_CNTRL_M20);
!
! /* setup match20 to interrupt once every 10ms */
! last_pc0 = last_match20 = readl(PC0_COUNTER_READ);
! writel(last_match20 + MATCH20_INC, PC0_MATCH2);
! au_sync();
! while (readl(PC_COUNTER_CNTRL) & PC_CNTRL_M20);
! startup_match20_interrupt();
! #endif
!
! //set_cp0_status(ALLINTS);
! au_sync();
}
/* This is for machines which generate the exact clock. */
#define USECS_PER_JIFFY (1000000/HZ)
! #define USECS_PER_JIFFY_FRAC (0x100000000*1000000/HZ&0xffffffff)
static unsigned long
div64_32(unsigned long v1, unsigned long v2, unsigned long v3)
***************
*** 180,188 ****
- /*
- * FIXME: Does playing with the RP bit in c0_status interfere with this code?
- */
static unsigned long do_fast_gettimeoffset(void)
{
u32 count;
unsigned long res, tmp;
--- 265,290 ----
static unsigned long do_fast_gettimeoffset(void)
{
+ #ifdef CONFIG_PM
+ unsigned long pc0;
+ unsigned long offset;
+
+ pc0 = readl(PC0_COUNTER_READ);
+ if (pc0 < last_pc0) {
+ offset = 0xffffffff - last_pc0 + pc0;
+ printk("offset over: %x\n", (unsigned)offset);
+ }
+ else {
+ offset = (unsigned long)(((pc0 - last_pc0) * 305) / 10);
+ }
+ if ((pc0-last_pc0) > 2*MATCH20_INC) {
+ printk("huge offset %x, last_pc0 %x last_match20 %x pc0 %x\n",
+ (unsigned)offset, (unsigned)last_pc0,
+ (unsigned)last_match20, (unsigned)pc0);
+ }
+ au_sync();
+ return offset;
+ #else
u32 count;
unsigned long res, tmp;
***************
*** 232,235 ****
--- 334,338 ----
return res;
+ #endif
}
***************
*** 280,292 ****
write_unlock_irq (&xtime_lock);
- }
-
- /*
- * The UART baud base is not known at compile time ... if
- * we want to be able to use the same code on different
- * speed CPUs.
- */
- unsigned long get_au1000_uart_baud()
- {
- return uart_baud_base;
}
--- 383,385 ----
|
|
From: Pete P. <pp...@us...> - 2001-08-28 07:23:57
|
Update of /cvsroot/linux-mips/linux/arch/mips/configs In directory usw-pr-cvs1:/tmp/cvs-serv14591/arch/mips/configs Modified Files: defconfig-pb1000 Log Message: Added preliminary power management supuport: * turn off the clocks to the uarts when not used * turn off the clocks to the ethernets when not used * adhoc /proc interface for putting the cpu to sleep and dynamically scaling the cpu frequency. * fixed a pci compile problem Index: defconfig-pb1000 =================================================================== RCS file: /cvsroot/linux-mips/linux/arch/mips/configs/defconfig-pb1000,v retrieving revision 1.4 retrieving revision 1.5 diff -C2 -d -r1.4 -r1.5 *** defconfig-pb1000 2001/08/22 18:18:13 1.4 --- defconfig-pb1000 2001/08/28 07:23:54 1.5 *************** *** 16,21 **** --- 16,25 ---- # CONFIG_ALGOR_P4032 is not set # CONFIG_BAGET_MIPS is not set + # CONFIG_COBALT_MICRO_SERVER is not set # CONFIG_DECSTATION is not set # CONFIG_DDB5074 is not set + # CONFIG_NEC_OSPREY is not set + # CONFIG_NEC_EAGLE is not set + # CONFIG_NEC_KORVA is not set # CONFIG_MIPS_EV96100 is not set # CONFIG_MIPS_EV64120 is not set *************** *** 23,26 **** --- 27,31 ---- # CONFIG_MIPS_MALTA is not set # CONFIG_NINO is not set + # CONFIG_PS2 is not set # CONFIG_MIPS_MAGNUM_4000 is not set # CONFIG_MOMENCO_OCELOT is not set *************** *** 39,45 **** CONFIG_MIPS_AU1000=y CONFIG_NEW_IRQ=y # CONFIG_ISA is not set # CONFIG_EISA is not set - # CONFIG_PCI is not set # CONFIG_I8259 is not set --- 44,53 ---- CONFIG_MIPS_AU1000=y CONFIG_NEW_IRQ=y + CONFIG_PCI=y + CONFIG_PC_KEYB=y + CONFIG_NEW_PCI=y + CONFIG_PCI_AUTO=y # CONFIG_ISA is not set # CONFIG_EISA is not set # CONFIG_I8259 is not set *************** *** 47,51 **** # Loadable module support # ! # CONFIG_MODULES is not set # --- 55,61 ---- # Loadable module support # ! CONFIG_MODULES=y ! # CONFIG_MODVERSIONS is not set ! CONFIG_KMOD=y # *************** *** 59,62 **** --- 69,73 ---- # CONFIG_CPU_R5000 is not set # CONFIG_CPU_R5432 is not set + # CONFIG_CPU_R5900 is not set # CONFIG_CPU_RM7000 is not set # CONFIG_CPU_NEVADA is not set *************** *** 79,83 **** --- 90,96 ---- CONFIG_BINFMT_ELF=y # CONFIG_BINFMT_MISC is not set + CONFIG_PM=y CONFIG_NET=y + CONFIG_PCI_NAMES=y # CONFIG_HOTPLUG is not set # CONFIG_PCMCIA is not set *************** *** 188,191 **** --- 201,205 ---- # # CONFIG_I2O is not set + # CONFIG_I2O_PCI is not set # CONFIG_I2O_BLOCK is not set # CONFIG_I2O_LAN is not set *************** *** 214,217 **** --- 228,232 ---- CONFIG_MIPS_AU1000_ENET=y # CONFIG_SUNLANCE is not set + # CONFIG_HAPPYMEAL is not set # CONFIG_SUNBMAC is not set # CONFIG_SUNQE is not set *************** *** 222,225 **** --- 237,241 ---- # CONFIG_NET_VENDOR_SMC is not set # CONFIG_NET_VENDOR_RACAL is not set + # CONFIG_HP100 is not set # CONFIG_NET_ISA is not set # CONFIG_NET_PCI is not set *************** *** 231,234 **** --- 247,251 ---- # CONFIG_ACENIC is not set # CONFIG_ACENIC_OMIT_TIGON_I is not set + # CONFIG_DL2K is not set # CONFIG_MYRI_SBUS is not set # CONFIG_HAMACHI is not set *************** *** 282,286 **** # Character devices # ! # CONFIG_VT is not set # CONFIG_SERIAL is not set # CONFIG_SERIAL_EXTENDED is not set --- 299,304 ---- # Character devices # ! CONFIG_VT=y ! CONFIG_VT_CONSOLE=y # CONFIG_SERIAL is not set # CONFIG_SERIAL_EXTENDED is not set *************** *** 294,297 **** --- 312,318 ---- # CONFIG_MOXA_INTELLIO is not set # CONFIG_MOXA_SMARTIO is not set + # CONFIG_ISI is not set + # CONFIG_SYNCLINK is not set + # CONFIG_N_HDLC is not set # CONFIG_RISCOM8 is not set # CONFIG_SPECIALIX is not set *************** *** 337,340 **** --- 358,362 ---- # CONFIG_R3964 is not set # CONFIG_APPLICOM is not set + # CONFIG_SONYPI is not set # *************** *** 369,372 **** --- 391,395 ---- # CONFIG_EFS_FS is not set # CONFIG_JFFS_FS is not set + # CONFIG_JFFS2_FS is not set # CONFIG_CRAMFS is not set # CONFIG_TMPFS is not set *************** *** 430,433 **** --- 453,457 ---- # CONFIG_SOLARIS_X86_PARTITION is not set # CONFIG_UNIXWARE_DISKLABEL is not set + # CONFIG_LDM_PARTITION is not set CONFIG_SGI_PARTITION=y # CONFIG_ULTRIX_PARTITION is not set *************** *** 435,438 **** --- 459,513 ---- # CONFIG_SMB_NLS is not set # CONFIG_NLS is not set + + # + # Console drivers + # + # CONFIG_VGA_CONSOLE is not set + # CONFIG_MDA_CONSOLE is not set + + # + # Frame-buffer support + # + CONFIG_FB=y + CONFIG_DUMMY_CONSOLE=y + # CONFIG_FB_RIVA is not set + # CONFIG_FB_CLGEN is not set + # CONFIG_FB_PM2 is not set + # CONFIG_FB_CYBER2000 is not set + # CONFIG_FB_E1355 is not set + # CONFIG_FB_PVR2 is not set + # CONFIG_FB_PVR2_DEBUG is not set + # CONFIG_FB_MQ200 is not set + # CONFIG_FB_MATROX is not set + # CONFIG_FB_ATY is not set + # CONFIG_FB_ATY128 is not set + # CONFIG_FB_3DFX is not set + # CONFIG_FB_SIS is not set + CONFIG_FB_E1356=y + # CONFIG_PB1000_CRT is not set + # CONFIG_PB1000_NTSC is not set + # CONFIG_PB1000_TFT is not set + # CONFIG_FB_VIRTUAL is not set + CONFIG_FBCON_ADVANCED=y + # CONFIG_FBCON_MFB is not set + # CONFIG_FBCON_CFB2 is not set + # CONFIG_FBCON_CFB4 is not set + CONFIG_FBCON_CFB8=y + CONFIG_FBCON_CFB16=y + # CONFIG_FBCON_CFB24 is not set + # CONFIG_FBCON_CFB32 is not set + # CONFIG_FBCON_AFB is not set + # CONFIG_FBCON_ILBM is not set + # CONFIG_FBCON_IPLAN2P2 is not set + # CONFIG_FBCON_IPLAN2P4 is not set + # CONFIG_FBCON_IPLAN2P8 is not set + # CONFIG_FBCON_MAC is not set + # CONFIG_FBCON_VGA_PLANES is not set + # CONFIG_FBCON_VGA is not set + # CONFIG_FBCON_HGA is not set + # CONFIG_FBCON_FONTWIDTH8_ONLY is not set + # CONFIG_FBCON_FONTS is not set + CONFIG_FONT_8x8=y + CONFIG_FONT_8x16=y # |
|
From: Pete P. <pp...@us...> - 2001-08-28 07:23:57
|
Update of /cvsroot/linux-mips/linux/arch/mips/kernel
In directory usw-pr-cvs1:/tmp/cvs-serv14591/arch/mips/kernel
Modified Files:
pci.c
Log Message:
Added preliminary power management supuport:
* turn off the clocks to the uarts when not used
* turn off the clocks to the ethernets when not used
* adhoc /proc interface for putting the cpu to sleep and
dynamically scaling the cpu frequency.
* fixed a pci compile problem
Index: pci.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/kernel/pci.c,v
retrieving revision 1.2
retrieving revision 1.3
diff -C2 -d -r1.2 -r1.3
*** pci.c 2001/08/23 23:39:51 1.2
--- pci.c 2001/08/28 07:23:54 1.3
***************
*** 173,174 ****
--- 173,179 ----
/* this should not be called */
}
+
+ unsigned int pcibios_assign_all_busses(void)
+ {
+ return 1;
+ }
|
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