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From: James S. <jsi...@us...> - 2001-11-26 19:26:08
|
Update of /cvsroot/linux-mips/linux/include/asm-mips In directory usw-pr-cvs1:/tmp/cvs-serv26593 Added Files: addrspace.h Log Message: Add some of the old stuff formerly in include/asm-mips/sibyte/sbmips.h. |
|
From: James S. <jsi...@us...> - 2001-11-26 19:25:14
|
Update of /cvsroot/linux-mips/linux/include/asm-mips/sibyte In directory usw-pr-cvs1:/tmp/cvs-serv26259 Removed Files: sbmips.h Log Message: Replication of information considered problematic ... --- sbmips.h DELETED --- |
|
From: James S. <jsi...@us...> - 2001-11-26 19:24:14
|
Update of /cvsroot/linux-mips/linux/arch/mips/philips/nino
In directory usw-pr-cvs1:/tmp/cvs-serv25829
Modified Files:
Makefile TODO irq.c prom.c setup.c
Log Message:
Your daily jolt of Nino updates.
Index: Makefile
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/philips/nino/Makefile,v
retrieving revision 1.8
retrieving revision 1.9
diff -u -d -r1.8 -r1.9
--- Makefile 2001/11/13 17:10:09 1.8
+++ Makefile 2001/11/26 19:24:11 1.9
@@ -11,11 +11,11 @@
.S.o:
$(CC) $(AFLAGS) -c $< -o $@
-O_TARGET := nino.o
+O_TARGET := nino.o
all: nino.o
-obj-y := int-handler.o irq.o setup.o prom.o power.o
+obj-y := int-handler.o irq.o setup.o prom.o power.o
int-handler.o: int-handler.S
Index: TODO
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/philips/nino/TODO,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- TODO 2001/11/13 17:10:09 1.1
+++ TODO 2001/11/26 19:24:11 1.2
@@ -13,5 +13,6 @@
and see what all the different IO pins are hooked to
- KGDB
* get stub working
-- SERIAL
- * complete rewrite and use only one interrupt instead of two
+- MMU
+ * Use CONFIG_CPU_TX39XX instead of current CONFIG_CPU_R3000 and
+ start using 3912 specific MMU management.
Index: irq.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/philips/nino/irq.c,v
retrieving revision 1.7
retrieving revision 1.8
diff -u -d -r1.7 -r1.8
--- irq.c 2001/11/06 20:23:54 1.7
+++ irq.c 2001/11/26 19:24:11 1.8
@@ -13,17 +13,30 @@
#include <linux/sched.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
+#include <asm/io.h>
#include <asm/irq.h>
#include <asm/mipsregs.h>
#include <asm/tx3912.h>
+#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
+
extern asmlinkage void do_IRQ(int irq, struct pt_regs *regs);
static void enable_irq6(unsigned int irq)
{
if(irq == 0) {
- IntEnable5 |= INT5_PERIODICINT;
- IntEnable6 |= INT6_PERIODICINT;
+ outl(inl(TX3912_INT6_ENABLE) |
+ TX3912_INT6_ENABLE_PRIORITYMASK_PERINT,
+ TX3912_INT6_ENABLE);
+ outl(inl(TX3912_INT5_ENABLE) | TX3912_INT5_PERINT,
+ TX3912_INT5_ENABLE);
+ }
+ if(irq == 3) {
+ outl(inl(TX3912_INT6_ENABLE) |
+ TX3912_INT6_ENABLE_PRIORITYMASK_UARTARXINT,
+ TX3912_INT6_ENABLE);
+ outl(inl(TX3912_INT2_ENABLE) | TX3912_INT2_UARTA_RX_BITS,
+ TX3912_INT2_ENABLE);
}
}
@@ -37,9 +50,20 @@
static void disable_irq6(unsigned int irq)
{
if(irq == 0) {
- IntEnable6 &= ~INT6_PERIODICINT;
- IntClear5 |= INT5_PERIODICINT;
- IntClear6 |= INT6_PERIODICINT;
+ outl(inl(TX3912_INT6_ENABLE) &
+ ~TX3912_INT6_ENABLE_PRIORITYMASK_PERINT,
+ TX3912_INT6_ENABLE);
+ outl(inl(TX3912_INT5_ENABLE) & ~TX3912_INT5_PERINT,
+ TX3912_INT5_ENABLE);
+ outl(inl(TX3912_INT5_CLEAR) | TX3912_INT5_PERINT,
+ TX3912_INT5_CLEAR);
+ }
+ if(irq == 3) {
+ outl(inl(TX3912_INT6_ENABLE) &
+ ~TX3912_INT6_ENABLE_PRIORITYMASK_UARTARXINT,
+ TX3912_INT6_ENABLE);
+ outl(inl(TX3912_INT2_ENABLE) & ~TX3912_INT2_UARTA_RX_BITS,
+ TX3912_INT2_ENABLE);
}
}
@@ -67,29 +91,35 @@
{
int irq = -1;
- if(IntStatus6 & INT6_PERIODICINT) {
+ if((inl(TX3912_INT6_STATUS) & TX3912_INT6_STATUS_INTVEC_UARTARXINT) ==
+ TX3912_INT6_STATUS_INTVEC_UARTARXINT) {
+ irq = 3;
+ goto done;
+ }
+ if((inl(TX3912_INT6_STATUS) & TX3912_INT6_STATUS_INTVEC_PERINT) ==
+ TX3912_INT6_STATUS_INTVEC_PERINT) {
irq = 0;
goto done;
}
- /* if irq == -1, then the interrupt has already been cleared */
+ /* if irq == -1, then interrupt was cleared or is invalid */
if(irq == -1) {
- panic("No handler installed for MIPS IRQ6\n");
+ panic("Unhandled High Priority PR31700 Interrupt = 0x%08x\n",
+ inl(TX3912_INT6_STATUS));
}
done:
do_IRQ(irq, regs);
-
-end:
- return;
}
static void enable_irq4(unsigned int irq)
{
set_cp0_status(STATUSF_IP4);
if(irq == 2) {
- IntClear2 = 0xffffffff;
- IntEnable2 |= 0x07c00000;
+ outl(inl(TX3912_INT2_CLEAR) | TX3912_INT2_UARTA_TX_BITS,
+ TX3912_INT2_CLEAR);
+ outl(inl(TX3912_INT2_ENABLE) | TX3912_INT2_UARTA_TX_BITS,
+ TX3912_INT2_ENABLE);
}
}
@@ -129,31 +159,38 @@
{
int irq = -1;
- if(IntStatus2 & 0x07c00000) {
+ if(inl(TX3912_INT2_STATUS) & TX3912_INT2_UARTA_TX_BITS) {
irq = 2;
goto done;
}
- /* if irq == -1, then the interrupt has already been cleared */
+ /* if irq == -1, then interrupt was cleared or is invalid */
if (irq == -1) {
- panic("No handler installed for MIPS IRQ4\n");
+ printk("PR31700 Interrupt Status Register 1 = 0x%08x\n",
+ inl(TX3912_INT1_STATUS));
+ printk("PR31700 Interrupt Status Register 2 = 0x%08x\n",
+ inl(TX3912_INT2_STATUS));
+ printk("PR31700 Interrupt Status Register 3 = 0x%08x\n",
+ inl(TX3912_INT3_STATUS));
+ printk("PR31700 Interrupt Status Register 4 = 0x%08x\n",
+ inl(TX3912_INT4_STATUS));
+ printk("PR31700 Interrupt Status Register 5 = 0x%08x\n",
+ inl(TX3912_INT5_STATUS));
+ panic("Unhandled Low Priority PR31700 Interrupt\n");
}
done:
do_IRQ(irq, regs);
-
-end:
return;
}
void irq_bad(struct pt_regs *regs)
{
/* This should never happen */
- printk("Stray interrupt, spinning...\n");
printk(" CAUSE register = 0x%08lx\n", regs->cp0_cause);
printk("STATUS register = 0x%08lx\n", regs->cp0_status);
printk(" EPC register = 0x%08lx\n", regs->cp0_epc);
- while(1);
+ panic("Stray interrupt, spinning...\n");
}
void __init nino_irq_setup(void)
@@ -166,19 +203,23 @@
/* Disable all hardware interrupts */
change_cp0_status(ST0_IM, 0x00);
- /* Clear any pending interrupts */
- IntClear1 = 0xffffffff;
- IntClear2 = 0xffffffff;
- IntClear3 = 0xffffffff;
- IntClear4 = 0xffffffff;
- IntClear5 = 0xffffffff;
+ /* Clear interrupts */
+ outl(0xffffffff, TX3912_INT1_CLEAR);
+ outl(0xffffffff, TX3912_INT2_CLEAR);
+ outl(0xffffffff, TX3912_INT3_CLEAR);
+ outl(0xffffffff, TX3912_INT4_CLEAR);
+ outl(0xffffffff, TX3912_INT5_CLEAR);
- /* FIXME: disable interrupts 1,3,4 */
- IntEnable1 = 0x00000000;
- IntEnable2 = 0xfffff000;
- IntEnable3 = 0x00000000;
- IntEnable4 = 0x00000000;
- IntEnable5 = 0xffffffff;
+ /*
+ * Disable all PR31700 interrupts. We let the various
+ * device drivers in the system register themselves
+ * and set the proper hardware bits.
+ */
+ outl(0x00000000, TX3912_INT1_ENABLE);
+ outl(0x00000000, TX3912_INT2_ENABLE);
+ outl(0x00000000, TX3912_INT3_ENABLE);
+ outl(0x00000000, TX3912_INT4_ENABLE);
+ outl(0x00000000, TX3912_INT5_ENABLE);
/* Initialize IRQ vector table */
init_generic_irq();
@@ -188,10 +229,8 @@
hw_irq_controller *handler = NULL;
if (i == 0 || i == 3)
handler = &irq6_type;
- else if (i == 2)
- handler = &irq4_type;
else
- handler = NULL;
+ handler = &irq4_type;
irq_desc[i].status = IRQ_DISABLED;
irq_desc[i].action = 0;
@@ -203,7 +242,8 @@
set_except_vector(0, ninoIRQ);
/* Enable high priority interrupts */
- IntEnable6 = (INT6_GLOBALEN | 0xffff);
+ outl(TX3912_INT6_ENABLE_GLOBALEN | TX3912_INT6_ENABLE_HIGH_PRIORITY,
+ TX3912_INT6_ENABLE);
/* Enable all interrupts */
change_cp0_status(ST0_IM, ALLINTS);
Index: prom.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/philips/nino/prom.c,v
retrieving revision 1.6
retrieving revision 1.7
diff -u -d -r1.6 -r1.7
--- prom.c 2001/11/13 17:10:09 1.6
+++ prom.c 2001/11/26 19:24:11 1.7
@@ -26,8 +26,7 @@
#endif
/* Do basic initialization */
-void __init prom_init(int argc, char **argv,
- unsigned long magic, int *prom_vec)
+void __init prom_init(int argc, char **argv, unsigned long magic, int *prom_vec)
{
unsigned long mem_size;
Index: setup.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/philips/nino/setup.c,v
retrieving revision 1.7
retrieving revision 1.8
diff -u -d -r1.7 -r1.8
--- setup.c 2001/11/13 17:10:09 1.7
+++ setup.c 2001/11/26 19:24:11 1.8
@@ -42,7 +42,21 @@
static void __init nino_board_init()
{
- /* Nothing for now */
+ /*
+ * Set up the master clock module. The value set in
+ * the Clock Control Register by WindowsCE is 0x00432ba.
+ * We set a few values here and let the device drivers
+ * handle the rest.
+ *
+ * NOTE: The UART clocks must be enabled here to provide
+ * enough time for them to settle.
+ */
+ outl(0x00000000, TX3912_CLK_CTRL);
+ outl((TX3912_CLK_CTRL_SIBMCLKDIR | TX3912_CLK_CTRL_SIBMCLKDIV_2 |
+ TX3912_CLK_CTRL_ENSIBMCLK | TX3912_CLK_CTRL_CSERSEL |
+ TX3912_CLK_CTRL_CSERDIV_3 | TX3912_CLK_CTRL_ENCSERCLK |
+ TX3912_CLK_CTRL_ENUARTACLK | TX3912_CLK_CTRL_ENUARTBCLK),
+ TX3912_CLK_CTRL);
}
static __init void nino_time_init(void)
@@ -51,7 +65,7 @@
outl(TX3912_SYS_TIMER_VALUE, TX3912_TIMER_PERIOD);
outl(TX3912_TIMER_CTRL_ENPERTIMER, TX3912_TIMER_CTRL);
- /* Enable the timer clock line */
+ /* Enable the master timer clock */
outl(inl(TX3912_CLK_CTRL) | TX3912_CLK_CTRL_ENTIMERCLK,
TX3912_CLK_CTRL);
@@ -72,7 +86,7 @@
extern void nino_wait(void);
irq_setup = nino_irq_setup;
- mips_io_port_base = KSEG1ADDR(0x10c00000);
+ set_io_port_base(KSEG1ADDR(0x10c00000));
_machine_restart = nino_machine_restart;
_machine_halt = nino_machine_halt;
|
|
From: James S. <jsi...@us...> - 2001-11-26 19:19:56
|
Update of /cvsroot/linux-mips/linux/arch/mips/dec In directory usw-pr-cvs1:/tmp/cvs-serv24686 Added Files: int-handler.S setup.c Log Message: Dec station updates. |
|
From: James S. <jsi...@us...> - 2001-11-26 19:18:15
|
Update of /cvsroot/linux-mips/linux/arch/mips/mm
In directory usw-pr-cvs1:/tmp/cvs-serv24224/mm
Modified Files:
c-andes.c c-r3k.c
Log Message:
ake flush_cache_all() an empty function for the R3000.
Index: c-andes.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/mm/c-andes.c,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- c-andes.c 2001/10/23 17:20:14 1.1
+++ c-andes.c 2001/11/26 19:18:13 1.2
@@ -70,6 +70,12 @@
}
}
+static void andes___flush_cache_all(void)
+{
+ andes_flush_cache_l1();
+ andes_flush_cache_l2();
+}
+
void
andes_flush_icache_page(unsigned long page)
{
@@ -101,6 +107,7 @@
_copy_page = andes_copy_page;
_flush_cache_all = andes_flush_cache_all;
+ ___flush_cache_all = andes___flush_cache_all;
_flush_cache_mm = andes_flush_cache_mm;
_flush_cache_page = andes_flush_cache_page;
_flush_page_to_ram = andes_flush_page_to_ram;
Index: c-r3k.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/mm/c-r3k.c,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -d -r1.2 -r1.3
--- c-r3k.c 2001/10/30 17:46:57 1.2
+++ c-r3k.c 2001/11/26 19:18:13 1.3
@@ -232,7 +232,6 @@
static inline void r3k_flush_cache_all(void)
{
- r3k_flush_icache_range(KSEG0, KSEG0 + icache_size);
}
static inline void r3k___flush_cache_all(void)
|
|
From: James S. <jsi...@us...> - 2001-11-26 19:18:15
|
Update of /cvsroot/linux-mips/linux/arch/mips/kernel In directory usw-pr-cvs1:/tmp/cvs-serv24224/kernel Modified Files: sysmips.c Added Files: gdb-stub.c Log Message: ake flush_cache_all() an empty function for the R3000. Index: sysmips.c =================================================================== RCS file: /cvsroot/linux-mips/linux/arch/mips/kernel/sysmips.c,v retrieving revision 1.9 retrieving revision 1.10 diff -u -d -r1.9 -r1.10 --- sysmips.c 2001/10/27 20:52:05 1.9 +++ sysmips.c 2001/11/26 19:18:13 1.10 @@ -84,7 +84,7 @@ goto out; case FLUSH_CACHE: - flush_cache_all(); + __flush_cache_all(); retval = 0; goto out; |
|
From: James S. <jsi...@us...> - 2001-11-26 19:16:09
|
Update of /cvsroot/linux-mips/linux/arch/mips/mm
In directory usw-pr-cvs1:/tmp/cvs-serv23666
Modified Files:
tlb-sb1.c
Log Message:
Move initialization of tlb_entries to tlb-sb1.c. Delete lots of unused variables.
Index: tlb-sb1.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/mm/tlb-sb1.c,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -d -r1.2 -r1.3
--- tlb-sb1.c 2001/11/19 17:57:38 1.2
+++ tlb-sb1.c 2001/11/26 19:16:06 1.3
@@ -27,19 +27,7 @@
#include <asm/cpu.h>
/* These are probed at ld_mmu time */
-static unsigned int icache_size;
-static unsigned int dcache_size;
-
-static unsigned int icache_line_size;
-static unsigned int dcache_line_size;
-static unsigned int icache_index_mask;
-
-static unsigned int icache_assoc;
-static unsigned int dcache_assoc;
-
-static unsigned int icache_sets;
-static unsigned int dcache_sets;
static unsigned int tlb_entries;
/* Dump the current entry* and pagemask registers */
@@ -305,6 +293,11 @@
*/
void sb1_tlb_init(void)
{
+ u32 config1;
+
+ config1 = read_mips32_cp0_config1();
+ tlb_entries = ((config1 >> 25) & 0x3f) + 1;
+
/*
* We don't know what state the firmware left the TLB's in, so this is
* the ultra-conservative way to flush the TLB's and avoid machine
|
|
From: James S. <jsi...@us...> - 2001-11-26 19:15:06
|
Update of /cvsroot/linux-mips/linux/arch/mips/mm In directory usw-pr-cvs1:/tmp/cvs-serv23350/mm Modified Files: Makefile Log Message: Export _dma_cache_* to modules iff CONFIG_NONCOHERENT_IO is enabled. Index: Makefile =================================================================== RCS file: /cvsroot/linux-mips/linux/arch/mips/mm/Makefile,v retrieving revision 1.10 retrieving revision 1.11 diff -u -d -r1.10 -r1.11 --- Makefile 2001/11/20 18:10:04 1.10 +++ Makefile 2001/11/26 19:15:03 1.11 @@ -13,7 +13,7 @@ O_TARGET := mm.o -export-objs += ioremap.o umap.o +export-objs += ioremap.o loadmmu.o umap.o obj-y += extable.o init.o ioremap.o fault.o loadmmu.o obj-$(CONFIG_CPU_R3000) += pg-r3k.o c-r3k.o c-tx39.o tlb-r3k.o \ |
|
From: James S. <jsi...@us...> - 2001-11-26 19:15:05
|
Update of /cvsroot/linux-mips/linux/arch/mips/kernel In directory usw-pr-cvs1:/tmp/cvs-serv23350/kernel Modified Files: mips_ksyms.c Log Message: Export _dma_cache_* to modules iff CONFIG_NONCOHERENT_IO is enabled. Index: mips_ksyms.c =================================================================== RCS file: /cvsroot/linux-mips/linux/arch/mips/kernel/mips_ksyms.c,v retrieving revision 1.4 retrieving revision 1.5 diff -u -d -r1.4 -r1.5 --- mips_ksyms.c 2001/10/17 20:28:58 1.4 +++ mips_ksyms.c 2001/11/26 19:15:03 1.5 @@ -88,8 +88,6 @@ */ EXPORT_SYMBOL(_flush_page_to_ram); EXPORT_SYMBOL(_flush_cache_all); -EXPORT_SYMBOL(_dma_cache_wback_inv); -EXPORT_SYMBOL(_dma_cache_inv); EXPORT_SYMBOL(invalid_pte_table); @@ -102,11 +100,6 @@ EXPORT_SYMBOL(__up); /* - * Base address of ports for Intel style I/O. - */ -EXPORT_SYMBOL(mips_io_port_base); - -/* * Architecture specific stuff. */ #ifdef CONFIG_MIPS_JAZZ @@ -124,9 +117,6 @@ */ #include <asm/branch.h> #include <linux/sched.h> - -int register_fpe(void (*handler)(struct pt_regs *regs, unsigned int fcr31)); -int unregister_fpe(void (*handler)(struct pt_regs *regs, unsigned int fcr31)); #ifdef CONFIG_VT EXPORT_SYMBOL(screen_info); |
|
From: James S. <jsi...@us...> - 2001-11-26 19:02:59
|
Update of /cvsroot/linux-mips/linux/drivers/sgi/char In directory usw-pr-cvs1:/tmp/cvs-serv19807 Added Files: ds1286.c Log Message: Synced to OSS tree. |
|
From: James S. <jsi...@us...> - 2001-11-26 19:02:24
|
Update of /cvsroot/linux-mips/linux/include/asm-mips
In directory usw-pr-cvs1:/tmp/cvs-serv19527/include/asm-mips
Modified Files:
pci.h
Log Message:
Reimplement ioswapping for 32-bit <asm/io.h>. Make support for non-coherent I/O on 32-bit MIPS option (CONFIG_NONCOHERENT_IO. Replace CONFIG_COHERENT_IO by CONFIG_NONCOHERENT_IO. The cobalt hacks can go away now.
Index: pci.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/pci.h,v
retrieving revision 1.7
retrieving revision 1.8
diff -u -d -r1.7 -r1.8
--- pci.h 2001/11/12 18:41:36 1.7
+++ pci.h 2001/11/26 19:02:22 1.8
@@ -92,7 +92,7 @@
if (direction == PCI_DMA_NONE)
BUG();
-#ifndef CONFIG_COHERENT_IO
+#ifdef CONFIG_NONCOHERENT_IO
dma_cache_wback_inv((unsigned long)ptr, size);
#endif
@@ -131,7 +131,7 @@
addr = (unsigned long) page_address(page);
addr += offset;
-#ifndef CONFIG_COHERENT_IO
+#ifdef CONFIG_NONCOHERENT_IO
dma_cache_wback_inv(addr, size);
#endif
@@ -165,14 +165,14 @@
static inline int pci_map_sg(struct pci_dev *hwdev, struct scatterlist *sg,
int nents, int direction)
{
-#ifndef CONFIG_COHERENT_IO
+#ifdef CONFIG_NONCOHERENT_IO
int i;
#endif
if (direction == PCI_DMA_NONE)
BUG();
-#ifndef CONFIG_COHERENT_IO
+#ifdef CONFIG_NONCOHERENT_IO
/* Make sure that gcc doesn't leave the empty loop body. */
for (i = 0; i < nents; i++, sg++)
dma_cache_wback_inv((unsigned long)sg->address, sg->length);
@@ -212,7 +212,7 @@
if (direction == PCI_DMA_NONE)
BUG();
-#ifndef CONFIG_COHERENT_IO
+#ifdef CONFIG_NONCOHERENT_IO
dma_cache_wback_inv((unsigned long)bus_to_virt(dma_handle), size);
#endif
}
@@ -228,7 +228,7 @@
struct scatterlist *sg,
int nelems, int direction)
{
-#ifndef CONFIG_COHERENT_IO
+#ifdef CONFIG_NONCOHERENT_IO
int i;
#endif
@@ -236,7 +236,7 @@
BUG();
/* Make sure that gcc doesn't leave the empty loop body. */
-#ifndef CONFIG_COHERENT_IO
+#ifdef CONFIG_NONCOHERENT_IO
for (i = 0; i < nelems; i++, sg++)
dma_cache_wback_inv((unsigned long)sg->address, sg->length);
#endif
|
|
From: James S. <jsi...@us...> - 2001-11-26 19:02:24
|
Update of /cvsroot/linux-mips/linux/arch/mips/kernel
In directory usw-pr-cvs1:/tmp/cvs-serv19527/arch/mips/kernel
Modified Files:
pci-dma.c
Log Message:
Reimplement ioswapping for 32-bit <asm/io.h>. Make support for non-coherent I/O on 32-bit MIPS option (CONFIG_NONCOHERENT_IO. Replace CONFIG_COHERENT_IO by CONFIG_NONCOHERENT_IO. The cobalt hacks can go away now.
Index: pci-dma.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/kernel/pci-dma.c,v
retrieving revision 1.6
retrieving revision 1.7
diff -u -d -r1.6 -r1.7
--- pci-dma.c 2001/11/06 00:30:42 1.6
+++ pci-dma.c 2001/11/26 19:02:22 1.7
@@ -28,7 +28,7 @@
if (ret != NULL) {
memset(ret, 0, size);
-#ifndef CONFIG_COHERENT_IO
+#ifdef CONFIG_NONCOHERENT_IO
dma_cache_wback_inv((unsigned long) ret, size);
ret = KSEG1ADDR(ret);
#endif
@@ -43,7 +43,7 @@
{
unsigned long addr = (unsigned long) vaddr;
-#ifndef CONFIG_COHERENT_IO
+#ifdef CONFIG_NONCOHERENT_IO
addr = KSEG0ADDR(addr);
#endif
free_pages(addr, get_order(size));
|
|
From: James S. <jsi...@us...> - 2001-11-26 18:58:41
|
Update of /cvsroot/linux-mips/linux/arch/mips/mips-boards/malta In directory usw-pr-cvs1:/tmp/cvs-serv18346 Added Files: malta_int.c Log Message: Kill some redundant code. This still isn't the explanation for why Malta interrupt doesn't seem to be working ... |
|
From: James S. <jsi...@us...> - 2001-11-26 18:57:30
|
Update of /cvsroot/linux-mips/linux/include/asm-mips
In directory usw-pr-cvs1:/tmp/cvs-serv18035
Modified Files:
io.h
Log Message:
New io stuff. Please test it out with the PCMICA issues and 16 bit access.
Index: io.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/io.h,v
retrieving revision 1.9
retrieving revision 1.10
diff -u -d -r1.9 -r1.10
--- io.h 2001/11/12 18:37:12 1.9
+++ io.h 2001/11/26 18:57:28 1.10
@@ -13,6 +13,7 @@
#include <linux/config.h>
#include <linux/pagemap.h>
+#include <linux/types.h>
#include <asm/addrspace.h>
#include <asm/byteorder.h>
@@ -40,25 +41,13 @@
#endif
/*
- * This file contains the definitions for the MIPS counterpart of the
- * x86 in/out instructions. This heap of macros and C results in much
- * better code than the approach of doing it in plain C. The macros
- * result in code that is to fast for certain hardware. On the other
- * side the performance of the string functions should be improved for
- * sake of certain devices like EIDE disks that do highspeed polled I/O.
- *
- * Ralf
- *
- * This file contains the definitions for the x86 IO instructions
- * inb/inw/inl/outb/outw/outl and the "string versions" of the same
- * (insb/insw/insl/outsb/outsw/outsl). You can also use "pausing"
- * versions of the single-IO instructions (inb_p/inw_p/..).
+ * <Bacchus> Historically I wrote this stuff the same way as Linus did
+ * because I was young and clueless. And now it's so jucky that I
+ * don't want to put my eyes on it again to get rid of it :-)
*
- * This file is not meant to be obfuscating: it's just complicated
- * to (a) handle it all in a way that makes gcc able to optimize it
- * as well as possible and (b) trying to avoid writing the same thing
- * over and over again with slight variations and possibly making a
- * mistake somewhere.
+ * I'll do it then, because this code offends both me and my compiler
+ * - particularly the bits of inline asm which end up doing crap like
+ * 'lb $2,$2($5)' -- dwmw2
*/
#define IO_SPACE_LIMIT 0xffff
@@ -71,8 +60,11 @@
* instruction, so the lower 16 bits must be zero. Should be true on
* on any sane architecture; generic code does not use this assumption.
*/
-extern unsigned long mips_io_port_base;
+extern const unsigned long mips_io_port_base;
+#define set_io_port_base(base) \
+ do { * (unsigned long *) &mips_io_port_base = (base); } while (0)
+
/*
* Thanks to James van Artsdalen for a better timing-fix than
* the two short jumps: using outb's to a nonexistent port seems
@@ -166,7 +158,7 @@
#define __raw_readw readw
#define __raw_readl readl
-#define writeb(b,addr) (*(volatile unsigned char *)(addr)) = (b)
+#define writeb(b,addr) (*(volatile unsigned char *)(addr)) = (__ioswab8(b))
#define writew(b,addr) (*(volatile unsigned short *)(addr)) = (__ioswab16(b))
#define writel(b,addr) (*(volatile unsigned int *)(addr)) = (__ioswab32(b))
#define __raw_writeb writeb
@@ -177,8 +169,6 @@
#define memcpy_fromio(a,b,c) memcpy((a),(void *)(b),(c))
#define memcpy_toio(a,b,c) memcpy((void *)(a),(b),(c))
-/* END SNI HACKS ... */
-
/*
* ISA space is 'always mapped' on currently supported MIPS systems, no need
* to explicitly ioremap() it. The fact that the ISA IO space is mapped
@@ -190,12 +180,12 @@
#define __ISA_IO_base ((char *)(isa_slot_offset))
#define isa_readb(a) readb(__ISA_IO_base + (a))
-#define isa_readw(a) readw(__ISA_IO_base + (a))
+#define isa_readw(a) readw(__ISA_IO_base + (a))
#define isa_readl(a) readl(__ISA_IO_base + (a))
#define isa_writeb(b,a) writeb(b,__ISA_IO_base + (a))
#define isa_writew(w,a) writew(w,__ISA_IO_base + (a))
#define isa_writel(l,a) writel(l,__ISA_IO_base + (a))
-#define isa_memset_io(a,b,c) memset_io(__ISA_IO_base + (a),(b),(c))
+#define isa_memset_io(a,b,c) memset_io(__ISA_IO_base + (a),(b),(c))
#define isa_memcpy_fromio(a,b,c) memcpy_fromio((a),__ISA_IO_base + (b),(c))
#define isa_memcpy_toio(a,b,c) memcpy_toio(__ISA_IO_base + (a),(b),(c))
@@ -223,237 +213,118 @@
}
#define isa_check_signature(io, s, l) check_signature(i,s,l)
-/*
- * Talk about misusing macros..
- */
-
-#define __OUT1(s) \
-static inline void __out##s(unsigned int value, unsigned int port) {
-
-#define __OUT2(m) \
-__asm__ __volatile__ ("s" #m "\t%0,%1(%2)"
-
-#define __OUT(m,s,w) \
-__OUT1(s) __OUT2(m) : : "r" (__ioswab##w(value)), "i" (0), "r" (mips_io_port_base+port)); } \
-__OUT1(s##_p) __OUT2(m) : : "r" (__ioswab##w(value)), "i" (0), "r" (mips_io_port_base+port)); \
- SLOW_DOWN_IO; }
-
-#define __OUTMAC(m,w,value,port) ({ __OUT2(m) : : "r" (__ioswab##w(value)), "i#*X" (port), \
- "r" (mips_io_port_base)); })
-#define __OUTMAC_P(m,w,value,port) ({ __OUT2(m) : : "r" (__ioswab##w(value)), "i#*X" (port), \
- "r" (mips_io_port_base)); SLOW_DOWN_IO; })
-
-#define __outbc(value,port) __OUTMAC(b,8,value,port)
-#define __outwc(value,port) __OUTMAC(h,16,value,port)
-#define __outlc(value,port) __OUTMAC(w,32,value,port)
-#define __outbc_p(value,port) __OUTMAC_P(b,8,value,port)
-#define __outwc_p(value,port) __OUTMAC_P(h,16,value,port)
-#define __outlc_p(value,port) __OUTMAC_P(w,32,value,port)
-
-#define __IN1(t,s) \
-extern __inline__ t __in##s(unsigned int port) { t _v;
-
-/*
- * Required nops will be inserted by the assembler
- */
-#define __IN2(m) \
-__asm__ __volatile__ ("l" #m "\t%0,%1(%2)"
-
-#define __IN(t,m,s,w) \
-__IN1(t,s) __IN2(m) : "=r" (_v) : "i" (0), "r" (mips_io_port_base+port)); return __ioswab##w(_v); } \
-__IN1(t,s##_p) __IN2(m) : "=r" (_v) : "i" (0), "r" (mips_io_port_base+port)); SLOW_DOWN_IO; return __ioswab##w(_v); }
-
-#define __INMAC(t,m,w,port) ({ t _v; __IN2(m) : "=r" (_v) : "i#*X" (port), \
- "r" (mips_io_port_base)); __ioswab##w(_v); })
-#define __INMAC_P(t,m,w,port) ({ t _v; __IN2(m) : "=r" (_v) : "i#*X" (port), \
- "r" (mips_io_port_base)); SLOW_DOWN_IO; __ioswab##w(_v); })
-
-#define __inbc(port) __INMAC(unsigned char,b,8,port)
-#define __inwc(port) __INMAC(unsigned short,h,16,port)
-#define __inlc(port) __INMAC(unsigned int,w,32,port)
-#define __inbc_p(port) __INMAC_P(unsigned char,b,8,port)
-#define __inwc_p(port) __INMAC_P(unsigned short,h,16,port)
-#define __inlc_p(port) __INMAC_P(unsigned int,w,32,port)
-
-#define __INS1(s) \
-static inline void __ins##s(unsigned int port, void * addr, unsigned long count) {
-
-#define __INS2(m,count) \
-if (count) \
-__asm__ __volatile__ ( \
- ".set\tnoreorder\n\t" \
- ".set\tnoat\n" \
- "1:\tl" #m "\t$1,%4(%5)\n\t" \
- "subu\t%1,1\n\t" \
- "s" #m "\t$1,(%0)\n\t" \
- "bne\t$0,%1,1b\n\t" \
- "addiu\t%0,%6\n\t" \
- ".set\tat\n\t" \
- ".set\treorder"
-
-#define __INS(m,s,i) \
-__INS1(s) __INS2(m,count) \
- : "=r" (addr), "=r" (count) \
- : "0" (addr), "1" (count), "i" (0), \
- "r" (mips_io_port_base+port), "I" (i) \
- : "$1");} \
-
-#define __INSMAC(m,i,port,addr,count) ({ void *_a = (addr); unsigned long _c = (count); \
- __INS2(m,_c) \
- : "=r" (_a), "=r" (_c) \
- : "0" (_a), "1" (_c), "i#*X" (port), \
- "r" (mips_io_port_base), "I" (i) \
- : "$1"); })
-
-#define __insbc(port,addr,count) __INSMAC(b,1,port,addr,count)
-#define __inswc(port,addr,count) __INSMAC(h,2,port,addr,count)
-#define __inslc(port,addr,count) __INSMAC(w,4,port,addr,count)
-
-#define __OUTS1(s) \
-static inline void __outs##s(unsigned int port, const void * addr, unsigned long count) {
-
-#define __OUTS2(m,count) \
-if (count) \
-__asm__ __volatile__ ( \
- ".set\tnoreorder\n\t" \
- ".set\tnoat\n" \
- "1:\tl" #m "\t$1,(%0)\n\t" \
- "subu\t%1,1\n\t" \
- "s" #m "\t$1,%4(%5)\n\t" \
- "bne\t$0,%1,1b\n\t" \
- "addiu\t%0,%6\n\t" \
- ".set\tat\n\t" \
- ".set\treorder"
-
-#define __OUTS(m,s,i) \
-__OUTS1(s) __OUTS2(m,count) \
- : "=r" (addr), "=r" (count) \
- : "0" (addr), "1" (count), "i" (0), "r" (mips_io_port_base+port), "I" (i) \
- : "$1");}
-
-#define __OUTSMAC(m,i,port,addr,count) ({ void *_a = (addr); unsigned long _c = (count); \
- __OUTS2(m,_c) \
- : "=r" (_a), "=r" (_c) \
- : "0" (_a), "1" (_c), "i#*X" (port), "r" (mips_io_port_base), "I" (i) \
- : "$1"); })
-#define __outsbc(port,addr,count) __OUTSMAC(b,1,port,addr,count)
-#define __outswc(port,addr,count) __OUTSMAC(h,2,port,addr,count)
-#define __outslc(port,addr,count) __OUTSMAC(w,4,port,addr,count)
-
-__IN(unsigned char,b,b,8)
-__IN(unsigned short,h,w,16)
-__IN(unsigned int,w,l,32)
-__OUT(b,b,8)
-__OUT(h,w,16)
-__OUT(w,l,32)
-
-__INS(b,b,1)
-__INS(h,w,2)
-__INS(w,l,4)
-
-__OUTS(b,b,1)
-__OUTS(h,w,2)
-__OUTS(w,l,4)
-
-
-/*
- * Note that due to the way __builtin_constant_p() works, you
- * - can't use it inside an inline function (it will never be true)
- * - you don't have to worry about side effects within the __builtin..
- */
-#define outb(val,port) \
-((__builtin_constant_p((port)) && (port) < 32768) ? \
- __outbc((val),(port)) : \
- __outb((val),(port)))
-
-#define inb(port) \
-((__builtin_constant_p((port)) && (port) < 32768) ? \
- __inbc(port) : \
- __inb(port))
-
-#define outb_p(val,port) \
-((__builtin_constant_p((port)) && (port) < 32768) ? \
- __outbc_p((val),(port)) : \
- __outb_p((val),(port)))
-
-#define inb_p(port) \
-((__builtin_constant_p((port)) && (port) < 32768) ? \
- __inbc_p(port) : \
- __inb_p(port))
-
-#define outw(val,port) \
-((__builtin_constant_p((port)) && (port) < 32768) ? \
- __outwc((val),(port)) : \
- __outw((val),(port)))
+#define outb(val,port) \
+do { \
+ *(volatile u8 *)(mips_io_port_base + (port)) = __ioswab8(val); \
+} while(0)
-#define inw(port) \
-((__builtin_constant_p((port)) && (port) < 32768) ? \
- __inwc(port) : \
- __inw(port))
+#define outw(val,port) \
+do { \
+ *(volatile u16 *)(mips_io_port_base + (port)) = __ioswab16(val); \
+} while(0)
-#define outw_p(val,port) \
-((__builtin_constant_p((port)) && (port) < 32768) ? \
- __outwc_p((val),(port)) : \
- __outw_p((val),(port)))
+#define outl(val,port) \
+do { \
+ *(volatile u32 *)(mips_io_port_base + (port)) = __ioswab32(val);\
+} while(0)
-#define inw_p(port) \
-((__builtin_constant_p((port)) && (port) < 32768) ? \
- __inwc_p(port) : \
- __inw_p(port))
+#define outb_p(val,port) \
+do { \
+ *(volatile u8 *)(mips_io_port_base + (port)) = __ioswab8(val); \
+ SLOW_DOWN_IO; \
+} while(0)
-#define outl(val,port) \
-((__builtin_constant_p((port)) && (port) < 32768) ? \
- __outlc((val),(port)) : \
- __outl((val),(port)))
+#define outw_p(val,port) \
+do { \
+ *(volatile u16 *)(mips_io_port_base + (port)) = __ioswab16(val);\
+ SLOW_DOWN_IO; \
+} while(0)
-#define inl(port) \
-((__builtin_constant_p((port)) && (port) < 32768) ? \
- __inlc(port) : \
- __inl(port))
+#define outl_p(val,port) \
+do { \
+ *(volatile u32 *)(mips_io_port_base + (port)) = __ioswab32(val);\
+ SLOW_DOWN_IO; \
+} while(0)
-#define outl_p(val,port) \
-((__builtin_constant_p((port)) && (port) < 32768) ? \
- __outlc_p((val),(port)) : \
- __outl_p((val),(port)))
+#define inb(port) (__ioswab8(*(volatile u8 *)(mips_io_port_base + (port))))
+#define inw(port) (__ioswab16(*(volatile u16 *)(mips_io_port_base + (port))))
+#define inl(port) (__ioswab32(*(volatile u32 *)(mips_io_port_base + (port))))
-#define inl_p(port) \
-((__builtin_constant_p((port)) && (port) < 32768) ? \
- __inlc_p(port) : \
- __inl_p(port))
+#define inb_p(port) \
+({ \
+ u8 __val; \
+ \
+ __val = *(volatile u8 *)(mips_io_port_base + (port)); \
+ SLOW_DOWN_IO; \
+ __ioswab8(__val); \
+})
+#define inw_p(port) \
+({ \
+ u16 __val; \
+ \
+ __val = *(volatile u16 *)(mips_io_port_base + (port)); \
+ SLOW_DOWN_IO; \
+ __ioswab16(__val); \
+})
-#define outsb(port,addr,count) \
-((__builtin_constant_p((port)) && (port) < 32768) ? \
- __outsbc((port),(addr),(count)) : \
- __outsb ((port),(addr),(count)))
+#define inl_p(port) \
+({ \
+ u32 __val; \
+ \
+ __val = *(volatile u32 *)(mips_io_port_base + (port)); \
+ SLOW_DOWN_IO; \
+ __ioswab32(__val); \
+})
-#define insb(port,addr,count) \
-((__builtin_constant_p((port)) && (port) < 32768) ? \
- __insbc((port),(addr),(count)) : \
- __insb((port),(addr),(count)))
+static inline void outsb(unsigned long port, void *addr, unsigned int count)
+{
+ while (count--) {
+ outb(*(u8 *)addr, port);
+ addr++;
+ }
+}
-#define outsw(port,addr,count) \
-((__builtin_constant_p((port)) && (port) < 32768) ? \
- __outswc((port),(addr),(count)) : \
- __outsw ((port),(addr),(count)))
+static inline void insb(unsigned long port, void *addr, unsigned int count)
+{
+ while (count--) {
+ *(u8 *)addr = inb(port);
+ addr++;
+ }
+}
-#define insw(port,addr,count) \
-((__builtin_constant_p((port)) && (port) < 32768) ? \
- __inswc((port),(addr),(count)) : \
- __insw((port),(addr),(count)))
+static inline void outsw(unsigned long port, void *addr, unsigned int count)
+{
+ while (count--) {
+ outw(*(u16 *)addr, port);
+ addr += 2;
+ }
+}
-#define outsl(port,addr,count) \
-((__builtin_constant_p((port)) && (port) < 32768) ? \
- __outslc((port),(addr),(count)) : \
- __outsl ((port),(addr),(count)))
+static inline void insw(unsigned long port, void *addr, unsigned int count)
+{
+ while (count--) {
+ *(u16 *)addr = inw(port);
+ addr += 2;
+ }
+}
-#define insl(port,addr,count) \
-((__builtin_constant_p((port)) && (port) < 32768) ? \
- __inslc((port),(addr),(count)) : \
- __insl((port),(addr),(count)))
+static inline void outsl(unsigned long port, void *addr, unsigned int count)
+{
+ while (count--) {
+ outl(*(u32 *)addr, port);
+ addr += 4;
+ }
+}
-#define IO_SPACE_LIMIT 0xffff
+static inline void insl(unsigned long port, void *addr, unsigned int count)
+{
+ while (count--) {
+ *(u32 *)addr = inw(port);
+ addr += 4;
+ }
+}
/*
* The caches on some architectures aren't dma-coherent and have need to
@@ -473,6 +344,8 @@
* be discarded. This operation is necessary before dma operations
* to the memory.
*/
+#ifdef CONFIG_NONCOHERENT_IO
+
extern void (*_dma_cache_wback_inv)(unsigned long start, unsigned long size);
extern void (*_dma_cache_wback)(unsigned long start, unsigned long size);
extern void (*_dma_cache_inv)(unsigned long start, unsigned long size);
@@ -480,5 +353,13 @@
#define dma_cache_wback_inv(start,size) _dma_cache_wback_inv(start,size)
#define dma_cache_wback(start,size) _dma_cache_wback(start,size)
#define dma_cache_inv(start,size) _dma_cache_inv(start,size)
+
+#else /* Sane hardware */
+
+#define dma_cache_wback_inv(start,size) do { (start); (size); } while (0)
+#define dma_cache_wback(start,size) do { (start); (size); } while (0)
+#define dma_cache_inv(start,size) do { (start); (size); } while (0)
+
+#endif /* CONFIG_NONCOHERENT_IO */
#endif /* _ASM_IO_H */
|
|
From: James S. <jsi...@us...> - 2001-11-26 18:54:00
|
Update of /cvsroot/linux-mips/linux/arch/mips/kernel
In directory usw-pr-cvs1:/tmp/cvs-serv17112
Modified Files:
traps.c
Log Message:
Lots of fixes. Dump full TLB when dieing. Don't print message about having sent a FP signal.Only install EJTAG handler if MIPS_CPU_EJTAG in cpu options set. This fixes a memory corruption bug. EJTAG exception handler is located at KSEG0+0x200.
Index: traps.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/kernel/traps.c,v
retrieving revision 1.25
retrieving revision 1.26
diff -u -d -r1.25 -r1.26
--- traps.c 2001/11/20 17:35:48 1.25
+++ traps.c 2001/11/26 18:53:57 1.26
@@ -309,7 +309,7 @@
/*
* Saved cp0 registers
*/
- printk("epc : %08lx %s\nStatus: %08x\nCause : %08x\n",
+ printk("epc : %08lx %s\nStatus: %08lx\nCause : %08lx\n",
regs->cp0_epc, print_tainted(), regs->cp0_status,
regs->cp0_cause);
}
@@ -501,7 +501,6 @@
return;
force_sig(SIGFPE, current);
- printk(KERN_DEBUG "Sent send SIGFPE to %s\n", current->comm);
}
static inline int get_insn_opcode(struct pt_regs *regs, unsigned int *opcode)
@@ -698,11 +697,13 @@
asmlinkage void do_watch(struct pt_regs *regs)
{
+ extern void dump_tlb_all(void);
+
/*
* We use the watch exception where available to detect stack
* overflows.
*/
- dump_tlb();
+ dump_tlb_all();
show_regs(regs);
panic("Caught WATCH exception - probably caused by stack overflow.");
}
@@ -843,7 +844,8 @@
* Copy the EJTAG debug exception vector handler code to it's final
* destination.
*/
- memcpy((void *)(KSEG0 + 0x300), &except_vec_ejtag_debug, 0x80);
+ if (mips_cpu.options & MIPS_CPU_EJTAG)
+ memcpy((void *)(KSEG0 + 0x200), &except_vec_ejtag_debug, 0x80);
/*
* Only some CPUs have the watch exceptions or a dedicated
|
|
From: James S. <jsi...@us...> - 2001-11-26 18:50:22
|
Update of /cvsroot/linux-mips/linux/include/asm-mips
In directory usw-pr-cvs1:/tmp/cvs-serv15987
Modified Files:
mmu_context.h
Log Message:
Flush virtually tagged i-caches on ASID overflow.
Index: mmu_context.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/mmu_context.h,v
retrieving revision 1.7
retrieving revision 1.8
diff -u -d -r1.7 -r1.8
--- mmu_context.h 2001/11/19 17:57:38 1.7
+++ mmu_context.h 2001/11/26 18:50:19 1.8
@@ -14,6 +14,7 @@
#include <linux/config.h>
#include <linux/slab.h>
#include <asm/pgalloc.h>
+#include <asm/pgtable.h>
/*
* For the fast tlb miss handlers, we currently keep a per cpu array
@@ -66,6 +67,7 @@
unsigned long asid = ASID_CACHE(cpu);
if (! ((asid += ASID_INC) & ASID_MASK) ) {
+ flush_icache_all();
local_flush_tlb_all(); /* start new asid cycle */
if (!asid) /* fix version if needed */
asid = ASID_FIRST_VERSION;
|
|
From: James S. <jsi...@us...> - 2001-11-26 18:49:25
|
Update of /cvsroot/linux-mips/linux/arch/mips/mm In directory usw-pr-cvs1:/tmp/cvs-serv15647 Modified Files: loadmmu.c Log Message: Define _flush_icache_all. Index: loadmmu.c =================================================================== RCS file: /cvsroot/linux-mips/linux/arch/mips/mm/loadmmu.c,v retrieving revision 1.8 retrieving revision 1.9 diff -u -d -r1.8 -r1.9 --- loadmmu.c 2001/11/19 17:38:47 1.8 +++ loadmmu.c 2001/11/26 18:49:22 1.9 @@ -29,14 +29,25 @@ unsigned long end); void (*_flush_cache_page)(struct vm_area_struct *vma, unsigned long page); void (*_flush_cache_sigtramp)(unsigned long addr); -void (*_flush_page_to_ram)(struct page * page); void (*_flush_icache_range)(unsigned long start, unsigned long end); void (*_flush_icache_page)(struct vm_area_struct *vma, struct page *page); +void (*_flush_page_to_ram)(struct page * page); +void (*_flush_icache_all)(void); + +#ifdef CONFIG_NONCOHERENT_IO + /* DMA cache operations. */ void (*_dma_cache_wback_inv)(unsigned long start, unsigned long size); void (*_dma_cache_wback)(unsigned long start, unsigned long size); void (*_dma_cache_inv)(unsigned long start, unsigned long size); + +EXPORT_SYMBOL(_dma_cache_wback_inv); +EXPORT_SYMBOL(_dma_cache_wback); +EXPORT_SYMBOL(_dma_cache_inv); + +#endif /* CONFIG_NONCOHERENT_IO */ + extern void ld_mmu_r23000(void); extern void ld_mmu_r4xx0(void); |
|
From: James S. <jsi...@us...> - 2001-11-26 18:48:17
|
Update of /cvsroot/linux-mips/linux/arch/mips/kernel
In directory usw-pr-cvs1:/tmp/cvs-serv15292
Modified Files:
setup.c
Log Message:
Add a kernel option to disable the FPU in the kernel. Useful for debugging the full FPU emulator on fpu-full systems.
Index: setup.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/kernel/setup.c,v
retrieving revision 1.31
retrieving revision 1.32
diff -u -d -r1.31 -r1.32
--- setup.c 2001/11/22 01:19:24 1.31
+++ setup.c 2001/11/26 18:48:14 1.32
@@ -7,7 +7,7 @@
* Copyright (C) 1995 Waldorf Electronics
* Copyright (C) 1995, 1996, 1997, 1998, 1999, 2000, 2001 Ralf Baechle
* Copyright (C) 1996 Stoned Elipot
- * Copyright (C) 2000 Maciej W. Rozycki
+ * Copyright (C) 2000, 2001 Maciej W. Rozycki
*/
#include <linux/config.h>
#include <linux/errno.h>
@@ -17,6 +17,7 @@
#include <linux/sched.h>
#include <linux/kernel.h>
#include <linux/mm.h>
+#include <linux/module.h>
#include <linux/stddef.h>
#include <linux/string.h>
#include <linux/unistd.h>
@@ -105,13 +106,14 @@
* mips_io_port_base is the begin of the address space to which x86 style
* I/O ports are mapped.
*/
-unsigned long mips_io_port_base;
+unsigned long mips_io_port_base; EXPORT_SYMBOL(mips_io_port_base);
+
/*
* isa_slot_offset is the address where E(ISA) busaddress 0 is is mapped
* for the processor.
*/
-unsigned long isa_slot_offset;
+unsigned long isa_slot_offset; EXPORT_SYMBOL(isa_slot_offset);
extern void sgi_sysinit(void);
extern void SetUpBootInfo(void);
@@ -182,6 +184,28 @@
#endif
}
+/*
+ * Get the FPU Implementation/Revision.
+ */
+static inline unsigned long cpu_get_fpu_id(void)
+{
+ unsigned long tmp, fpu_id;
+
+ tmp = read_32bit_cp0_register(CP0_STATUS);
+ write_32bit_cp0_register(CP0_STATUS, tmp | ST0_CU1);
+ fpu_id = read_32bit_cp1_register(CP1_REVISION);
+ write_32bit_cp0_register(CP0_STATUS, tmp);
+ return fpu_id;
+}
+
+/*
+ * Check the CPU has an FPU the official way.
+ */
+static inline int cpu_has_fpu(void)
+{
+ return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE);
+}
+
/* declaration of the global struct */
struct mips_cpu mips_cpu = {PRID_IMP_UNKNOWN, CPU_UNKNOWN, 0, 0, 0,
{0,0,0,0}, {0,0,0,0}, {0,0,0,0}, {0,0,0,0}};
@@ -206,6 +230,8 @@
mips_cpu.cputype = CPU_R2000;
mips_cpu.isa_level = MIPS_CPU_ISA_I;
mips_cpu.options = MIPS_CPU_TLB;
+ if (cpu_has_fpu())
+ mips_cpu.options |= MIPS_CPU_FPU;
mips_cpu.tlbsize = 64;
break;
case PRID_IMP_R3000:
@@ -218,6 +244,8 @@
mips_cpu.cputype = CPU_R3000;
mips_cpu.isa_level = MIPS_CPU_ISA_I;
mips_cpu.options = MIPS_CPU_TLB;
+ if (cpu_has_fpu())
+ mips_cpu.options |= MIPS_CPU_FPU;
mips_cpu.tlbsize = 64;
break;
case PRID_IMP_R4000:
@@ -344,7 +372,7 @@
mips_cpu.cputype = CPU_NEVADA;
mips_cpu.isa_level = MIPS_CPU_ISA_IV;
mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU |
- MIPS_CPU_32FPR | MIPS_CPU_DIVEC;
+ MIPS_CPU_32FPR | MIPS_CPU_DIVEC;
mips_cpu.tlbsize = 48;
mips_cpu.icache.ways = 2;
mips_cpu.dcache.ways = 2;
@@ -630,7 +658,7 @@
void atlas_setup(void);
void baget_setup(void);
void ddb_setup(void);
- void cobalt_setup(void);
+ void cobalt_setup(void);
void decstation_setup(void);
void deskstation_setup(void);
void jazz_setup(void);
@@ -647,12 +675,14 @@
void ps2_setup(void);
void clio_1000_setup(void);
void jmr3927_setup(void);
- void it8172_setup(void);
+ void it8172_setup(void);
+ void swarm_setup(void);
+ void hp_setup(void);
unsigned long bootmap_size;
unsigned long start_pfn, max_pfn, first_usable_pfn;
#ifdef CONFIG_BLK_DEV_INITRD
- unsigned long *initrd_header;
+ unsigned long* initrd_header;
unsigned long tmp;
#endif
int i;
@@ -797,7 +827,7 @@
#endif
#ifdef CONFIG_HP_LASERJET
case MACH_GROUP_HP_LASERJET:
- { void hp_setup(void); hp_setup(); }
+ hp_setup();
break;
#endif
default:
@@ -985,3 +1015,10 @@
"wait\n\t"
".set\tmips0");
}
+
+int __init fpu_disable(char *s)
+{
+ mips_cpu.options &= ~MIPS_CPU_FPU;
+ return 1;
+}
+__setup("nofpu", fpu_disable);
|
|
From: James S. <jsi...@us...> - 2001-11-26 18:44:43
|
Update of /cvsroot/linux-mips/linux/arch/mips/hp-lj
In directory usw-pr-cvs1:/tmp/cvs-serv12292
Modified Files:
int-handler.S pci.c
Log Message:
Fill missing nop into delay slot.
Index: int-handler.S
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/hp-lj/int-handler.S,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- int-handler.S 2001/11/19 18:31:01 1.1
+++ int-handler.S 2001/11/26 18:38:40 1.2
@@ -54,6 +54,7 @@
jal do_IRQ
nop # delay slot
j ret_from_irq
+ nop
/*
mfc0 t0,CP0_STATUS # disable interrupts
Index: pci.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/hp-lj/pci.c,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- pci.c 2001/11/19 18:31:01 1.1
+++ pci.c 2001/11/26 18:38:40 1.2
@@ -178,9 +178,7 @@
// by letting both low (illegal) and high (legal) addresses appear in pci io space
ioport_resource.start = 0x0;
- mips_io_port_base = IO_PORT_LOGICAL_START + IO_PORT_VIRTUAL_OFFSET;
- printk("Set IO port base to 0x%lx\n", mips_io_port_base);
-
+ set_io_port_base(IO_PORT_LOGICAL_START + IO_PORT_VIRTUAL_OFFSET);
// map the PCI address space
// global map - all levels & processes can access
|
|
From: James S. <jsi...@us...> - 2001-11-26 18:33:44
|
Update of /cvsroot/linux-mips/linux/include/asm-mips In directory usw-pr-cvs1:/tmp/cvs-serv10312 Added Files: ds1286.h Log Message: This one was missing from the Indy RTC updates. --- NEW FILE: ds1286.h --- /* * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * * mc146818rtc.h - register definitions for the Real-Time-Clock / CMOS RAM * Copyright Torsten Duwe <du...@in...> 1993 * derived from Data Sheet, Copyright Motorola 1984 (!). * It was written to be part of the Linux operating system. * * Copyright (C) 1998, 1999 Ralf Baechle */ #ifndef _ASM_DS1286_h #define _ASM_DS1286_h #include <asm/mc146818rtc.h> /********************************************************************** * register summary **********************************************************************/ #define RTC_HUNDREDTH_SECOND 0 #define RTC_SECONDS 1 #define RTC_MINUTES 2 #define RTC_MINUTES_ALARM 3 #define RTC_HOURS 4 #define RTC_HOURS_ALARM 5 #define RTC_DAY 6 #define RTC_DAY_ALARM 7 #define RTC_DATE 8 #define RTC_MONTH 9 #define RTC_YEAR 10 #define RTC_CMD 11 #define RTC_WHSEC 12 #define RTC_WSEC 13 #define RTC_UNUSED 14 /* RTC_*_alarm is always true if 2 MSBs are set */ # define RTC_ALARM_DONT_CARE 0xC0 /* * Bits in the month register */ #define RTC_EOSC 0x80 #define RTC_ESQW 0x40 /* * Bits in the Command register */ #define RTC_TDF 0x01 #define RTC_WAF 0x02 #define RTC_TDM 0x04 #define RTC_WAM 0x08 #define RTC_PU_LVL 0x10 #define RTC_IBH_LO 0x20 #define RTC_IPSW 0x40 #define RTC_TE 0x80 /* * Conversion between binary and BCD. */ #ifndef BCD_TO_BIN #define BCD_TO_BIN(val) ((val)=((val)&15) + ((val)>>4)*10) #endif #ifndef BIN_TO_BCD #define BIN_TO_BCD(val) ((val)=(((val)/10)<<4) + (val)%10) #endif #endif /* _ASM_DS1286_h */ |
|
From: James S. <jsi...@us...> - 2001-11-26 18:32:55
|
Update of /cvsroot/linux-mips/linux/arch/mips/mm
In directory usw-pr-cvs1:/tmp/cvs-serv10019
Modified Files:
c-sb1.c
Log Message:
Seems like on the SB1 remote i-caches indeed need flushing. Old remote flushing code had a big ugly race so reimplement it. Make __flush_cache_all() flush all caches without consideration of number of cache sets. flush_cache_all() is now a nop.
Index: c-sb1.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/mm/c-sb1.c,v
retrieving revision 1.4
retrieving revision 1.5
diff -u -d -r1.4 -r1.5
--- c-sb1.c 2001/11/21 22:12:42 1.4
+++ c-sb1.c 2001/11/26 18:32:52 1.5
@@ -21,6 +21,7 @@
#include <linux/init.h>
#include <asm/mmu_context.h>
#include <asm/bootinfo.h>
+#include <asm/cacheops.h>
#include <asm/cpu.h>
/* These are probed at ld_mmu time */
@@ -37,7 +38,6 @@
static unsigned int icache_sets;
static unsigned int dcache_sets;
-static unsigned int tlb_entries;
void pgd_init(unsigned long page)
{
@@ -71,7 +71,10 @@
static void sb1_flush_cache_all(void)
{
+}
+static void local_sb1___flush_cache_all(void)
+{
/*
* Haven't worried too much about speed here; given that we're flushing
* the icache, the time to invalidate is dwarfed by the time it's going
@@ -80,55 +83,61 @@
* $1 - moving cache index
* $2 - set count
*/
- if (icache_sets) {
- if (dcache_sets) {
- __asm__ __volatile__ (
- ".set push \n"
- ".set noreorder \n"
- ".set noat \n"
- ".set mips4 \n"
- " move $1, %2 \n" /* Start at index 0 */
- "1: cache 0x1, 0($1) \n" /* WB/Invalidate this index */
- " addiu %1, %1, -1 \n" /* Decrement loop count */
- " bnez %1, 1b \n" /* loop test */
- " addu $1, $1, %0 \n" /* Next address */
- ".set pop \n"
- :
- : "r" (dcache_line_size),
- "r" (dcache_sets * dcache_assoc),
- "r" (KSEG0)
- "i" (Index_Writeback_Inv_D));
+ __asm__ __volatile__ (
+ ".set push \n"
+ ".set noreorder \n"
+ ".set noat \n"
+ ".set mips4 \n"
+ " move $1, %2 \n" /* Start at index 0 */
+ "1: cache 0x1, 0($1) \n" /* WB/Invalidate this index */
+ " addiu %1, %1, -1 \n" /* Decrement loop count */
+ " bnez %1, 1b \n" /* loop test */
+ " addu $1, $1, %0 \n" /* Next address */
+ ".set pop \n"
+ :
+ : "r" (dcache_line_size), "r" (dcache_sets * dcache_assoc),
+ "r" (KSEG0), "i" (Index_Writeback_Inv_D));
- __asm__ __volatile__ (
- ".set push \n"
- ".set noreorder \n"
- ".set mips2 \n"
- "sync \n"
+ __asm__ __volatile__ (
+ ".set push \n"
+ ".set noreorder \n"
+ ".set mips2 \n"
+ "sync \n"
#ifdef CONFIG_SB1_PASS_1_WORKAROUNDS /* Bug 1384 */
- "sync \n"
+ "sync \n"
#endif
- ".set pop \n");
- }
- __asm__ __volatile__ (
- ".set push \n"
- ".set noreorder \n"
- ".set noat \n"
- ".set mips4 \n"
- " move $1, %2 \n" /* Start at index 0 */
- "1: cache %3, 0($1) \n" /* Invalidate this index */
- " addiu %1, %1, -1 \n" /* Decrement loop count */
- " bnez %1, 1b \n" /* loop test */
- " addu $1, $1, %0 \n" /* Next address */
- ".set pop \n"
- :
- : "r" (icache_line_size),
- "r" (icache_sets * icache_assoc),
- "r" (KSEG0),
- "i" (Index_Invalidate_I)
- :"$1");
- }
+ ".set pop \n");
+
+ __asm__ __volatile__ (
+ ".set push \n"
+ ".set noreorder \n"
+ ".set noat \n"
+ ".set mips4 \n"
+ " move $1, %2 \n" /* Start at index 0 */
+ "1: cache %3, 0($1) \n" /* Invalidate this index */
+ " addiu %1, %1, -1 \n" /* Decrement loop count */
+ " bnez %1, 1b \n" /* loop test */
+ " addu $1, $1, %0 \n" /* Next address */
+ ".set pop \n"
+ :
+ : "r" (icache_line_size), "r" (icache_sets * icache_assoc),
+ "r" (KSEG0), "i" (Index_Invalidate_I));
}
+#ifdef CONFIG_SMP
+extern void sb1___flush_cache_all_ipi(void *ignored);
+asm("sb1___flush_cache_all_ipi = local_sb1___flush_cache_all");
+
+static void sb1___flush_cache_all(void)
+{
+ smp_call_function(sb1___flush_cache_all_ipi, 0, 1, 1);
+ local_sb1___flush_cache_all();
+}
+#else
+asm("sb1___flush_cache_all = local_sb1___flush_cache_all");
+#endif
+
+
/*
* When flushing a range in the icache, we have to first writeback
* the dcache for the same range, so new ifetches will see any
@@ -141,85 +150,106 @@
* of writeback-invalidating it. Not doing the invalidates
* doesn't cost us anything, since we're coherent
*
-*/
+ */
-static void sb1_flush_icache_range(unsigned long start, unsigned long end)
+static void local_sb1_flush_icache_range(unsigned long start, unsigned long end)
{
- if (icache_sets) {
- if (dcache_sets) {
#ifdef CONFIG_SB1_PASS_1_WORKAROUNDS
- unsigned long flags;
- local_irq_save(flags);
+ unsigned long flags;
+ local_irq_save(flags);
#endif
- __asm__ __volatile__ (
- ".set push \n"
- ".set noreorder \n"
- ".set noat \n"
- ".set mips4 \n"
- " move $1, %0 \n"
- "1: \n"
+ __asm__ __volatile__ (
+ ".set push \n"
+ ".set noreorder \n"
+ ".set noat \n"
+ ".set mips4 \n"
+ " move $1, %0 \n"
+ "1: \n"
#ifdef CONFIG_SB1_PASS_1_WORKAROUNDS
- " lw $0, 0($1) \n" /* Bug 1370, 1368 */
- " cache 0x15, 0($1) \n" /* Hit-WB-inval this address */
+ " lw $0, 0($1) \n" /* Bug 1370, 1368 */
+ " cache 0x15, 0($1) \n" /* Hit-WB-inval this address */
#else
- " cache 0x19, 0($1) \n" /* Hit-WB this address */
+ " cache 0x19, 0($1) \n" /* Hit-WB this address */
#endif
- " bne $1, %1, 1b \n" /* loop test */
- " addu $1, $1, %2 \n" /* next line */
- ".set pop \n"
- ::"r" (start),
- "r" (end),
- "r" (dcache_line_size)
- :"$1");
- __asm__ __volatile__ (
- ".set push \n"
- ".set noreorder \n"
- ".set mips2 \n"
- "sync \n"
+ " bne $1, %1, 1b \n" /* loop test */
+ " addu $1, $1, %2 \n" /* next line */
+ ".set pop \n"
+ :
+ : "r" (start), "r" (end),
+ "r" (dcache_line_size));
+ __asm__ __volatile__ (
+ ".set push \n"
+ ".set noreorder \n"
+ ".set mips2 \n"
+ "sync \n"
#ifdef CONFIG_SB1_PASS_1_WORKAROUNDS /* Bug 1384 */
- "sync \n"
+ "sync \n"
#endif
- ".set pop \n");
+ ".set pop \n");
#ifdef CONFIG_SB1_PASS_1_WORKAROUNDS
- local_irq_restore(flags);
+ local_irq_restore(flags);
#endif
- }
- /* XXXKW Guess what: these Kseg0 addressese aren't
- enough to let us figure out what may be in the
- cache under mapped Useg tags. The situation is
- even worse, because bit 12 belongs to both the page
- number AND the cache index, which means the Kseg0
- page number may have a different cache index than
- the Useg address. For these two reasons, we have
- to flush the entire thing. Since the Dcache is
- physically tagged, we *can* use hit operations, */
+
+ /* XXXKW Guess what: these Kseg0 addressese aren't
+ enough to let us figure out what may be in the
+ cache under mapped Useg tags. The situation is
+ even worse, because bit 12 belongs to both the page
+ number AND the cache index, which means the Kseg0
+ page number may have a different cache index than
+ the Useg address. For these two reasons, we have
+ to flush the entire thing. Since the Dcache is
+ physically tagged, we *can* use hit operations, */
#if 0
- start &= icache_index_mask;
- end &= icache_index_mask;
+ start &= icache_index_mask;
+ end &= icache_index_mask;
#else
- start = 0;
- end = icache_index_mask;
+ start = 0;
+ end = icache_index_mask;
#endif
- __asm__ __volatile__ (
- ".set push \n"
- ".set noreorder \n"
- ".set noat \n"
- ".set mips4 \n"
- " move $1, %0 \n"
- "1: cache 0, (0<<13)($1) \n" /* Index-inval this address */
- " cache 0, (1<<13)($1) \n" /* Index-inval this address */
- " cache 0, (2<<13)($1) \n" /* Index-inval this address */
- " cache 0, (3<<13)($1) \n" /* Index-inval this address */
- " bne $1, %1, 1b \n" /* loop test */
- " addu $1, $1, %2 \n" /* next line */
- ".set pop \n"
- ::"r" (start),
- "r" (end),
- "r" (icache_line_size)
- :"$1");
- }
+ __asm__ __volatile__ (
+ ".set push \n"
+ ".set noreorder \n"
+ ".set noat \n"
+ ".set mips4 \n"
+ " move $1, %0 \n"
+ "1: cache 0, (0<<13)($1) \n" /* Index-inval this address */
+ " cache 0, (1<<13)($1) \n" /* Index-inval this address */
+ " cache 0, (2<<13)($1) \n" /* Index-inval this address */
+ " cache 0, (3<<13)($1) \n" /* Index-inval this address */
+ " bne $1, %1, 1b \n" /* loop test */
+ " addu $1, $1, %2 \n" /* next line */
+ ".set pop \n"
+ ::"r" (start),
+ "r" (end),
+ "r" (icache_line_size));
}
+#ifdef CONFIG_SMP
+struct flush_icache_range_args {
+ unsigned long start;
+ unsigned long end;
+};
+
+static void sb1_flush_icache_range_ipi(void *info)
+{
+ struct flush_icache_range_args *args = info;
+
+ local_sb1_flush_icache_range(args->start, args->end);
+}
+
+void sb1_flush_icache_range(unsigned long start, unsigned long end)
+{
+ struct flush_icache_range_args args;
+
+ args.start = start;
+ args.end = end;
+ smp_call_function(sb1_flush_icache_range_ipi, &args, 1, 1);
+ local_sb1_flush_icache_range(start, end);
+}
+#else
+asm("sb1_flush_icache_range = local_sb1_flush_icache_range");
+#endif
+
/*
* If there's no context yet, or the page isn't executable, no icache flush
* is needed
@@ -304,7 +334,7 @@
* but things that "seem to work" when I don't understand *why* they
* "seem to work" disturb me greatly...JDC
*/
-static void sb1_flush_cache_sigtramp(unsigned long addr)
+static void local_sb1_flush_cache_sigtramp(unsigned long addr)
{
unsigned long daddr, iaddr;
@@ -316,6 +346,45 @@
protected_flush_icache_line(iaddr + icache_line_size);
}
+#ifdef CONFIG_SMP
+extern void sb1_flush_cache_sigtramp_ipi(void *ignored);
+asm("sb1_flush_cache_sigtramp_ipi = local_sb1_flush_cache_sigtramp");
+
+static void sb1_flush_cache_sigtramp(unsigned long addr)
+{
+ smp_call_function(sb1_flush_cache_sigtramp_ipi, (void *) addr, 1, 1);
+ local_sb1_flush_cache_sigtramp(addr);
+}
+#else
+asm("sb1_flush_cache_sigtramp = local_sb1_flush_cache_sigtramp");
+#endif
+
+static void sb1_flush_icache_all(void)
+{
+ /*
+ * Haven't worried too much about speed here; given that we're flushing
+ * the icache, the time to invalidate is dwarfed by the time it's going
+ * to take to refill it. Register usage:
+ *
+ * $1 - moving cache index
+ * $2 - set count
+ */
+ __asm__ __volatile__ (
+ ".set push \n"
+ ".set noreorder \n"
+ ".set noat \n"
+ ".set mips4 \n"
+ " move $1, %2 \n" /* Start at index 0 */
+ "1: cache %3, 0($1) \n" /* Invalidate this index */
+ " addiu %1, %1, -1 \n" /* Decrement loop count */
+ " bnez %1, 1b \n" /* loop test */
+ " addu $1, $1, %0 \n" /* Next address */
+ ".set pop \n"
+ :
+ : "r" (icache_line_size), "r" (icache_sets * icache_assoc),
+ "r" (KSEG0), "i" (Index_Invalidate_I));
+}
+
/*
* Anything that just flushes dcache state can be ignored, as we're always
* coherent in dcache space. This is just a dummy function that all the
@@ -416,7 +485,6 @@
icache_size = icache_line_size * icache_sets * icache_assoc;
dcache_size = dcache_line_size * dcache_sets * dcache_assoc;
icache_index_mask = (icache_sets - 1) * icache_line_size;
- tlb_entries = ((config1 >> 25) & 0x3f) + 1;
}
/*
@@ -432,16 +500,18 @@
_copy_page = sb1_copy_page;
_flush_cache_all = sb1_flush_cache_all;
- ___flush_cache_all = sb1_flush_cache_all;
+ ___flush_cache_all = sb1___flush_cache_all;
_flush_cache_mm = (void (*)(struct mm_struct *))sb1_nop;
_flush_cache_range = (void (*)(struct mm_struct *, unsigned long, unsigned long))sb1_nop;
_flush_page_to_ram = sb1_flush_page_to_ram;
_flush_icache_page = sb1_flush_icache_page;
- _flush_cache_sigtramp = sb1_flush_cache_sigtramp;
_flush_icache_range = sb1_flush_icache_range;
/* None of these are needed for the sb1 */
_flush_cache_page = (void (*)(struct vm_area_struct *, unsigned long))sb1_nop;
+
+ _flush_cache_sigtramp = sb1_flush_cache_sigtramp;
+ _flush_icache_all = sb1_flush_icache_all;
/* JDCXXX I'm not sure whether these are necessary: is this the right
place to initialize the tlb? If it is, why is it done
|
|
From: James S. <jsi...@us...> - 2001-11-26 18:31:27
|
Update of /cvsroot/linux-mips/linux/arch/mips
In directory usw-pr-cvs1:/tmp/cvs-serv9534
Modified Files:
config.in defconfig
Log Message:
Config changes for IP22 timer updates were missing; this gets it to compile again.
Index: config.in
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/config.in,v
retrieving revision 1.53
retrieving revision 1.54
diff -u -d -r1.53 -r1.54
--- config.in 2001/11/22 01:19:24 1.53
+++ config.in 2001/11/26 18:31:24 1.54
@@ -61,17 +61,6 @@
int ' Maximum memory chunks' CONFIG_SIBYTE_SWARM_MAX_MEM_REGIONS 16
bool ' Multi-Processing support' CONFIG_SMP
fi
- if [ "$CONFIG_BLK_DEV_INITRD" = "y" ]; then
- bool ' Embed root filesystem ramdisk into the kernel' CONFIG_EMBEDDED_RAMDISK
- if [ "$CONFIG_EMBEDDED_RAMDISK" = "y" ]; then
- choice ' Ramdisk Image to use for root filesystem' \
- "Simple-init CONFIG_SIBYTE_RAMDISK_SIMPLE_INIT \
- General CONFIG_SIBYTE_RAMDISK_GENERAL \
- Promice-console CONFIG_SIBYTE_RAMDISK_PROMICE_CONSOLE\
- N+I-demo CONFIG_SIBYTE_RAMDISK_NIDEMO\
- Screening CONFIG_SIBYTE_RAMDISK_SCREENING" General
- fi
- fi
fi
fi
bool 'Support for Sony PlayStation 2' CONFIG_PS2
@@ -87,14 +76,14 @@
bool 'Support for SGI IP22' CONFIG_SGI_IP22
bool 'Support for SNI RM200 PCI' CONFIG_SNI_RM200_PCI
bool 'Support for ITE 8172G board' CONFIG_MIPS_ITE8172
- if [ "$CONFIG_MIPS_ITE8172" = "y" ]; then
- bool ' Support for older IT8172 (Rev C)' CONFIG_IT8172_REVC
- fi
- bool 'Support for Globespan IVR board' CONFIG_MIPS_IVR
+if [ "$CONFIG_MIPS_ITE8172" = "y" ]; then
+ bool ' Support for older IT8172 (Rev C)' CONFIG_IT8172_REVC
+fi
+bool 'Support for Globespan IVR board' CONFIG_MIPS_IVR
bool 'Support for Alchemy Semi PB1000 board' CONFIG_MIPS_PB1000
- if [ "$CONFIG_MIPS_PB1000" = "y" ]; then
- bool ' Support for PCI AUTO Config' CONFIG_PCI_AUTO
- fi
+if [ "$CONFIG_MIPS_PB1000" = "y" ]; then
+ bool ' Support for PCI AUTO Config' CONFIG_PCI_AUTO
+fi
bool 'Support for Hewlett Packard LaserJet board' CONFIG_HP_LASERJET
bool 'Support for Toshiba JMR-TX3927 board' CONFIG_TOSHIBA_JMR3927
@@ -106,7 +95,6 @@
#
unset CONFIG_ARC32
unset CONFIG_BOARD_SCACHE
-unset CONFIG_COHERENT_IO
unset CONFIG_HAVE_STD_PC_SERIAL_PORT
unset CONFIG_I8259
unset CONFIG_ISA
@@ -120,7 +108,6 @@
define_bool CONFIG_SBUS n
if [ "$CONFIG_SIBYTE_SB1250" = "y" ]; then
- define_bool CONFIG_COHERENT_IO y
define_bool CONFIG_NEW_IRQ y
define_bool CONFIG_PCI n
define_bool CONFIG_SWAP_IO_SPACE y
@@ -131,17 +118,20 @@
define_bool CONFIG_MIPS_GT96100 y
define_bool CONFIG_SWAP_IO_SPACE y
define_bool CONFIG_NEW_PCI y
+ define_bool CONFIG_NONCOHERENT_IO y
define_bool CONFIG_PCI_AUTO y
fi
if [ "$CONFIG_MIPS_EV64120" = "y" ]; then
define_bool CONFIG_PCI y
define_bool CONFIG_ISA n
define_bool CONFIG_MIPS_GT64120 y
+ define_bool CONFIG_NONCOHERENT_IO y
define_bool CONFIG_OLD_TIME_C y
fi
if [ "$CONFIG_ALGOR_P4032" = "y" ]; then
define_bool CONFIG_PCI y
+ define_bool CONFIG_NONCOHERENT_IO y
define_bool CONFIG_OLD_TIME_C y
fi
if [ "$CONFIG_MIPS_MAGNUM_4000" = "y" -o \
@@ -152,6 +142,7 @@
define_bool CONFIG_FB y
define_bool CONFIG_FB_G364 y
define_bool CONFIG_MIPS_JAZZ y
+ define_bool CONFIG_NONCOHERENT_IO y
define_bool CONFIG_PC_KEYB y
define_bool CONFIG_OLD_TIME_C y
fi
@@ -165,6 +156,7 @@
define_bool CONFIG_OLD_TIME_C y
fi
if [ "$CONFIG_MIPS_ATLAS" = "y" ]; then
+ define_bool CONFIG_NONCOHERENT_IO y
define_bool CONFIG_PCI y
define_bool CONFIG_SWAP_IO_SPACE y
fi
@@ -173,6 +165,7 @@
define_bool CONFIG_PCI y
define_bool CONFIG_HAVE_STD_PC_SERIAL_PORT y
define_bool CONFIG_NEW_IRQ y
+ define_bool CONFIG_NONCOHERENT_IO y
define_bool CONFIG_SWAP_IO_SPACE y
fi
if [ "$CONFIG_MOMENCO_OCELOT" = "y" ]; then
@@ -180,32 +173,37 @@
define_bool CONFIG_SYSCLK_100 y
define_bool CONFIG_SWAP_IO_SPACE y
define_bool CONFIG_NEW_IRQ y
+ define_bool CONFIG_NONCOHERENT_IO y
define_bool CONFIG_NEW_TIME_C y
fi
if [ "$CONFIG_SGI_IP22" = "y" ]; then
define_bool CONFIG_ARC32 y
define_bool CONFIG_BOARD_SCACHE y
+ define_bool CONFIG_IRQ_CPU y
define_bool CONFIG_PC_KEYB y
define_bool CONFIG_SGI y
define_bool CONFIG_NEW_IRQ y
- define_bool CONFIG_OLD_TIME_C y
+ define_bool CONFIG_NEW_TIME_C y
+ define_bool CONFIG_NONCOHERENT_IO y
fi
if [ "$CONFIG_SNI_RM200_PCI" = "y" ]; then
define_bool CONFIG_ARC32 y
define_bool CONFIG_I8259 y
define_bool CONFIG_ISA y
define_bool CONFIG_NEW_IRQ y
+ define_bool CONFIG_NONCOHERENT_IO y
+ define_bool CONFIG_OLD_TIME_C y
define_bool CONFIG_PC_KEYB y
define_bool CONFIG_PCI y
- define_bool CONFIG_OLD_TIME_C y
fi
if [ "$CONFIG_DDB5074" = "y" ]; then
+ define_bool CONFIG_HAVE_STD_PC_SERIAL_PORT y
define_bool CONFIG_I8259 y
define_bool CONFIG_ISA y
+ define_bool CONFIG_NONCOHERENT_IO y
define_bool CONFIG_PCI y
define_bool CONFIG_PC_KEYB y
define_bool CONFIG_ROTTEN_IRQ y
- define_bool CONFIG_HAVE_STD_PC_SERIAL_PORT y
define_bool CONFIG_OLD_TIME_C y
fi
if [ "$CONFIG_DDB5476" = "y" ]; then
@@ -219,6 +217,7 @@
define_bool CONFIG_NEW_PCI y
define_bool CONFIG_PCI_AUTO y
define_bool CONFIG_NEW_TIME_C y
+ define_bool CONFIG_NONCOHERENT_IO y
fi
if [ "$CONFIG_DDB5477" = "y" ]; then
define_bool CONFIG_PCI y
@@ -226,6 +225,7 @@
define_bool CONFIG_NEW_IRQ y
define_bool CONFIG_IRQ_CPU y
define_bool CONFIG_NEW_PCI y
+ define_bool CONFIG_NONCOHERENT_IO y
define_bool CONFIG_PCI_AUTO y
define_bool CONFIG_DUMMY_KEYB y
fi
@@ -237,6 +237,7 @@
define_bool CONFIG_NEW_IRQ y
define_bool CONFIG_IRQ_CPU y
define_bool CONFIG_NEW_TIME_C y
+ define_bool CONFIG_NONCOHERENT_IO y
define_bool CONFIG_DUMMY_KEYB y
define_bool CONFIG_SCSI n
fi
@@ -246,6 +247,7 @@
define_bool CONFIG_VRC4173 y
define_bool CONFIG_NEW_IRQ y
define_bool CONFIG_NEW_TIME_C y
+ define_bool CONFIG_NONCOHERENT_IO y
define_bool CONFIG_DUMMY_KEYB y
define_bool CONFIG_PCI y
fi
@@ -255,6 +257,7 @@
define_bool CONFIG_SERIAL_MANY_PORTS y
define_bool CONFIG_NEW_IRQ y
define_bool CONFIG_NEW_TIME_C y
+ define_bool CONFIG_NONCOHERENT_IO y
define_bool CONFIG_SCSI n
fi
if [ "$CONFIG_MIPS_ITE8172" = "y" ]; then
@@ -262,6 +265,7 @@
define_bool CONFIG_IT8712 y
define_bool CONFIG_PC_KEYB y
define_bool CONFIG_NEW_PCI y
+ define_bool CONFIG_NONCOHERENT_IO y
define_bool CONFIG_PCI_AUTO y
define_bool CONFIG_IT8172_CIR y
define_bool CONFIG_NEW_IRQ y
@@ -271,6 +275,7 @@
define_bool CONFIG_PCI y
define_bool CONFIG_PC_KEYB y
define_bool CONFIG_NEW_PCI y
+ define_bool CONFIG_NONCOHERENT_IO y
define_bool CONFIG_PCI_AUTO y
define_bool CONFIG_IT8172_CIR y
define_bool CONFIG_NEW_IRQ y
@@ -281,6 +286,7 @@
define_bool CONFIG_NEW_IRQ y
define_bool CONFIG_PCI y
define_bool CONFIG_NEW_PCI y
+ define_bool CONFIG_NONCOHERENT_IO y
define_bool CONFIG_PC_KEYB y
define_int MAX_HWIFS 1
fi
@@ -294,6 +300,7 @@
define_bool CONFIG_PCI y
# define_bool CONFIG_NEW_PCI y
# define_bool CONFIG_PCI_AUTO y
+ define_bool CONFIG_NONCOHERENT_IO y
define_bool CONFIG_OLD_TIME_C y
fi
if [ "$CONFIG_VADEM_CLIO_1000" = "y" ]; then
@@ -310,6 +317,7 @@
if [ "$CONFIG_NINO" = "y" ]; then
define_bool CONFIG_NEW_IRQ y
define_bool CONFIG_NEW_TIME_C y
+ define_bool CONFIG_NONCOHERENT_IO y
define_bool CONFIG_PC_KEYB y
fi
if [ "$CONFIG_PS2" = "y" ]; then
@@ -329,15 +337,19 @@
define_bool CONFIG_VRC4173 y
define_bool CONFIG_NEW_IRQ y
define_bool CONFIG_NEW_TIME_C y
+ define_bool CONFIG_NONCOHERENT_IO y
define_bool CONFIG_DUMMY_KEYB y
define_bool CONFIG_PCI y
fi
if [ "$CONFIG_HP_LASERJET" = "y" ]; then
define_bool CONFIG_PCI y
+ define_bool CONFIG_IRQ_CPU y
define_bool CONFIG_NEW_TIME_C y
define_bool CONFIG_NEW_IRQ y
define_bool CONFIG_IRQ_CPU y
define_bool CONFIG_NEW_PCI y
+ define_bool CONFIG_NONCOHERENT_IO y
+ define_bool CONFIG_PCI y
#not yet define_bool CONFIG_PCI_AUTO y
fi
if [ "$CONFIG_TOSHIBA_JMR3927" = "y" ]; then
@@ -400,6 +412,7 @@
if [ "$CONFIG_CPU_SB1" = "y" ]; then
bool ' Workarounds for pass 1 sb1 bugs' CONFIG_SB1_PASS_1_WORKAROUNDS
bool ' Support for SB1 Cache Error handler' CONFIG_SB1_CACHE_ERROR
+ define_bool CONFIG_VTAG_ICACHE y
fi
bool 'Override CPU Options' CONFIG_CPU_ADVANCED
@@ -501,6 +514,9 @@
source drivers/parport/Config.in
source drivers/block/Config.in
+if [ "$CONFIG_BLK_DEV_INITRD" = "y" ]; then
+ bool ' Embed root filesystem ramdisk into the kernel' CONFIG_EMBEDDED_RAMDISK
+fi
source drivers/md/Config.in
Index: defconfig
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/defconfig,v
retrieving revision 1.15
retrieving revision 1.16
diff -u -d -r1.15 -r1.16
--- defconfig 2001/11/19 18:31:01 1.15
+++ defconfig 2001/11/26 18:31:24 1.16
@@ -2,7 +2,6 @@
# Automatically generated make config: don't edit
#
CONFIG_MIPS=y
-# CONFIG_SMP is not set
#
# Code maturity level options
@@ -15,7 +14,6 @@
# CONFIG_ACER_PICA_61 is not set
# CONFIG_ALGOR_P4032 is not set
# CONFIG_BAGET_MIPS is not set
-# CONFIG_COBALT_MICRO_SERVER is not set
# CONFIG_DECSTATION is not set
# CONFIG_DDB5074 is not set
# CONFIG_MIPS_EV96100 is not set
@@ -24,20 +22,18 @@
# CONFIG_MIPS_MALTA is not set
# CONFIG_NINO is not set
# CONFIG_SIBYTE_SB1250 is not set
-# CONFIG_PS2 is not set
# CONFIG_MIPS_MAGNUM_4000 is not set
# CONFIG_MOMENCO_OCELOT is not set
# CONFIG_DDB5476 is not set
# CONFIG_DDB5477 is not set
# CONFIG_NEC_OSPREY is not set
-# CONFIG_NEC_EAGLE is not set
-# CONFIG_NEC_KORVA is not set
# CONFIG_OLIVETTI_M700 is not set
CONFIG_SGI_IP22=y
# CONFIG_SNI_RM200_PCI is not set
# CONFIG_MIPS_ITE8172 is not set
# CONFIG_MIPS_IVR is not set
# CONFIG_MIPS_PB1000 is not set
+# CONFIG_TOSHIBA_JMR3927 is not set
# CONFIG_HP_LASERJET is not set
CONFIG_RWSEM_GENERIC_SPINLOCK=y
# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
@@ -45,10 +41,12 @@
# CONFIG_SBUS is not set
CONFIG_ARC32=y
CONFIG_BOARD_SCACHE=y
+CONFIG_IRQ_CPU=y
CONFIG_PC_KEYB=y
CONFIG_SGI=y
CONFIG_NEW_IRQ=y
-CONFIG_OLD_TIME_C=y
+CONFIG_NEW_TIME_C=y
+CONFIG_NONCOHERENT_IO=y
# CONFIG_ISA is not set
# CONFIG_EISA is not set
# CONFIG_PCI is not set
@@ -73,7 +71,6 @@
# CONFIG_CPU_TX49XX is not set
CONFIG_CPU_R5000=y
# CONFIG_CPU_R5432 is not set
-# CONFIG_CPU_R5900 is not set
# CONFIG_CPU_RM7000 is not set
# CONFIG_CPU_NEVADA is not set
# CONFIG_CPU_R10000 is not set
@@ -250,7 +247,6 @@
# CONFIG_SCSI_INITIO is not set
# CONFIG_SCSI_INIA100 is not set
# CONFIG_SCSI_NCR53C406A is not set
-# CONFIG_SCSI_NCR_D700 is not set
# CONFIG_SCSI_NCR53C7xx is not set
# CONFIG_SCSI_PAS16 is not set
# CONFIG_SCSI_PCI2000 is not set
@@ -399,7 +395,6 @@
# CONFIG_DTLK is not set
# CONFIG_R3964 is not set
# CONFIG_APPLICOM is not set
-# CONFIG_SONYPI is not set
#
# Ftape, the floppy tape device driver
|
|
From: James S. <jsi...@us...> - 2001-11-26 18:17:41
|
Update of /cvsroot/linux-mips/linux/arch/mips/sgi/kernel
In directory usw-pr-cvs1:/tmp/cvs-serv4706/arch/mips/sgi/kernel
Modified Files:
indy_int.c
Added Files:
Makefile indy_rtc.c indy_time.c setup.c
Log Message:
RTC fixes for SGI systems.
--- NEW FILE: Makefile ---
#
# Makefile for the SGI specific kernel interface routines
# under Linux.
#
# Note! Dependencies are done automagically by 'make dep', which also
# removes any old dependencies. DON'T put your own dependencies here
# unless it's something special (ie not a .c file).
#
# Note 2! The CFLAGS definitions are now in the main makefile...
.S.s:
$(CPP) $(CFLAGS) $< -o $*.s
.S.o:
$(CC) $(CFLAGS) -c $< -o $*.o
O_TARGET := ip22-kern.o
all: ip22-kern.o indyIRQ.o
obj-y += indy_mc.o indy_sc.o indy_hpc.o indy_int.o indy_time.o indy_rtc.o \
system.o indyIRQ.o reset.o setup.o
indyIRQ.o: indyIRQ.S
include $(TOPDIR)/Rules.make
--- NEW FILE: indy_time.c ---
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Time operations for IP22 machines. Original code may come from
* Ralf Baechle or David S. Miller (sorry guys, i'm really not sure)
*
* Copyright (C) 2001 by Ladislav Michl
*/
#include <linux/config.h>
#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/kernel_stat.h>
#include <asm/cpu.h>
#include <asm/mipsregs.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/time.h>
#include <asm/ds1286.h>
#include <asm/sgialib.h>
#include <asm/sgi/sgint23.h>
/*
* note that mktime uses month from 1 to 12 while to_tm
* uses 0 to 11. ask Jun Sun why!
*/
static unsigned long indy_rtc_get_time(void)
{
unsigned char yrs, mon, day, hrs, min, sec;
unsigned char save_control;
save_control = CMOS_READ(RTC_CMD);
CMOS_WRITE((save_control|RTC_TE), RTC_CMD);
sec = CMOS_READ(RTC_SECONDS);
min = CMOS_READ(RTC_MINUTES);
hrs = CMOS_READ(RTC_HOURS) & 0x1f;
day = CMOS_READ(RTC_DATE);
mon = CMOS_READ(RTC_MONTH) & 0x1f;
yrs = CMOS_READ(RTC_YEAR);
CMOS_WRITE(save_control, RTC_CMD);
BCD_TO_BIN(sec);
BCD_TO_BIN(min);
BCD_TO_BIN(hrs);
BCD_TO_BIN(day);
BCD_TO_BIN(mon);
BCD_TO_BIN(yrs);
if (yrs < 45)
yrs += 30;
if ((yrs += 40) < 70)
yrs += 100;
return mktime((int)yrs + 1900, mon, day, hrs, min, sec);
}
static int indy_rtc_set_time(unsigned long tim)
{
struct rtc_time tm;
unsigned char save_control;
to_tm(tim, &tm);
tm.tm_year -= 1900;
tm.tm_mon += 1;
if (tm.tm_year >= 100)
tm.tm_year -= 100;
BIN_TO_BCD(tm.tm_sec);
BIN_TO_BCD(tm.tm_min);
BIN_TO_BCD(tm.tm_hour);
BIN_TO_BCD(tm.tm_mday);
BIN_TO_BCD(tm.tm_mon);
BIN_TO_BCD(tm.tm_year);
save_control = CMOS_READ(RTC_CMD);
CMOS_WRITE((save_control|RTC_TE), RTC_CMD);
CMOS_WRITE(tm.tm_year, RTC_YEAR);
CMOS_WRITE(tm.tm_mon, RTC_MONTH);
CMOS_WRITE(tm.tm_mday, RTC_DATE);
CMOS_WRITE(tm.tm_hour, RTC_HOURS);
CMOS_WRITE(tm.tm_min, RTC_MINUTES);
CMOS_WRITE(tm.tm_sec, RTC_SECONDS);
CMOS_WRITE(0, RTC_HUNDREDTH_SECOND);
CMOS_WRITE(save_control, RTC_CMD);
return 0;
}
static unsigned long dosample(volatile unsigned char *tcwp,
volatile unsigned char *tc2p)
{
unsigned long ct0, ct1;
unsigned char msb, lsb;
/* Start the counter. */
*tcwp = (SGINT_TCWORD_CNT2 | SGINT_TCWORD_CALL | SGINT_TCWORD_MRGEN);
*tc2p = (SGINT_TCSAMP_COUNTER & 0xff);
*tc2p = (SGINT_TCSAMP_COUNTER >> 8);
/* Get initial counter invariant */
ct0 = read_32bit_cp0_register(CP0_COUNT);
/* Latch and spin until top byte of counter2 is zero */
do {
*tcwp = (SGINT_TCWORD_CNT2 | SGINT_TCWORD_CLAT);
lsb = *tc2p;
msb = *tc2p;
ct1 = read_32bit_cp0_register(CP0_COUNT);
} while(msb);
/* Stop the counter. */
*tcwp = (SGINT_TCWORD_CNT2 | SGINT_TCWORD_CALL | SGINT_TCWORD_MSWST);
/*
* Return the difference, this is how far the r4k counter increments
* for every 1/HZ seconds. We round off the nearest 1 MHz of master
* clock (= 1000000 / 100 / 2 = 5000 count).
*/
return ((ct1 - ct0) / 5000) * 5000;
}
void indy_time_init(void)
{
/* Here we need to calibrate the cycle counter to at least be close.
* We don't need to actually register the irq handler because that's
* all done in indyIRQ.S.
*/
struct sgi_ioc_timers *p;
volatile unsigned char *tcwp, *tc2p;
unsigned long r4k_ticks[3];
unsigned long r4k_tick;
/* Figure out the r4k offset, the algorithm is very simple
* and works in _all_ cases as long as the 8254 counter
* register itself works ok (as an interrupt driving timer
* it does not because of bug, this is why we are using
* the onchip r4k counter/compare register to serve this
* purpose, but for r4k_offset calculation it will work
* ok for us). There are other very complicated ways
* of performing this calculation but this one works just
* fine so I am not going to futz around. ;-)
*/
p = ioc_timers;
tcwp = &p->tcword;
tc2p = &p->tcnt2;
printk("Calibrating system timer... ");
dosample(tcwp, tc2p); /* Prime cache. */
dosample(tcwp, tc2p); /* Prime cache. */
/* Zero is NOT an option. */
do {
r4k_ticks[0] = dosample (tcwp, tc2p);
} while (!r4k_ticks[0]);
do {
r4k_ticks[1] = dosample (tcwp, tc2p);
} while (!r4k_ticks[1]);
if (r4k_ticks[0] != r4k_ticks[1]) {
printk ("warning: timer counts differ, retrying...");
r4k_ticks[2] = dosample (tcwp, tc2p);
if (r4k_ticks[2] == r4k_ticks[0]
|| r4k_ticks[2] == r4k_ticks[1])
r4k_tick = r4k_ticks[2];
else {
printk ("disagreement, using average...");
r4k_tick = (r4k_ticks[0] + r4k_ticks[1]
+ r4k_ticks[2]) / 3;
}
} else
r4k_tick = r4k_ticks[0];
printk("%d [%d.%02d MHz CPU]\n", (int) r4k_tick,
(int) (r4k_tick / 5000), (int) (r4k_tick % 5000) / 50);
mips_counter_frequency = r4k_tick * HZ;
}
/* Generic SGI handler for (spurious) 8254 interrupts */
void indy_8254timer_irq(struct pt_regs *regs)
{
int cpu = smp_processor_id();
int irq = SGI_8254_0_IRQ;
irq_enter(cpu, irq);
kstat.irqs[cpu][irq]++;
printk("indy_8254timer_irq: Whoops, should not have gotten this IRQ\n");
prom_getchar();
ArcEnterInteractiveMode();
irq_exit(cpu, irq);
}
void indy_r4k_timer_interrupt(struct pt_regs *regs)
{
int cpu = smp_processor_id();
int irq = SGI_TIMER_IRQ;
irq_enter(cpu, irq);
kstat.irqs[cpu][irq]++;
timer_interrupt(irq, NULL, regs);
irq_exit(cpu, irq);
if (softirq_pending(cpu))
do_softirq();
}
extern int setup_irq(unsigned int irq, struct irqaction *irqaction);
static void indy_timer_setup(struct irqaction *irq)
{
/* over-write the handler. we use our own way */
irq->handler = no_action;
/* setup irqaction */
setup_irq(SGI_TIMER_IRQ, irq);
}
void sgitime_init(void)
{
/*
* setup hookup function only when Indy Dallas chip driver
* is included.
*/
rtc_get_time = indy_rtc_get_time;
rtc_set_time = indy_rtc_set_time;
board_time_init = indy_time_init;
board_timer_setup = indy_timer_setup;
}
Index: indy_int.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/sgi/kernel/indy_int.c,v
retrieving revision 1.4
retrieving revision 1.5
diff -u -d -r1.4 -r1.5
--- indy_int.c 2001/11/14 16:17:58 1.4
+++ indy_int.c 2001/11/26 18:17:36 1.5
@@ -7,54 +7,26 @@
* Copyright (C) 1999 Andrew R. Baker (an...@ua...)
* - Indigo2 changes
* - Interrupt handling fixes
+ * Copyright (C) 2001 Ladislav Michl (la...@ps...)
*/
-#include <linux/init.h>
-#include <linux/errno.h>
+#include <linux/types.h>
+#include <linux/init.h>
#include <linux/kernel_stat.h>
#include <linux/signal.h>
#include <linux/sched.h>
-#include <linux/types.h>
#include <linux/interrupt.h>
-#include <linux/ioport.h>
-#include <linux/timex.h>
-#include <linux/slab.h>
-#include <linux/random.h>
-#include <linux/smp.h>
-#include <linux/smp_lock.h>
-#include <asm/bitops.h>
-#include <asm/bootinfo.h>
-#include <asm/io.h>
#include <asm/irq.h>
#include <asm/mipsregs.h>
-#include <asm/system.h>
-
-#include <asm/ptrace.h>
-#include <asm/processor.h>
-#include <asm/sgi/sgi.h>
-#include <asm/sgi/sgihpc.h>
-#include <asm/sgi/sgint23.h>
-#include <asm/sgialib.h>
+#include <asm/addrspace.h>
#include <asm/gdb-stub.h>
-/*
- * Linux has a controller-independent x86 interrupt architecture.
- * every controller has a 'controller-template', that is used
- * by the main code to do the right thing. Each driver-visible
- * interrupt source is transparently wired to the apropriate
- * controller. Thus drivers need not be aware of the
- * interrupt-controller.
- *
- * Various interrupt controllers we handle: 8259 PIC, SMP IO-APIC,
- * PIIX4's internal 8259 PIC and SGI's Visual Workstation Cobalt (IO-)APIC.
- * (IO-APICs assumed to be messaging to Pentium local-APICs)
- *
- * the code is designed to be easily extended with new/different
- * interrupt controllers, without having to do assembly magic.
- */
+#include <asm/sgi/sgint23.h>
+#include <asm/sgi/sgihpc.h>
/* #define DEBUG_SGINT */
+#undef I_REALLY_NEED_THIS_IRQ
struct sgi_int2_regs *sgi_i2regs;
struct sgi_int3_regs *sgi_i3regs;
@@ -68,30 +40,23 @@
static char lc3msk_to_irqnr[256];
extern asmlinkage void indyIRQ(void);
-
-/* Local IRQ's are layed out logically like this:
- *
- * 0 --> 7 == local 0 interrupts
- * 8 --> 15 == local 1 interrupts
- * 16 --> 23 == vectored level 2 interrupts
- * 24 --> 31 == vectored level 3 interrupts (not used)
- * 32 --> 40 == vectored GIO interrupts
- * 41 --> 52 == vectored HPCDMA interrupts
- */
+extern void do_IRQ(int irq, struct pt_regs *regs);
static void enable_local0_irq(unsigned int irq)
{
unsigned long flags;
save_and_cli(flags);
- ioc_icontrol->imask0 |= (1 << (irq - SGINT_LOCAL0));
+ /* don't allow mappable interrupt to be enabled from setup_irq,
+ * we have our own way to do so */
+ if (irq != SGI_MAP_0_IRQ)
+ ioc_icontrol->imask0 |= (1 << (irq - SGINT_LOCAL0));
restore_flags(flags);
}
static unsigned int startup_local0_irq(unsigned int irq)
{
enable_local0_irq(irq);
-
return 0; /* Never anything pending */
}
@@ -129,14 +94,16 @@
unsigned long flags;
save_and_cli(flags);
- ioc_icontrol->imask1 |= (1 << (irq - SGINT_LOCAL1));
+ /* don't allow mappable interrupt to be enabled from setup_irq,
+ * we have our own way to do so */
+ if (irq != SGI_MAP_1_IRQ)
+ ioc_icontrol->imask1 |= (1 << (irq - SGINT_LOCAL1));
restore_flags(flags);
}
static unsigned int startup_local1_irq(unsigned int irq)
{
enable_local1_irq(irq);
-
return 0; /* Never anything pending */
}
@@ -145,7 +112,7 @@
unsigned long flags;
save_and_cli(flags);
- ioc_icontrol->imask1 &= ~(1 << (irq- SGINT_LOCAL1));
+ ioc_icontrol->imask1 &= ~(1 << (irq - SGINT_LOCAL1));
restore_flags(flags);
}
@@ -174,7 +141,7 @@
unsigned long flags;
save_and_cli(flags);
- enable_local0_irq(7);
+ ioc_icontrol->imask0 |= (1 << (SGI_MAP_0_IRQ - SGINT_LOCAL0));
ioc_icontrol->cmeimask0 |= (1 << (irq - SGINT_LOCAL2));
restore_flags(flags);
}
@@ -182,7 +149,6 @@
static unsigned int startup_local2_irq(unsigned int irq)
{
enable_local2_irq(irq);
-
return 0; /* Never anything pending */
}
@@ -192,6 +158,8 @@
save_and_cli(flags);
ioc_icontrol->cmeimask0 &= ~(1 << (irq - SGINT_LOCAL2));
+ if (!ioc_icontrol->cmeimask0)
+ ioc_icontrol->imask0 &= ~(1 << (SGI_MAP_0_IRQ - SGINT_LOCAL0));
restore_flags(flags);
}
@@ -217,18 +185,21 @@
static void enable_local3_irq(unsigned int irq)
{
+#ifdef I_REALLY_NEED_THIS_IRQ
unsigned long flags;
-
+
save_and_cli(flags);
- printk("Yeeee, got passed irq_nr %d at enable_local3_irq\n", irq);
- panic("Invalid IRQ level!");
+ ioc_icontrol->imask1 |= (1 << (SGI_MAP_1_IRQ - SGINT_LOCAL1));
+ ioc_icontrol->cmeimask1 |= (1 << (irq - SGINT_LOCAL3));
restore_flags(flags);
+#else
+ panic("Who need local 3 irq? see indy_int.c\n");
+#endif
}
static unsigned int startup_local3_irq(unsigned int irq)
{
enable_local3_irq(irq);
-
return 0; /* Never anything pending */
}
@@ -237,12 +208,9 @@
unsigned long flags;
save_and_cli(flags);
- /*
- * This way we'll see if anyone would ever want vectored level 3
- * interrupts. Highly unlikely.
- */
- printk("Yeeee, got passed irq_nr %d at disable_local3_irq\n", irq);
- panic("Invalid IRQ level!");
+ ioc_icontrol->cmeimask1 &= ~(1 << (irq - SGINT_LOCAL3));
+ if (!ioc_icontrol->cmeimask1)
+ ioc_icontrol->imask1 &= ~(1 << (SGI_MAP_1_IRQ - SGINT_LOCAL1));
restore_flags(flags);
}
@@ -266,80 +234,6 @@
NULL
};
-void enable_gio_irq(unsigned int irq)
-{
- /* XXX TODO XXX */
-}
-
-static unsigned int startup_gio_irq(unsigned int irq)
-{
- enable_gio_irq(irq);
-
- return 0; /* Never anything pending */
-}
-
-void disable_gio_irq(unsigned int irq)
-{
- /* XXX TODO XXX */
-}
-
-#define shutdown_gio_irq disable_gio_irq
-#define mask_and_ack_gio_irq disable_gio_irq
-
-static void end_gio_irq (unsigned int irq)
-{
- if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
- enable_gio_irq(irq);
-}
-
-static struct hw_interrupt_type ip22_gio_irq_type = {
- "IP22 GIO",
- startup_gio_irq,
- shutdown_gio_irq,
- enable_gio_irq,
- disable_gio_irq,
- mask_and_ack_gio_irq,
- end_gio_irq,
- NULL
-};
-
-void enable_hpcdma_irq(unsigned int irq)
-{
- /* XXX TODO XXX */
-}
-
-static unsigned int startup_hpcdma_irq(unsigned int irq)
-{
- enable_hpcdma_irq(irq);
-
- return 0; /* Never anything pending */
-}
-
-void disable_hpcdma_irq(unsigned int irq)
-{
- /* XXX TODO XXX */
-}
-
-#define shutdown_hpcdma_irq disable_hpcdma_irq
-#define mask_and_ack_hpcdma_irq disable_hpcdma_irq
-
-static void end_hpcdma_irq (unsigned int irq)
-{
- if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
- enable_hpcdma_irq(irq);
-}
-
-static struct hw_interrupt_type ip22_hpcdma_irq_type = {
- "IP22 HPC DMA",
- startup_hpcdma_irq,
- shutdown_hpcdma_irq,
- enable_hpcdma_irq,
- disable_hpcdma_irq,
- mask_and_ack_hpcdma_irq,
- end_hpcdma_irq,
- NULL
-};
-
void indy_local0_irqdispatch(struct pt_regs *regs)
{
unsigned char mask = ioc_icontrol->istat0;
@@ -369,16 +263,17 @@
mask &= ioc_icontrol->imask1;
if (mask & ISTAT1_LIO3) {
- printk("WHee: Got an LIO3 irq, winging it...\n");
+#ifndef I_REALLY_NEED_THIS_IRQ
+ printk("Whee: Got an LIO3 irq, winging it...\n");
+#endif
mask2 = ioc_icontrol->vmeistat;
mask2 &= ioc_icontrol->cmeimask1;
- irq = lc3msk_to_irqnr[ioc_icontrol->vmeistat];
+ irq = lc3msk_to_irqnr[mask2];
} else {
irq = lc1msk_to_irqnr[mask];
}
/* if irq == 0, then the interrupt has already been cleared */
- /* not sure if it is needed here, but it is needed for local0 */
if (irq)
do_IRQ(irq, regs);
return;
@@ -387,16 +282,33 @@
void indy_buserror_irq(struct pt_regs *regs)
{
int cpu = smp_processor_id();
- int irq = 6;
+ int irq = SGI_BUSERR_IRQ;
irq_enter(cpu, irq);
- kstat.irqs[0][irq]++;
+ kstat.irqs[cpu][irq]++;
die("Got a bus error IRQ, shouldn't happen yet\n", regs);
printk("Spinning...\n");
while(1);
irq_exit(cpu, irq);
}
+static struct irqaction local0_cascade =
+ { no_action, SA_INTERRUPT, 0, "local0 cascade", NULL, NULL };
+static struct irqaction local1_cascade =
+ { no_action, SA_INTERRUPT, 0, "local1 cascade", NULL, NULL };
+static struct irqaction buserr =
+ { no_action, SA_INTERRUPT, 0, "Bus Error", NULL, NULL };
+static struct irqaction map0_cascade =
+ { no_action, SA_INTERRUPT, 0, "mappable0 cascade", NULL, NULL };
+#ifdef I_REALLY_NEED_THIS_IRQ
+static struct irqaction map1_cascade =
+ { no_action, SA_INTERRUPT, 0, "mappable1 cascade", NULL, NULL };
+#endif
+
+extern int setup_irq(unsigned int irq, struct irqaction *irqaction);
+extern void mips_cpu_irq_init(u32 irq_base);
+extern void init_generic_irq(void);
+
void __init init_IRQ(void)
{
int i;
@@ -407,45 +319,45 @@
/* Init local mask --> irq tables. */
for (i = 0; i < 256; i++) {
if (i & 0x80) {
- lc0msk_to_irqnr[i] = 7;
- lc1msk_to_irqnr[i] = 15;
- lc2msk_to_irqnr[i] = 23;
- lc3msk_to_irqnr[i] = 31;
+ lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 7;
+ lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 7;
+ lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 7;
+ lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 7;
} else if (i & 0x40) {
- lc0msk_to_irqnr[i] = 6;
- lc1msk_to_irqnr[i] = 14;
- lc2msk_to_irqnr[i] = 22;
- lc3msk_to_irqnr[i] = 30;
+ lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 6;
+ lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 6;
+ lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 6;
+ lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 6;
} else if (i & 0x20) {
- lc0msk_to_irqnr[i] = 5;
- lc1msk_to_irqnr[i] = 13;
- lc2msk_to_irqnr[i] = 21;
- lc3msk_to_irqnr[i] = 29;
+ lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 5;
+ lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 5;
+ lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 5;
+ lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 5;
} else if (i & 0x10) {
- lc0msk_to_irqnr[i] = 4;
- lc1msk_to_irqnr[i] = 12;
- lc2msk_to_irqnr[i] = 20;
- lc3msk_to_irqnr[i] = 28;
+ lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 4;
+ lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 4;
+ lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 4;
+ lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 4;
} else if (i & 0x08) {
- lc0msk_to_irqnr[i] = 3;
- lc1msk_to_irqnr[i] = 11;
- lc2msk_to_irqnr[i] = 19;
- lc3msk_to_irqnr[i] = 27;
+ lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 3;
+ lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 3;
+ lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 3;
+ lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 3;
} else if (i & 0x04) {
- lc0msk_to_irqnr[i] = 2;
- lc1msk_to_irqnr[i] = 10;
- lc2msk_to_irqnr[i] = 18;
- lc3msk_to_irqnr[i] = 26;
+ lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 2;
+ lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 2;
+ lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 2;
+ lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 2;
} else if (i & 0x02) {
- lc0msk_to_irqnr[i] = 1;
- lc1msk_to_irqnr[i] = 9;
- lc2msk_to_irqnr[i] = 17;
- lc3msk_to_irqnr[i] = 25;
+ lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 1;
+ lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 1;
+ lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 1;
+ lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 1;
} else if (i & 0x01) {
- lc0msk_to_irqnr[i] = 0;
- lc1msk_to_irqnr[i] = 8;
- lc2msk_to_irqnr[i] = 16;
- lc3msk_to_irqnr[i] = 24;
+ lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 0;
+ lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 0;
+ lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 0;
+ lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 0;
} else {
lc0msk_to_irqnr[i] = 0;
lc1msk_to_irqnr[i] = 0;
@@ -474,6 +386,8 @@
set_except_vector(0, indyIRQ);
init_generic_irq();
+ /* init CPU irqs */
+ mips_cpu_irq_init(SGINT_CPU);
for (i = SGINT_LOCAL0; i < SGINT_END; i++) {
hw_irq_controller *handler;
@@ -484,16 +398,23 @@
handler = &ip22_local1_irq_type;
else if (i < SGINT_LOCAL3)
handler = &ip22_local2_irq_type;
- else if (i < SGINT_GIO)
+ else
handler = &ip22_local3_irq_type;
- else if (i < SGINT_HPCDMA)
- handler = &ip22_gio_irq_type;
- else if (i < SGINT_END)
- handler = &ip22_hpcdma_irq_type;
irq_desc[i].status = IRQ_DISABLED;
irq_desc[i].action = 0;
irq_desc[i].depth = 1;
irq_desc[i].handler = handler;
}
+
+ /* vector handler. this register the IRQ as non-sharable */
+ setup_irq(SGI_LOCAL_0_IRQ, &local0_cascade);
+ setup_irq(SGI_LOCAL_1_IRQ, &local1_cascade);
+ setup_irq(SGI_BUSERR_IRQ, &buserr);
+
+ /* cascade in cascade. i love Indy ;-) */
+ setup_irq(SGI_MAP_0_IRQ, &map0_cascade);
+#ifdef I_REALLY_NEED_THIS_IRQ
+ setup_irq(SGI_MAP_1_IRQ, &map1_cascade);
+#endif
}
|
|
From: James S. <jsi...@us...> - 2001-11-26 18:17:40
|
Update of /cvsroot/linux-mips/linux/include/asm-mips/sgi
In directory usw-pr-cvs1:/tmp/cvs-serv4706/include/asm-mips/sgi
Modified Files:
sgint23.h
Log Message:
RTC fixes for SGI systems.
Index: sgint23.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/sgi/sgint23.h,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- sgint23.h 2001/10/08 16:33:04 1.3
+++ sgint23.h 2001/11/26 18:17:36 1.4
@@ -8,100 +8,127 @@
* Copyright (C) 1996 David S. Miller (dm...@en...)
* Copyright (C) 1997, 98, 1999, 2000 Ralf Baechle
* Copyright (C) 1999 Andrew R. Baker (an...@ua...) - INT2 corrections
+ * Copyright (C) 2001 Ladislav Michl (la...@ps...)
*/
#ifndef _ASM_SGI_SGINT23_H
#define _ASM_SGI_SGINT23_H
/* These are the virtual IRQ numbers, we divide all IRQ's into
* 'spaces', the 'space' determines where and how to enable/disable
- * that particular IRQ on an SGI machine. Add new 'spaces' as new
- * IRQ hardware is supported.
+ * that particular IRQ on an SGI machine. HPC DMA and MC DMA interrups
+ * are not supported this way. Driver is supposed to allocate HPC/MC
+ * interrupt as shareable and then look to proper status bit (see
+ * HAL2 driver). This will prevent many complications, trust me ;-)
+ * --ladis
*/
-#define SGINT_LOCAL0 0 /* INDY has 8 local0 irq levels */
-#define SGINT_LOCAL1 8 /* INDY has 8 local1 irq levels */
-#define SGINT_LOCAL2 16 /* INDY has 8 local2 vectored irq levels */
-#define SGINT_LOCAL3 24 /* INDY has 8 local3 vectored irq levels */
-#define SGINT_GIO 32 /* INDY has 9 GIO irq levels */
-#define SGINT_HPCDMA 41 /* INDY has 11 HPCDMA irq _sources_ */
-#define SGINT_END 52 /* End of 'spaces' */
+#define SGINT_CPU 0 /* MIPS CPU define 8 interrupt sources */
+#define SGINT_LOCAL0 8 /* INDY has 8 local0 irq levels */
+#define SGINT_LOCAL1 16 /* INDY has 8 local1 irq levels */
+#define SGINT_LOCAL2 24 /* INDY has 8 local2 vectored irq levels */
+#define SGINT_LOCAL3 32 /* INDY has 8 local3 vectored irq levels */
+#define SGINT_END 40 /* End of 'spaces' */
/*
* Individual interrupt definitions for the INDY and Indigo2
*/
-#define SGI_WD93_0_IRQ SGINT_LOCAL0 + 1 /* 1st onboard WD93 */
-#define SGI_WD93_1_IRQ SGINT_LOCAL0 + 2 /* 2nd onboard WD93 */
-#define SGI_ENET_IRQ SGINT_LOCAL0 + 3 /* onboard ethernet */
+#define SGI_SOFT_0_IRQ SGINT_CPU + 0
+#define SGI_SOFT_1_IRQ SGINT_CPU + 1
+#define SGI_LOCAL_0_IRQ SGINT_CPU + 2
+#define SGI_LOCAL_1_IRQ SGINT_CPU + 3
+#define SGI_8254_0_IRQ SGINT_CPU + 4
+#define SGI_8254_1_IRQ SGINT_CPU + 5
+#define SGI_BUSERR_IRQ SGINT_CPU + 6
+#define SGI_TIMER_IRQ SGINT_CPU + 7
-#define SGI_PANEL_IRQ SGINT_LOCAL1 + 1 /* front panel */
-#define SGI_VINO_IRQ SGINT_LOCAL1 + 6 /* Indy VINO */
+#define SGI_FIFO_IRQ SGINT_LOCAL0 + 0 /* FIFO full */
+#define SGI_GIO_0_IRQ SGI_FIFO_IRQ /* GIO-0 */
+#define SGI_WD93_0_IRQ SGINT_LOCAL0 + 1 /* 1st onboard WD93 */
+#define SGI_WD93_1_IRQ SGINT_LOCAL0 + 2 /* 2nd onboard WD93 */
+#define SGI_ENET_IRQ SGINT_LOCAL0 + 3 /* onboard ethernet */
+#define SGI_MCDMA_IRQ SGINT_LOCAL0 + 4 /* MC DMA done */
+#define SGI_PARPORT_IRQ SGINT_LOCAL0 + 5 /* Parallel port */
+#define SGI_GIO_1_IRQ SGINT_LOCAL0 + 6 /* GE / GIO-1 / 2nd-HPC */
+#define SGI_MAP_0_IRQ SGINT_LOCAL0 + 7 /* Mappable interrupt 0 */
-#define SGI_EISA_IRQ SGINT_LOCAL2 + 3 /* EISA interrupts */
+#define SGI_GPL0_IRQ SGINT_LOCAL1 + 0 /* General Purpose LOCAL1_N<0> */
+#define SGI_PANEL_IRQ SGINT_LOCAL1 + 1 /* front panel */
+#define SGI_GPL2_IRQ SGINT_LOCAL1 + 2 /* General Purpose LOCAL1_N<2> */
+#define SGI_MAP_1_IRQ SGINT_LOCAL1 + 3 /* Mappable interrupt 1 */
+#define SGI_HPCDMA_IRQ SGINT_LOCAL1 + 4 /* HPC DMA done */
+#define SGI_ACFAIL_IRQ SGINT_LOCAL1 + 5 /* AC fail */
+#define SGI_VINO_IRQ SGINT_LOCAL1 + 6 /* Indy VINO */
+#define SGI_GIO_2_IRQ SGINT_LOCAL1 + 7 /* Vert retrace / GIO-2 */
+
+/* Mapped interrupts. These interrupts may be mapped to either 0, or 1
+ * We map them to 0 */
+#define SGI_VERT_IRQ SGINT_LOCAL2 + 0 /* INT3: newport vertical status */
+#define SGI_EISA_IRQ SGINT_LOCAL2 + 3 /* EISA interrupts */
#define SGI_KEYBOARD_IRQ SGINT_LOCAL2 + 4 /* keyboard */
-#define SGI_SERIAL_IRQ SGINT_LOCAL2 + 5 /* onboard serial */
+#define SGI_SERIAL_IRQ SGINT_LOCAL2 + 5 /* onboard serial */
/* INT2 occupies HPC PBUS slot 4, INT3 uses slot 6. */
-#define SGI_INT2_BASE 0x1fbd9000 /* physical */
-#define SGI_INT3_BASE 0x1fbd9880 /* physical */
+#define SGI_INT2_BASE 0x1fbd9000 /* physical */
+#define SGI_INT3_BASE 0x1fbd9880 /* physical */
struct sgi_ioc_ints {
#ifdef __MIPSEB__
unsigned char _unused0[3];
- volatile unsigned char istat0; /* Interrupt status zero */
+ volatile unsigned char istat0; /* Interrupt status zero */
#else
- volatile unsigned char istat0; /* Interrupt status zero */
+ volatile unsigned char istat0; /* Interrupt status zero */
unsigned char _unused0[3];
#endif
-#define ISTAT0_FFULL 0x01
-#define ISTAT0_SCSI0 0x02
-#define ISTAT0_SCSI1 0x04
-#define ISTAT0_ENET 0x08
-#define ISTAT0_GFXDMA 0x10
-#define ISTAT0_LPR 0x20
-#define ISTAT0_HPC2 0x40
-#define ISTAT0_LIO2 0x80
-
+#define ISTAT0_FFULL 0x01
+#define ISTAT0_SCSI0 0x02
+#define ISTAT0_SCSI1 0x04
+#define ISTAT0_ENET 0x08
+#define ISTAT0_GFXDMA 0x10
+#define ISTAT0_LPR 0x20
+#define ISTAT0_HPC2 0x40
+#define ISTAT0_LIO2 0x80
+
#ifdef __MIPSEB__
unsigned char _unused1[3];
- volatile unsigned char imask0; /* Interrupt mask zero */
+ volatile unsigned char imask0; /* Interrupt mask zero */
unsigned char _unused2[3];
- volatile unsigned char istat1; /* Interrupt status one */
+ volatile unsigned char istat1; /* Interrupt status one */
#else
- volatile unsigned char imask0; /* Interrupt mask zero */
+ volatile unsigned char imask0; /* Interrupt mask zero */
unsigned char _unused1[3];
- volatile unsigned char istat1; /* Interrupt status one */
+ volatile unsigned char istat1; /* Interrupt status one */
unsigned char _unused2[3];
#endif
-#define ISTAT1_ISDNI 0x01
-#define ISTAT1_PWR 0x02
-#define ISTAT1_ISDNH 0x04
-#define ISTAT1_LIO3 0x08
-#define ISTAT1_HPC3 0x10
-#define ISTAT1_AFAIL 0x20
-#define ISTAT1_VIDEO 0x40
-#define ISTAT1_GIO2 0x80
-
+#define ISTAT1_ISDNI 0x01
+#define ISTAT1_PWR 0x02
+#define ISTAT1_ISDNH 0x04
+#define ISTAT1_LIO3 0x08
+#define ISTAT1_HPC3 0x10
+#define ISTAT1_AFAIL 0x20
+#define ISTAT1_VIDEO 0x40
+#define ISTAT1_GIO2 0x80
+
#ifdef __MIPSEB__
unsigned char _unused3[3];
- volatile unsigned char imask1; /* Interrupt mask one */
+ volatile unsigned char imask1; /* Interrupt mask one */
unsigned char _unused4[3];
- volatile unsigned char vmeistat; /* VME interrupt status */
+ volatile unsigned char vmeistat; /* VME interrupt status */
unsigned char _unused5[3];
- volatile unsigned char cmeimask0; /* VME interrupt mask zero */
+ volatile unsigned char cmeimask0; /* VME interrupt mask zero */
unsigned char _unused6[3];
- volatile unsigned char cmeimask1; /* VME interrupt mask one */
+ volatile unsigned char cmeimask1; /* VME interrupt mask one */
unsigned char _unused7[3];
- volatile unsigned char cmepol; /* VME polarity */
+ volatile unsigned char cmepol; /* VME polarity */
#else
- volatile unsigned char imask1; /* Interrupt mask one */
+ volatile unsigned char imask1; /* Interrupt mask one */
unsigned char _unused3[3];
- volatile unsigned char vmeistat; /* VME interrupt status */
+ volatile unsigned char vmeistat; /* VME interrupt status */
unsigned char _unused4[3];
- volatile unsigned char cmeimask0; /* VME interrupt mask zero */
+ volatile unsigned char cmeimask0; /* VME interrupt mask zero */
unsigned char _unused5[3];
- volatile unsigned char cmeimask1; /* VME interrupt mask one */
+ volatile unsigned char cmeimask1; /* VME interrupt mask one */
unsigned char _unused6[3];
- volatile unsigned char cmepol; /* VME polarity */
+ volatile unsigned char cmepol; /* VME polarity */
unsigned char _unused7[3];
#endif
};
@@ -109,21 +136,21 @@
struct sgi_ioc_timers {
#ifdef __MIPSEB__
unsigned char _unused0[3];
- volatile unsigned char tcnt0; /* counter 0 */
+ volatile unsigned char tcnt0; /* counter 0 */
unsigned char _unused1[3];
- volatile unsigned char tcnt1; /* counter 1 */
+ volatile unsigned char tcnt1; /* counter 1 */
unsigned char _unused2[3];
- volatile unsigned char tcnt2; /* counter 2 */
+ volatile unsigned char tcnt2; /* counter 2 */
unsigned char _unused3[3];
- volatile unsigned char tcword; /* control word */
+ volatile unsigned char tcword; /* control word */
#else
- volatile unsigned char tcnt0; /* counter 0 */
+ volatile unsigned char tcnt0; /* counter 0 */
unsigned char _unused0[3];
- volatile unsigned char tcnt1; /* counter 1 */
+ volatile unsigned char tcnt1; /* counter 1 */
unsigned char _unused1[3];
- volatile unsigned char tcnt2; /* counter 2 */
+ volatile unsigned char tcnt2; /* counter 2 */
unsigned char _unused2[3];
- volatile unsigned char tcword; /* control word */
+ volatile unsigned char tcword; /* control word */
unsigned char _unused3[3];
#endif
};
@@ -156,22 +183,22 @@
struct sgi_int2_regs {
struct sgi_ioc_ints ints;
- volatile u32 ledbits; /* LED control bits */
-#define INT2_LED_TXCLK 0x01 /* GPI to TXCLK enable */
-#define INT2_LED_SERSLCT0 0x02 /* serial port0: 0=apple 1=pc */
-#define INT2_LED_SERSLCT1 0x04 /* serial port1: 0=apple 1=pc */
-#define INT2_LED_CHEAPER 0x08 /* 0=cheapernet 1=ethernet */
-#define INT2_LED_POWEROFF 0x10 /* Power-off request, active high */
+ volatile u32 ledbits; /* LED control bits */
+#define INT2_LED_TXCLK 0x01 /* GPI to TXCLK enable */
+#define INT2_LED_SERSLCT0 0x02 /* serial port0: 0=apple 1=pc */
+#define INT2_LED_SERSLCT1 0x04 /* serial port1: 0=apple 1=pc */
+#define INT2_LED_CHEAPER 0x08 /* 0=cheapernet 1=ethernet */
+#define INT2_LED_POWEROFF 0x10 /* Power-off request, active high */
#ifdef __MIPSEB__
unsigned char _unused0[3];
- volatile unsigned char tclear; /* Timer clear strobe address */
+ volatile unsigned char tclear; /* Timer clear strobe address */
#else
- volatile unsigned char tclear; /* Timer clear strobe address */
+ volatile unsigned char tclear; /* Timer clear strobe address */
unsigned char _unused0[3];
#endif
-#define INT2_TCLEAR_T0CLR 0x1 /* Clear timer0 IRQ */
-#define INT2_TCLEAR_T1CLR 0x2 /* Clear timer1 IRQ */
+#define INT2_TCLEAR_T0CLR 0x1 /* Clear timer0 IRQ */
+#define INT2_TCLEAR_T1CLR 0x2 /* Clear timer1 IRQ */
/* I am guesing there are only two unused registers here
* but I could be wrong... - andrewb
*/
@@ -185,12 +212,12 @@
#ifdef __MIPSEB__
unsigned char _unused0[3];
- volatile unsigned char tclear; /* Timer clear strobe address */
+ volatile unsigned char tclear; /* Timer clear strobe address */
#else
- volatile unsigned char tclear; /* Timer clear strobe address */
+ volatile unsigned char tclear; /* Timer clear strobe address */
unsigned char _unused0[3];
#endif
- volatile u32 estatus; /* Error status reg */
+ volatile u32 estatus; /* Error status reg */
u32 _unused1[2];
struct sgi_ioc_timers timers;
};
|
|
From: James S. <jsi...@us...> - 2001-11-26 18:13:20
|
Update of /cvsroot/linux-mips/linux/arch/mips64/arc
In directory usw-pr-cvs1:/tmp/cvs-serv3052
Added Files:
misc.c
Log Message:
Oops. missed a file.
--- NEW FILE: misc.c ---
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Miscellaneous ARCS PROM routines.
*
* Copyright (C) 1996 David S. Miller (dm...@en...)
* Copyright (C) 1999 Ralf Baechle (ra...@gn...)
* Copyright (C) 1999 Silicon Graphics, Inc.
*/
#include <linux/config.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <asm/bcache.h>
#include <asm/arc/types.h>
#include <asm/sgialib.h>
#include <asm/bootinfo.h>
#include <asm/system.h>
extern void *sgiwd93_host;
extern void reset_wd33c93(void *instance);
VOID
ArcHalt(VOID)
{
bc_disable();
cli();
#if CONFIG_SCSI_SGIWD93
reset_wd33c93(sgiwd93_host);
#endif
ARC_CALL0(halt);
never: goto never;
}
VOID
ArcPowerDown(VOID)
{
bc_disable();
cli();
#if CONFIG_SCSI_SGIWD93
reset_wd33c93(sgiwd93_host);
#endif
ARC_CALL0(pdown);
never: goto never;
}
/* XXX is this a soft reset basically? XXX */
VOID
ArcRestart(VOID)
{
bc_disable();
cli();
#if CONFIG_SCSI_SGIWD93
reset_wd33c93(sgiwd93_host);
#endif
ARC_CALL0(restart);
never: goto never;
}
VOID
ArcReboot(VOID)
{
bc_disable();
cli();
#if CONFIG_SCSI_SGIWD93
reset_wd33c93(sgiwd93_host);
#endif
ARC_CALL0(reboot);
never: goto never;
}
VOID
ArcEnterInteractiveMode(VOID)
{
bc_disable();
cli();
#if CONFIG_SCSI_SGIWD93
reset_wd33c93(sgiwd93_host);
#endif
ARC_CALL0(imode);
never: goto never;
}
LONG
ArcSaveConfiguration(VOID)
{
return ARC_CALL0(cfg_save);
}
struct linux_sysid *
ArcGetSystemId(VOID)
{
return (struct linux_sysid *) ARC_CALL0(get_sysid);
}
VOID __init
ArcFlushAllCaches(VOID)
{
ARC_CALL0(cache_flush);
}
|
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