linux-mips-commits — CVS Commit Patches

[Linux-mips-commits]CVS: linux/arch/mips64/configs defconfig-sb1250-swarm,1.5,1.6

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips64/configs
In directory usw-pr-cvs1:/tmp/cvs-serv17142

Modified Files:
	defconfig-sb1250-swarm 
Log Message:
Enable root-nfs and dhcp / bootp network autoconfiguration. Enable SMP again by default.

Index: defconfig-sb1250-swarm
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips64/configs/defconfig-sb1250-swarm,v
retrieving revision 1.5
retrieving revision 1.6
diff -u -d -r1.5 -r1.6
--- defconfig-sb1250-swarm	14 Feb 2002 20:43:59 -0000	1.5
+++ defconfig-sb1250-swarm	19 Feb 2002 18:00:31 -0000	1.6
@@ -13,9 +13,23 @@
 # Machine selection
 #
 # CONFIG_SGI_IP27 is not set
-# CONFIG_SIBYTE_SB1250 is not set
+CONFIG_SIBYTE_SB1250=y
+# CONFIG_PCI is not set
+# CONFIG_SIBYTE_SB1250_PROF is not set
+# CONFIG_BCM1250_TBPROF is not set
+# CONFIG_REMOTE_DEBUG is not set
+CONFIG_SIBYTE_SWARM=y
+# CONFIG_SIMULATION is not set
+# CONFIG_L3DEMO is not set
+CONFIG_SIBYTE_SWARM_MAX_MEM_REGIONS=16
+CONFIG_SMP=y
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
 # CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
+CONFIG_BOOT_ELF32=y
+CONFIG_SWAP_IO_SPACE=y
+CONFIG_CFE=y
+CONFIG_SIBYTE_SB1250=y
+CONFIG_L1_CACHE_SHIFT=5
 # CONFIG_ISA is not set
 # CONFIG_EISA is not set
 # CONFIG_PCI is not set
@@ -32,8 +46,8 @@
 # CONFIG_CPU_R8000 is not set
 # CONFIG_CPU_R10000 is not set
 CONFIG_CPU_SB1=y
-# CONFIG_SB1_PASS_1_WORKAROUNDS is not set
-# CONFIG_SB1_CACHE_ERROR is not set
+CONFIG_SB1_PASS_1_WORKAROUNDS=y
+CONFIG_SB1_CACHE_ERROR=y
 CONFIG_VTAG_ICACHE=y
 CONFIG_CPU_HAS_LLSC=y
 CONFIG_CPU_HAS_LLDSCD=y
@@ -50,7 +64,8 @@
 # CONFIG_BSD_PROCESS_ACCT is not set
 # CONFIG_SYSCTL is not set
 CONFIG_BINFMT_ELF=y
-# CONFIG_MIPS32_COMPAT is not set
+CONFIG_MIPS32_COMPAT=y
+CONFIG_BINFMT_ELF32=y
 # CONFIG_BINFMT_MISC is not set
 
 #
@@ -79,9 +94,8 @@
 # CONFIG_BLK_DEV_DAC960 is not set
 # CONFIG_BLK_DEV_LOOP is not set
 # CONFIG_BLK_DEV_NBD is not set
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=4096
-CONFIG_BLK_DEV_INITRD=y
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_BLK_DEV_INITRD is not set
 
 #
 # Multi-device support (RAID and LVM)
@@ -106,7 +120,10 @@
 CONFIG_INET=y
 # CONFIG_IP_MULTICAST is not set
 # CONFIG_IP_ADVANCED_ROUTER is not set
-# CONFIG_IP_PNP is not set
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_IP_PNP_RARP is not set
 # CONFIG_NET_IPIP is not set
 # CONFIG_NET_IPGRE is not set
 # CONFIG_INET_ECN is not set
@@ -162,6 +179,7 @@
 # Ethernet (10 or 100Mbit)
 #
 CONFIG_NET_ETHERNET=y
+CONFIG_NET_SB1250_MAC=y
 # CONFIG_SUNLANCE is not set
 # CONFIG_SUNBMAC is not set
 # CONFIG_SUNQE is not set
@@ -252,6 +270,11 @@
 # CONFIG_SERIAL_TX3912_CONSOLE is not set
 # CONFIG_AU1000_UART is not set
 # CONFIG_TXX927_SERIAL is not set
+CONFIG_SIBYTE_SB1250_DUART=y
+CONFIG_SIBYTE_SB1250_DUART_CONSOLE=y
+CONFIG_SERIAL_CONSOLE=y
+CONFIG_SB1250_DUART_OUTPUT_BUF_SIZE=1024
+# CONFIG_SIBYTE_SB1250_DUART_NO_PORT_1 is not set
 # CONFIG_UNIX98_PTYS is not set
 
 #
@@ -286,7 +309,6 @@
 # CONFIG_INTEL_RNG is not set
 # CONFIG_NVRAM is not set
 # CONFIG_RTC is not set
-# CONFIG_MIPS_RTC is not set
 # CONFIG_DTLK is not set
 # CONFIG_R3964 is not set
 # CONFIG_APPLICOM is not set
@@ -360,7 +382,7 @@
 # CONFIG_INTERMEZZO_FS is not set
 CONFIG_NFS_FS=y
 CONFIG_NFS_V3=y
-# CONFIG_ROOT_NFS is not set
+CONFIG_ROOT_NFS=y
 # CONFIG_NFSD is not set
 # CONFIG_NFSD_V3 is not set
 CONFIG_SUNRPC=y
@@ -523,4 +545,3 @@
 CONFIG_CROSSCOMPILE=y
 # CONFIG_REMOTE_DEBUG is not set
 # CONFIG_MAGIC_SYSRQ is not set
-# CONFIG_MIPS_UNCACHED is not set

[Linux-mips-commits]CVS: linux/arch/mips/kernel smp.c,1.13,1.14

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips/kernel
In directory usw-pr-cvs1:/tmp/cvs-serv15005

Modified Files:
	smp.c 
Log Message:
Make start_secondary a void function. Call smp_processor_id() only once. Initialize c0_context to 0. Seems like it always was just coincidence that any SMP kernel ever worked ...

Index: smp.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/kernel/smp.c,v
retrieving revision 1.13
retrieving revision 1.14
diff -u -d -r1.13 -r1.14
--- smp.c	28 Jan 2002 20:31:56 -0000	1.13
+++ smp.c	19 Feb 2002 17:57:11 -0000	1.14
@@ -83,8 +83,10 @@
  * Hook for doing final board-specific setup after the generic smp setup
  * is done
  */
-asmlinkage int start_secondary(void)
+asmlinkage void start_secondary(void)
 {
+	unsigned int cpu = smp_processor_id();
+
 	prom_init_secondary();
 
 	/* Do stuff that trap_init() did for the first processor */
@@ -95,16 +97,15 @@
 	/* XXX parity protection should be folded in here when it's converted to
 	   an option instead of something based on .cputype */
 
-	write_32bit_cp0_register(CP0_CONTEXT, smp_processor_id()<<23);
-	pgd_current[smp_processor_id()] = init_mm.pgd;
-	cpu_data[smp_processor_id()].udelay_val = loops_per_jiffy;
-	cpu_data[smp_processor_id()].asid_cache = ASID_FIRST_VERSION;
+	set_context(cpu << 23);
+	pgd_current[cpu] = init_mm.pgd;
+	cpu_data[cpu].udelay_val = loops_per_jiffy;
+	cpu_data[cpu].asid_cache = ASID_FIRST_VERSION;
 	prom_smp_finish();
 	printk("Slave cpu booted successfully\n");
-	CPUMASK_SETB(cpu_online_map, smp_processor_id());
+	CPUMASK_SETB(cpu_online_map, cpu);
 	atomic_inc(&cpus_booted);
 	cpu_idle();
-	return 0;
 }
 
 void __init smp_commence(void)

[Linux-mips-commits]CVS: linux/arch/mips64/kernel smp.c,1.13,1.14

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips64/kernel
In directory usw-pr-cvs1:/tmp/cvs-serv13359

Modified Files:
	smp.c 
Log Message:
Redo start_secondary a la 32-bit kernel. Make start_secondary a void function. Call smp_processor_id() only once. Initialize c0_context to 0. Seems like it always was just coincidence that any SMP kernel ever worked ...

Index: smp.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips64/kernel/smp.c,v
retrieving revision 1.13
retrieving revision 1.14
diff -u -d -r1.13 -r1.14
--- smp.c	28 Jan 2002 20:31:57 -0000	1.13
+++ smp.c	19 Feb 2002 17:54:59 -0000	1.14
@@ -19,6 +19,7 @@
 #include <linux/cache.h>
 
 #include <asm/atomic.h>
+#include <asm/cpu.h>
 #include <asm/processor.h>
 #include <asm/system.h>
 #include <asm/hardirq.h>
@@ -55,20 +56,41 @@
 #endif
 }
 
-int __init start_secondary(void)
+/*
+ * Hook for doing final board-specific setup after the generic smp setup
+ * is done
+ */
+asmlinkage void start_secondary(void)
 {
-	extern atomic_t smp_commenced;
+	unsigned int cpu = smp_processor_id();
 
-	smp_callin();
-	while (!atomic_read(&smp_commenced));
+	prom_init_secondary();
+
+	/* Do stuff that trap_init() did for the first processor */
+	clear_cp0_status(ST0_BEV);
+	if (mips_cpu.options & MIPS_CPU_DIVEC) {
+		set_cp0_cause(CAUSEF_IV);
+	}
 
+	/*
+	 * XXX parity protection should be folded in here when it's converted
+	 * to an option instead of something based on .cputype
+	 */
+	set_context(cpu << 23);
+	pgd_current[cpu] = init_mm.pgd;
+	cpu_data[cpu].udelay_val = loops_per_jiffy;
+	cpu_data[cpu].asid_cache = ASID_FIRST_VERSION;
+	prom_smp_finish();
+	printk("Slave cpu booted successfully\n");
+	CPUMASK_SETB(cpu_online_map, cpu);
+	atomic_inc(&cpus_booted);
 	cpu_idle();
 }
 
 void __init smp_commence(void)
 {
 	wmb();
-	atomic_set(&smp_commenced,1);
+	atomic_set(&smp_commenced, 1);
 }
 
 /*

[Linux-mips-commits]CVS: linux/arch/mips64/mm fault.c,1.9,1.10

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips64/mm
In directory usw-pr-cvs1:/tmp/cvs-serv11681

Modified Files:
	fault.c 
Log Message:
Reshuffle debug code.

Index: fault.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips64/mm/fault.c,v
retrieving revision 1.9
retrieving revision 1.10
diff -u -d -r1.9 -r1.10
--- fault.c	28 Jan 2002 20:31:57 -0000	1.9
+++ fault.c	19 Feb 2002 17:51:29 -0000	1.10
@@ -106,6 +106,11 @@
 	unsigned long fixup;
 	siginfo_t info;
 
+#if 0
+	printk("Cpu%d[%s:%d:%08lx:%ld:%08lx]\n", smp_processor_id(),
+		current->comm, current->pid, address, write, regs->cp0_epc);
+#endif
+
 	/*
 	 * We fault-in kernel-space virtual memory on-demand. The
 	 * 'reference' page table is init_mm.pgd.
@@ -125,10 +130,7 @@
 	 */
 	if (in_interrupt() || mm == &init_mm)
 		goto no_context;
-#if DEBUG_MIPS64
-	printk("Cpu%d[%s:%d:%08lx:%ld:%08lx]\n", smp_processor_id(), current->comm,
-		current->pid, address, write, regs->cp0_epc);
-#endif
+
 	down_read(&mm->mmap_sem);
 	vma = find_vma(mm, address);
 	if (!vma)

[Linux-mips-commits]CVS: linux/arch/mips64/kernel head.S,1.3,1.4 setup.c,1.10,1.11

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips64/kernel
In directory usw-pr-cvs1:/tmp/cvs-serv11476/kernel

Modified Files:
	head.S setup.c 
Log Message:
Rework initialization code to be more similar to the 32-bit kernel.

Index: head.S
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips64/kernel/head.S,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- head.S	28 Jan 2002 20:34:23 -0000	1.3
+++ head.S	19 Feb 2002 17:50:59 -0000	1.4
@@ -106,33 +106,19 @@
 
 	CLI					# disable interrupts
 
-	mfc0	t0, CP0_STATUS
-	/*
-	 * On IP27, I am seeing the TS bit set when the
-	 * kernel is loaded. Maybe because the kernel is
-	 * in ckseg0 and not xkphys? Clear it anyway ...
-	 */
-	li	t1, ~(ST0_TS|ST0_CU1|ST0_CU2|ST0_CU3)
-	and	t0, t1
-	or	t0, (ST0_CU0|ST0_KX|ST0_SX|ST0_FR) # Bogosity: cu0 indicates kernel
-	mtc0	t0, CP0_STATUS			   # thread in copy_thread.
-
 	la	$28, init_task_union		# init current pointer
 	daddiu	t0, $28, KERNEL_STACK_SIZE-32
 	sd	t0, kernelsp
 	dsubu	sp, t0, 4*SZREG			# init stack pointer
 	move	t0, $28
+
 #ifdef CONFIG_SMP
 	mtc0	t0, CP0_WATCHLO
 	dsrl32	t0, t0, 0
 	mtc0	t0, CP0_WATCHHI
 #endif
-	/* Note that all firmware passed argument registers still
-	   have their values.  */
-	jal	prom_init			# initialize firmware
 
-	jal	start_kernel
-1:	b	1b				# just in case ...
+	jal	init_arch
 	END(kernel_entry)
 
 #ifdef CONFIG_SMP
@@ -164,18 +150,19 @@
 	LEAF(smp_bootstrap)
 	.set push
 	.set noreorder
+
 	mtc0	zero, CP0_WIRED
 	CLI
 	mfc0	t0, CP0_STATUS
-	li	t1, ~(ST0_CU1|ST0_CU2|ST0_CU3|ST0_KX|ST0_SX|ST0_BEV)
+	li	t1, ~(ST0_CU1|ST0_CU2|ST0_CU3|ST0_BEV)
 	and	t0, t1
-	or	t0, (ST0_CU0|ST0_FR);
+	or	t0, (ST0_CU0|ST0_FR|ST0_KX|ST0_SX);
 	jal	start_secondary
 	mtc0	t0, CP0_STATUS
 	.set pop
 	END(smp_bootstrap)
-#endif
 #endif /* CONFIG_SGI_IP27 */
+#endif /* CONFIG_SMP */
 
 	__FINIT
 

Index: setup.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips64/kernel/setup.c,v
retrieving revision 1.10
retrieving revision 1.11
diff -u -d -r1.10 -r1.11
--- setup.c	2 Jan 2002 19:12:17 -0000	1.10
+++ setup.c	19 Feb 2002 17:50:59 -0000	1.11
@@ -28,6 +28,7 @@
 #include <linux/blk.h>
 #endif
 
+#include <asm/addrspace.h>
 #include <asm/bootinfo.h>
 #include <asm/cpu.h>
 #include <asm/mipsregs.h>
@@ -109,6 +110,12 @@
 extern void ip27_setup(void);
 extern void ip32_setup(void);
 
+extern void sgi_sysinit(void);
+extern void SetUpBootInfo(void);
+extern void load_mmu(void);
+extern ATTRIB_NORET asmlinkage void start_kernel(void);
+extern void prom_init(int, char **, char **, int *);
+
 static inline void check_wait(void)
 {
 	printk("Checking for 'wait' instruction... ");
@@ -468,11 +475,252 @@
 	}
 }
 
-void __init setup_arch(char **cmdline_p)
+static inline void cpu_report(void)
+{
+	printk("CPU revision is: %08x\n", mips_cpu.processor_id);
+	if (mips_cpu.options & MIPS_CPU_FPU)
+		printk("FPU revision is: %08x\n", mips_cpu.fpu_id);
+}
+
+asmlinkage void __init init_arch(int argc, char **argv, char **envp,
+	int *prom_vec)
 {
+	/* Determine which MIPS variant we are running on. */
 	cpu_probe();
+
+	prom_init(argc, argv, envp, prom_vec);
+
+#ifdef CONFIG_SGI_IP22
+	sgi_sysinit();
+#endif
+
+	cpu_report();
+
+	/*
+	 * Determine the mmu/cache attached to this machine, then flush the
+	 * tlb and caches.  On the r4xx0 variants this also sets CP0_WIRED to
+	 * zero.
+	 */
 	load_mmu();
 
+	/*
+	 * On IP27, I am seeing the TS bit set when the kernel is loaded.
+	 * Maybe because the kernel is in ckseg0 and not xkphys? Clear it
+	 * anyway ...
+	 */
+	clear_cp0_status(ST0_BEV|ST0_TS|ST0_CU1|ST0_CU2|ST0_CU3);
+	set_cp0_status(ST0_CU0|ST0_KX|ST0_SX|ST0_FR);
+
+	start_kernel();
+}
+
+void __init add_memory_region(phys_t start, phys_t size,
+			      long type)
+{
+	int x = boot_mem_map.nr_map;
+
+	if (x == BOOT_MEM_MAP_MAX) {
+		printk("Ooops! Too many entries in the memory map!\n");
+		return;
+	}
+
+	boot_mem_map.map[x].addr = start;
+	boot_mem_map.map[x].size = size;
+	boot_mem_map.map[x].type = type;
+	boot_mem_map.nr_map++;
+}
+
+static void __init print_memory_map(void)
+{
+	int i;
+
+	for (i = 0; i < boot_mem_map.nr_map; i++) {
+		printk(" memory: %08Lx @ %08Lx ",
+			(unsigned long long) boot_mem_map.map[i].size,
+			(unsigned long long) boot_mem_map.map[i].addr);
+		switch (boot_mem_map.map[i].type) {
+		case BOOT_MEM_RAM:
+			printk("(usable)\n");
+			break;
+		case BOOT_MEM_ROM_DATA:
+			printk("(ROM data)\n");
+			break;
+		case BOOT_MEM_RESERVED:
+			printk("(reserved)\n");
+			break;
+		default:
+			printk("type %lu\n", boot_mem_map.map[i].type);
+			break;
+		}
+	}
+}
+
+static inline void parse_mem_cmdline(void)
+{
+	char c = ' ', *to = command_line, *from = saved_command_line;
+	unsigned long start_at, mem_size;
+	int len = 0;
+	int usermem = 0;
+
+	printk("Determined physical RAM map:\n");
+	print_memory_map();
+
+	for (;;) {
+		/*
+		 * "mem=XXX[kKmM]" defines a memory region from
+		 * 0 to <XXX>, overriding the determined size.
+		 * "mem=XXX[KkmM]@YYY[KkmM]" defines a memory region from
+		 * <YYY> to <YYY>+<XXX>, overriding the determined size.
+		 */
+		if (c == ' ' && !memcmp(from, "mem=", 4)) {
+			if (to != command_line)
+				to--;
+			/*
+			 * If a user specifies memory size, we
+			 * blow away any automatically generated
+			 * size.
+			 */
+			if (usermem == 0) {
+				boot_mem_map.nr_map = 0;
+				usermem = 1;
+			}
+			mem_size = memparse(from + 4, &from);
+			if (*from == '@')
+				start_at = memparse(from + 1, &from);
+			else
+				start_at = 0;
+			add_memory_region(start_at, mem_size, BOOT_MEM_RAM);
+		}
+		c = *(from++);
+		if (!c)
+			break;
+		if (CL_SIZE <= ++len)
+			break;
+		*(to++) = c;
+	}
+	*to = '\0';
+
+	if (usermem) {
+		printk("User-defined physical RAM map:\n");
+		print_memory_map();
+	}
+}
+
+void bootmem_init(void)
+{
+#ifdef CONFIG_BLK_DEV_INITRD
+	unsigned long tmp;
+	unsigned long *initrd_header;
+#endif
+	unsigned long bootmap_size;
+	unsigned long start_pfn, max_pfn;
+	int i;
+	extern int _end;
+
+#define PFN_UP(x)	(((x) + PAGE_SIZE - 1) >> PAGE_SHIFT)
+#define PFN_DOWN(x)	((x) >> PAGE_SHIFT)
+#define PFN_PHYS(x)	((x) << PAGE_SHIFT)
+
+	/*
+	 * Partially used pages are not usable - thus
+	 * we are rounding upwards.
+	 * start_pfn = PFN_UP(__pa(&_end));
+	 */
+	start_pfn = PFN_UP((unsigned long)&_end - KSEG0);
+
+	/* Find the highest page frame number we have available.  */
+	max_pfn = 0;
+	for (i = 0; i < boot_mem_map.nr_map; i++) {
+		unsigned long start, end;
+
+		if (boot_mem_map.map[i].type != BOOT_MEM_RAM)
+			continue;
+
+		start = PFN_UP(boot_mem_map.map[i].addr);
+		end = PFN_DOWN(boot_mem_map.map[i].addr
+		      + boot_mem_map.map[i].size);
+
+		if (start >= end)
+			continue;
+		if (end > max_pfn)
+			max_pfn = end;
+	}
+
+	/* Initialize the boot-time allocator.  */
+	bootmap_size = init_bootmem(start_pfn, max_pfn);
+
+	/*
+	 * Register fully available low RAM pages with the bootmem allocator.
+	 */
+	for (i = 0; i < boot_mem_map.nr_map; i++) {
+		unsigned long curr_pfn, last_pfn, size;
+
+		/*
+		 * Reserve usable memory.
+		 */
+		if (boot_mem_map.map[i].type != BOOT_MEM_RAM)
+			continue;
+
+		/*
+		 * We are rounding up the start address of usable memory:
+		 */
+		curr_pfn = PFN_UP(boot_mem_map.map[i].addr);
+		if (curr_pfn >= max_pfn)
+			continue;
+		if (curr_pfn < start_pfn)
+			curr_pfn = start_pfn;
+
+		/*
+		 * ... and at the end of the usable range downwards:
+		 */
+		last_pfn = PFN_DOWN(boot_mem_map.map[i].addr
+				    + boot_mem_map.map[i].size);
+
+		if (last_pfn > max_pfn)
+			last_pfn = max_pfn;
+
+		/*
+		 * ... finally, did all the rounding and playing
+		 * around just make the area go away?
+		 */
+		if (last_pfn <= curr_pfn)
+			continue;
+
+		size = last_pfn - curr_pfn;
+		free_bootmem(PFN_PHYS(curr_pfn), PFN_PHYS(size));
+	}
+
+	/* Reserve the bootmap memory.  */
+	reserve_bootmem(PFN_PHYS(start_pfn), bootmap_size);
+
+#ifdef CONFIG_BLK_DEV_INITRD
+#error "Initrd is broken, please fit it."
+	tmp = (((unsigned long)&_end + PAGE_SIZE-1) & PAGE_MASK) - 8;
+	if (tmp < (unsigned long)&_end)
+		tmp += PAGE_SIZE;
+	initrd_header = (unsigned long *)tmp;
+	if (initrd_header[0] == 0x494E5244) {
+		initrd_start = (unsigned long)&initrd_header[2];
+		initrd_end = initrd_start + initrd_header[1];
+		initrd_below_start_ok = 1;
+		if (initrd_end > memory_end) {
+			printk("initrd extends beyond end of memory "
+			       "(0x%08lx > 0x%08lx)\ndisabling initrd\n",
+			       initrd_end,memory_end);
+			initrd_start = 0;
+		} else
+			*memory_start_p = initrd_end;
+	}
+#endif
+
+#undef PFN_UP
+#undef PFN_DOWN
+#undef PFN_PHYS
+
+}
+
+void __init setup_arch(char **cmdline_p)
+{
 #ifdef CONFIG_SGI_IP22
 	ip22_setup();
 #endif
@@ -482,9 +730,16 @@
 #ifdef CONFIG_SGI_IP32
 	ip32_setup();
 #endif
+#ifdef CONFIG_SGI_IP32
+	ip32_setup();
+#endif
+#ifdef CONFIG_SIBYTE_SWARM
+	swarm_setup();
+	bootmem_init();		/* XXX */
+#endif
 
 #ifdef CONFIG_ARC_MEMORY
-	bootmem_init ();
+	bootmem_init();
 #endif
 
 	strncpy(command_line, arcs_cmdline, CL_SIZE);
@@ -492,6 +747,8 @@
 	saved_command_line[CL_SIZE-1] = '\0';
 
 	*cmdline_p = command_line;
+
+	parse_mem_cmdline();
 
 	paging_init();
 }

[Linux-mips-commits]CVS: linux/arch/mips64/mm init.c,1.7,1.8

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips64/mm
In directory usw-pr-cvs1:/tmp/cvs-serv11476/mm

Modified Files:
	init.c 
Log Message:
Rework initialization code to be more similar to the 32-bit kernel.

Index: init.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips64/mm/init.c,v
retrieving revision 1.7
retrieving revision 1.8
diff -u -d -r1.7 -r1.8
--- init.c	2 Jan 2002 19:12:18 -0000	1.7
+++ init.c	19 Feb 2002 17:50:59 -0000	1.8
@@ -161,158 +161,6 @@
 	return 1UL << order;
 }
 
-void __init add_memory_region(unsigned long start, unsigned long size,
-                              long type)
-{
-        int x = boot_mem_map.nr_map;
-
-        if (x == BOOT_MEM_MAP_MAX) {
-                printk("Ooops! Too many entries in the memory map!\n");
-                return;
-        }
-
-        boot_mem_map.map[x].addr = start;
-        boot_mem_map.map[x].size = size;
-        boot_mem_map.map[x].type = type;
-        boot_mem_map.nr_map++;
-}
-
-static void __init print_memory_map(void)
-{
-        int i;
-
-        for (i = 0; i < boot_mem_map.nr_map; i++) {
-                printk(" memory: %08lx @ %08lx ",
-                        boot_mem_map.map[i].size, boot_mem_map.map[i].addr);
-                switch (boot_mem_map.map[i].type) {
-                case BOOT_MEM_RAM:
-                        printk("(usable)\n");
-                        break;
-                case BOOT_MEM_ROM_DATA:
-                        printk("(ROM data)\n");
-                        break;
-                case BOOT_MEM_RESERVED:
-                        printk("(reserved)\n");
-                        break;
-                default:
-                        printk("type %lu\n", boot_mem_map.map[i].type);
-                        break;
-                }
-        }
-}
-
-void bootmem_init(void)
-{
-#ifdef CONFIG_BLK_DEV_INITRD
-	unsigned long tmp;
-	unsigned long *initrd_header;
-#endif
-	unsigned long bootmap_size;
-	unsigned long start_pfn, max_pfn;
-	int i;
-	extern int _end;
-
-#define PFN_UP(x)	(((x) + PAGE_SIZE - 1) >> PAGE_SHIFT)
-#define PFN_DOWN(x)	((x) >> PAGE_SHIFT)
-#define PFN_PHYS(x)	((x) << PAGE_SHIFT)
-
-	/*
-	 * Partially used pages are not usable - thus
-	 * we are rounding upwards.
-	 */
-	start_pfn = PFN_UP(__pa(&_end));
-
-	/* Find the highest page frame number we have available.  */
-	max_pfn = 0;
-	for (i = 0; i < boot_mem_map.nr_map; i++) {
-		unsigned long start, end;
-
-		if (boot_mem_map.map[i].type != BOOT_MEM_RAM)
-			continue;
-
-		start = PFN_UP(boot_mem_map.map[i].addr);
-		end = PFN_DOWN(boot_mem_map.map[i].addr
-		      + boot_mem_map.map[i].size);
-
-		if (start >= end)
-			continue;
-		if (end > max_pfn)
-			max_pfn = end;
-	}
-
-	/* Initialize the boot-time allocator.  */
-	bootmap_size = init_bootmem(start_pfn, max_pfn);
-
-	/*
-	 * Register fully available low RAM pages with the bootmem allocator.
-	 */
-	for (i = 0; i < boot_mem_map.nr_map; i++) {
-		unsigned long curr_pfn, last_pfn, size;
-
-		/*
-		 * Reserve usable memory.
-		 */
-		if (boot_mem_map.map[i].type != BOOT_MEM_RAM)
-			continue;
-
-		/*
-		 * We are rounding up the start address of usable memory:
-		 */
-		curr_pfn = PFN_UP(boot_mem_map.map[i].addr);
-		if (curr_pfn >= max_pfn)
-			continue;
-		if (curr_pfn < start_pfn)
-			curr_pfn = start_pfn;
-
-		/*
-		 * ... and at the end of the usable range downwards:
-		 */
-		last_pfn = PFN_DOWN(boot_mem_map.map[i].addr
-				    + boot_mem_map.map[i].size);
-
-		if (last_pfn > max_pfn)
-			last_pfn = max_pfn;
-
-		/*
-		 * ... finally, did all the rounding and playing
-		 * around just make the area go away?
-		 */
-		if (last_pfn <= curr_pfn)
-			continue;
-
-		size = last_pfn - curr_pfn;
-		free_bootmem(PFN_PHYS(curr_pfn), PFN_PHYS(size));
-	}
-
-	/* Reserve the bootmap memory.  */
-	reserve_bootmem(PFN_PHYS(start_pfn), bootmap_size);
-
-#ifdef CONFIG_BLK_DEV_INITRD
-#error "Initrd is broken, please fit it."
-	tmp = (((unsigned long)&_end + PAGE_SIZE-1) & PAGE_MASK) - 8;
-	if (tmp < (unsigned long)&_end)
-		tmp += PAGE_SIZE;
-	initrd_header = (unsigned long *)tmp;
-	if (initrd_header[0] == 0x494E5244) {
-		initrd_start = (unsigned long)&initrd_header[2];
-		initrd_end = initrd_start + initrd_header[1];
-		initrd_below_start_ok = 1;
-		if (initrd_end > memory_end) {
-			printk("initrd extends beyond end of memory "
-			       "(0x%08lx > 0x%08lx)\ndisabling initrd\n",
-			       initrd_end,memory_end);
-			initrd_start = 0;
-		} else
-			*memory_start_p = initrd_end;
-	}
-#endif
-
-#undef PFN_UP
-#undef PFN_DOWN
-#undef PFN_PHYS
-
-}
-
 void show_mem(void)
 {
 	int i, free = 0, total = 0, reserved = 0;
@@ -365,7 +213,7 @@
 	max_dma =  virt_to_phys((char *)MAX_DMA_ADDRESS) >> PAGE_SHIFT;
 	low = max_low_pfn;
 
-#if defined(CONFIG_PCI) || defined(CONFIG_ISA)
+#ifdef CONFIG_ISA
 	if (low < max_dma)
 		zones_size[ZONE_DMA] = low;
 	else {
@@ -377,7 +225,7 @@
 #endif
 
 	free_area_init(zones_size);
-	
+
 	memset((void *)kptbl, 0, PAGE_SIZE << KPTBL_PAGE_ORDER);
 	memset((void *)kpmdtbl, 0, PAGE_SIZE);
 	pgd_set(swapper_pg_dir, kpmdtbl);

[Linux-mips-commits]CVS: linux/include/asm-mips64/sibyte sb1250.h,1.2,1.3

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/include/asm-mips64/sibyte
In directory usw-pr-cvs1:/tmp/cvs-serv10237

Modified Files:
	sb1250.h 
Log Message:
Delete duplicate definiton with different value.

Index: sb1250.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips64/sibyte/sb1250.h,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -d -r1.2 -r1.3
--- sb1250.h	28 Jan 2002 20:32:06 -0000	1.2
+++ sb1250.h	19 Feb 2002 17:48:34 -0000	1.3
@@ -24,6 +24,4 @@
 extern void sb1250_unmask_irq(int cpu, int irq);
 extern void sb1250_smp_finish(void);
 
-#define IO_SPACE_BASE 0xa0000000UL
-
 #endif

[Linux-mips-commits]CVS: linux/include/asm-mips64/sibyte swarm.h,1.1,1.2

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/include/asm-mips64/sibyte
In directory usw-pr-cvs1:/tmp/cvs-serv9731/asm-mips64/sibyte

Modified Files:
	swarm.h 
Log Message:
Kill dead code.  Reformat.

Index: swarm.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips64/sibyte/swarm.h,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- swarm.h	8 Nov 2001 17:28:25 -0000	1.1
+++ swarm.h	19 Feb 2002 17:47:37 -0000	1.2
@@ -19,19 +19,10 @@
 #ifndef _ASM_SIBYTE_SWARM_H
 #define _ASM_SIBYTE_SWARM_H
 
-#include <asm/addrspace.h>
-
-/*#define IO_SPACE_BASE 0xffffffffa0000000UL*/
-#define IO_SPACE_BASE K1BASE
-
-/* Not sure this is right... ---JDC */
-#define IO_SPACE_LIMIT 0xffff
-
 #define KERNEL_RESERVED_MEM 0x100000
+#define LED_BASE_ADDR 0x100a0020
 
 void swarm_setup(void);
-
-#define LED_BASE_ADDR 0x100a0020
 void setleds(char *str); 
 
-#endif
+#endif /* _ASM_SIBYTE_SWARM_H */

[Linux-mips-commits]CVS: linux/include/asm-mips/sibyte swarm.h,1.1,1.2

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/include/asm-mips/sibyte
In directory usw-pr-cvs1:/tmp/cvs-serv9731/asm-mips/sibyte

Modified Files:
	swarm.h 
Log Message:
Kill dead code.  Reformat.

Index: swarm.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/sibyte/swarm.h,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- swarm.h	8 Nov 2001 17:28:25 -0000	1.1
+++ swarm.h	19 Feb 2002 17:47:37 -0000	1.2
@@ -16,8 +16,8 @@
  * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  */
 
-#ifndef _SWARM_H
-#define _SWARM_H
+#ifndef _ASM_SIBYTE_SWARM_H
+#define _ASM_SIBYTE_SWARM_H
 
 #define KERNEL_RESERVED_MEM 0x100000
 #define LED_BASE_ADDR 0x100a0020
@@ -26,4 +26,4 @@
 
 void setleds(char *str); 
 
-#endif
+#endif /* _ASM_SIBYTE_SWARM_H */

[Linux-mips-commits]CVS: linux/include/asm-mips/sibyte 64bit.h,1.1,1.2

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/include/asm-mips/sibyte
In directory usw-pr-cvs1:/tmp/cvs-serv9335

Modified Files:
	64bit.h 
Log Message:
Minor code overhaul.

Index: 64bit.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/sibyte/64bit.h,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- 64bit.h	8 Nov 2001 17:28:25 -0000	1.1
+++ 64bit.h	19 Feb 2002 17:46:59 -0000	1.2
@@ -19,43 +19,47 @@
 #ifndef _SB1_64BIT_H
 #define _SB1_64BIT_H
 
+#include <linux/types.h>
 #include <asm/system.h>
 
+/*
+ * This is annoying...we can't actually write the 64-bit IO register properly
+ * without having access to 64-bit registers...  which doesn't work by default
+ * in o32 format...grrr...
+*/
 
-/* This is annoying...we can't actually write the 64-bit IO 
-   register properly without having access to 64-bit registers...
-   which doesn't work by default in o32 format...grrr...*/
-extern inline void out64(u64 val, unsigned long addr)
+static inline void out64(u64 val, unsigned long addr)
 {
-	u32 low, high;
+	u32 low, high, tmp;
 	unsigned long flags;
+
 	high = val >> 32;
 	low = val & 0xffffffff;
-	// save_flags(flags);
 	__save_and_cli(flags);
 	__asm__ __volatile__ (
-		".set push\n"
+		".set push\t\t\t# out64n"
 		".set noreorder\n"
 		".set noat\n"
 		".set mips4\n"
-		"   dsll32 $2, %1, 0   \n"
-		"   dsll32 $1, %0, 0   \n"
-		"   dsrl32 $2, $2, 0   \n"
-		"   or     $1, $1, $2  \n"
-		"   sd $1, (%2)\n"
+		"   dsll32 %0, %2, 0   \n"
+		"   dsll32 $1, %1, 0   \n"
+		"   dsrl32 %0, %0, 0   \n"
+		"   or     $1, $1, %0  \n"
+		"   sd $1, (%3)\n"
 		".set pop\n"
-		::"r" (high), "r" (low), "r" (addr)
-		:"$1", "$2");
+		: "=&r" (tmp)
+		: "r" (high), "r" (low), "r" (addr));
 	__restore_flags(flags);
 }
 
-extern inline u64 in64(unsigned long addr)
+static inline u64 in64(unsigned long addr)
 {
-	u32 low, high;
 	unsigned long flags;
+	u32 low, high;
+
 	__save_and_cli(flags);
 	__asm__ __volatile__ (
-		".set push\n"
+		".set push\t\t\t# in64\n"
 		".set noreorder\n"
 		".set noat     \n"
 		".set mips4    \n"
@@ -63,9 +67,11 @@
 		"  dsra32 %0, %1, 0\n"
 		"  sll    %1, %1, 0\n"
 		".set pop\n"
-		:"=r" (high), "=r" (low): "r" (addr));
+		: "=r" (high), "=r" (low)
+		: "r" (addr));
 	__restore_flags(flags);
+
 	return (((u64)high) << 32) | low;
 }
 
-#endif
+#endif /* _SB1_64BIT_H */

[Linux-mips-commits]CVS: linux/include/asm-mips64/sibyte 64bit.h,1.1,1.2

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/include/asm-mips64/sibyte
In directory usw-pr-cvs1:/tmp/cvs-serv8152/asm-mips64/sibyte

Modified Files:
	64bit.h 
Log Message:
Minor code overhaul.

Index: 64bit.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips64/sibyte/64bit.h,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- 64bit.h	8 Nov 2001 17:28:25 -0000	1.1
+++ 64bit.h	19 Feb 2002 17:45:04 -0000	1.2
@@ -19,7 +19,7 @@
 #ifndef _ASM_SIBYTE_64BIT_H
 #define _ASM_SIBYTE_64BIT_H
 
-#include <asm/types.h>
+#include <linux/types.h>
 
 /* These are provided so as to be able to use common
    driver code for the 32-bit and 64-bit trees */
@@ -34,4 +34,4 @@
 	return *(volatile unsigned long *)addr;
 }
 
-#endif
+#endif /* _ASM_SIBYTE_64BIT_H */

[Linux-mips-commits]CVS: linux/arch/mips64/mm andes.c,1.9,1.10 loadmmu.c,1.5,1.6 r4xx0.c,1.12,1.13

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips64/mm
In directory usw-pr-cvs1:/tmp/cvs-serv7093/arch/mips64/mm

Modified Files:
	andes.c loadmmu.c r4xx0.c 
Log Message:
Unify show_regs() for all 64-bit processors.

Index: andes.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips64/mm/andes.c,v
retrieving revision 1.9
retrieving revision 1.10
diff -u -d -r1.9 -r1.10
--- andes.c	28 Jan 2002 20:31:57 -0000	1.9
+++ andes.c	19 Feb 2002 17:43:02 -0000	1.10
@@ -298,36 +298,6 @@
 	__restore_flags(flags);
 }
 
-static void andes_show_regs(struct pt_regs *regs)
-{
-	printk("Cpu %d\n", smp_processor_id());
-	/* Saved main processor registers. */
-	printk("$0      : %016lx %016lx %016lx %016lx\n",
-	       0UL, regs->regs[1], regs->regs[2], regs->regs[3]);
-	printk("$4      : %016lx %016lx %016lx %016lx\n",
-               regs->regs[4], regs->regs[5], regs->regs[6], regs->regs[7]);
-	printk("$8      : %016lx %016lx %016lx %016lx\n",
-	       regs->regs[8], regs->regs[9], regs->regs[10], regs->regs[11]);
-	printk("$12     : %016lx %016lx %016lx %016lx\n",
-               regs->regs[12], regs->regs[13], regs->regs[14], regs->regs[15]);
-	printk("$16     : %016lx %016lx %016lx %016lx\n",
-	       regs->regs[16], regs->regs[17], regs->regs[18], regs->regs[19]);
-	printk("$20     : %016lx %016lx %016lx %016lx\n",
-               regs->regs[20], regs->regs[21], regs->regs[22], regs->regs[23]);
-	printk("$24     : %016lx %016lx\n",
-	       regs->regs[24], regs->regs[25]);
-	printk("$28     : %016lx %016lx %016lx %016lx\n",
-	       regs->regs[28], regs->regs[29], regs->regs[30], regs->regs[31]);
-	printk("Hi      : %016lx\n", regs->hi);
-	printk("Lo      : %016lx\n", regs->lo);
-
-	/* Saved cp0 registers. */
-	printk("epc     : %016lx    %s\nbadvaddr: %016lx\n",
-	       regs->cp0_epc, print_tainted(), regs->cp0_badvaddr);
-	printk("Status  : %08x\nCause   : %08x\n",
-	       (unsigned int) regs->cp0_status, (unsigned int) regs->cp0_cause);
-}
-
 void __init ld_mmu_andes(void)
 {
 	printk("CPU revision is: %08x\n", read_32bit_cp0_register(CP0_PRID));
@@ -359,8 +329,6 @@
 	}
     
 	_update_mmu_cache = andes_update_mmu_cache;
-
-	_show_regs = andes_show_regs;
 
         flush_cache_l1();
 

Index: loadmmu.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips64/mm/loadmmu.c,v
retrieving revision 1.5
retrieving revision 1.6
diff -u -d -r1.5 -r1.6
--- loadmmu.c	14 Feb 2002 20:48:54 -0000	1.5
+++ loadmmu.c	19 Feb 2002 17:43:02 -0000	1.6
@@ -50,8 +50,6 @@
 void (*_update_mmu_cache)(struct vm_area_struct * vma,
 	unsigned long address, pte_t pte);
 
-void (*_show_regs)(struct pt_regs *);
-
 extern void ld_mmu_r4xx0(void);
 extern void ld_mmu_andes(void);
 extern void ld_mmu_sb1(void);

Index: r4xx0.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips64/mm/r4xx0.c,v
retrieving revision 1.12
retrieving revision 1.13
diff -u -d -r1.12 -r1.13
--- r4xx0.c	28 Jan 2002 20:31:57 -0000	1.12
+++ r4xx0.c	19 Feb 2002 17:43:02 -0000	1.13
@@ -2081,35 +2081,6 @@
 }
 #endif
 
-static void r4k_show_regs(struct pt_regs *regs)
-{
-	/* Saved main processor registers. */
-	printk("$0      : %016lx %016lx %016lx %016lx\n",
-	       0UL, regs->regs[1], regs->regs[2], regs->regs[3]);
-	printk("$4      : %016lx %016lx %016lx %016lx\n",
-               regs->regs[4], regs->regs[5], regs->regs[6], regs->regs[7]);
-	printk("$8      : %016lx %016lx %016lx %016lx\n",
-	       regs->regs[8], regs->regs[9], regs->regs[10], regs->regs[11]);
-	printk("$12     : %016lx %016lx %016lx %016lx\n",
-               regs->regs[12], regs->regs[13], regs->regs[14], regs->regs[15]);
-	printk("$16     : %016lx %016lx %016lx %016lx\n",
-	       regs->regs[16], regs->regs[17], regs->regs[18], regs->regs[19]);
-	printk("$20     : %016lx %016lx %016lx %016lx\n",
-               regs->regs[20], regs->regs[21], regs->regs[22], regs->regs[23]);
-	printk("$24     : %016lx %016lx\n",
-	       regs->regs[24], regs->regs[25]);
-	printk("$28     : %016lx %016lx %016lx %016lx\n",
-	       regs->regs[28], regs->regs[29], regs->regs[30], regs->regs[31]);
-	printk("Hi      : %016lx\n", regs->hi);
-	printk("Lo      : %016lx\n", regs->lo);
-
-	/* Saved cp0 registers. */
-	printk("epc     : %016lx    %s\nbadvaddr: %016lx\n",
-	       regs->cp0_epc, print_tainted(), regs->cp0_badvaddr);
-	printk("Status  : %08x\nCause   : %08x\n",
-	       (unsigned int) regs->cp0_status, (unsigned int) regs->cp0_cause);
-}
-
 /* Detect and size the various r4k caches. */
 static void __init probe_icache(unsigned long config)
 {
@@ -2389,8 +2360,6 @@
 	_flush_cache_l2 = r4k_flush_cache_l2;
 
 	_update_mmu_cache = r4k_update_mmu_cache;
-
-	_show_regs = r4k_show_regs;
 
 	flush_cache_l1();
 

[Linux-mips-commits]CVS: linux/arch/mips64/kernel traps.c,1.12,1.13

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips64/kernel
In directory usw-pr-cvs1:/tmp/cvs-serv7093/arch/mips64/kernel

Modified Files:
	traps.c 
Log Message:
Unify show_regs() for all 64-bit processors.

Index: traps.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips64/kernel/traps.c,v
retrieving revision 1.12
retrieving revision 1.13
diff -u -d -r1.12 -r1.13
--- traps.c	28 Jan 2002 20:31:57 -0000	1.12
+++ traps.c	19 Feb 2002 17:43:02 -0000	1.13
@@ -166,6 +166,50 @@
 	}
 }
 
+void show_regs(struct pt_regs *regs)
+{
+	printk("Cpu %d\n", smp_processor_id());
+	/* Saved main processor registers. */
+	printk("$0      : %016lx %016lx %016lx %016lx\n",
+	       0UL, regs->regs[1], regs->regs[2], regs->regs[3]);
+	printk("$4      : %016lx %016lx %016lx %016lx\n",
+               regs->regs[4], regs->regs[5], regs->regs[6], regs->regs[7]);
+	printk("$8      : %016lx %016lx %016lx %016lx\n",
+	       regs->regs[8], regs->regs[9], regs->regs[10], regs->regs[11]);
+	printk("$12     : %016lx %016lx %016lx %016lx\n",
+               regs->regs[12], regs->regs[13], regs->regs[14], regs->regs[15]);
+	printk("$16     : %016lx %016lx %016lx %016lx\n",
+	       regs->regs[16], regs->regs[17], regs->regs[18], regs->regs[19]);
+	printk("$20     : %016lx %016lx %016lx %016lx\n",
+               regs->regs[20], regs->regs[21], regs->regs[22], regs->regs[23]);
+	printk("$24     : %016lx %016lx\n",
+	       regs->regs[24], regs->regs[25]);
+	printk("$28     : %016lx %016lx %016lx %016lx\n",
+	       regs->regs[28], regs->regs[29], regs->regs[30], regs->regs[31]);
+	printk("Hi      : %016lx\n", regs->hi);
+	printk("Lo      : %016lx\n", regs->lo);
+
+	/* Saved cp0 registers. */
+	printk("epc     : %016lx    %s\nbadvaddr: %016lx\n",
+	       regs->cp0_epc, print_tainted(), regs->cp0_badvaddr);
+	printk("Status  : %08x  [ ", (unsigned int) regs->cp0_status);
+	if (regs->cp0_status & ST0_KX) printk("KX ");
+	if (regs->cp0_status & ST0_SX) printk("SX ");
+	if (regs->cp0_status & ST0_UX) printk("UX ");
+	switch (regs->cp0_status & ST0_KSU) {
+		case KSU_USER: printk("USER ");			break;
+		case KSU_SUPERVISOR: printk("SUPERVISOR ");	break;
+		case KSU_KERNEL: printk("KERNEL ");		break;
+		default: printk("BAD_MODE ");			break;
+	}
+	if (regs->cp0_status & ST0_ERL) printk("ERL ");
+	if (regs->cp0_status & ST0_EXL) printk("EXL ");
+	if (regs->cp0_status & ST0_IE) printk("IE ");
+	printk("]\n");
+
+	printk("Cause   : %08x\n", (unsigned int) regs->cp0_cause);
+}
+
 static spinlock_t die_lock;
 
 void die(const char * str, struct pt_regs * regs)
@@ -545,6 +589,7 @@
 {
 	unsigned long handler = (unsigned long) addr;
 	exception_handlers[n] = handler;
+
 	if (n == 0 && mips_cpu.options & MIPS_CPU_DIVEC) {
 		*(volatile u32 *)(KSEG0+0x200) = 0x08000000 |
 		                                 (0x03ffffff & (handler >> 2));
@@ -618,7 +663,7 @@
 		/* Enable timer interrupt and scd mapped interrupt */
 		clear_cp0_status(0xf000);
 		set_cp0_status(0xc00);
-		break;
+		goto nocache;
 
 	case CPU_R10000:
 	case CPU_R4000MC:
@@ -632,19 +677,20 @@
 	case CPU_R4600:
 	case CPU_R5000:
 	case CPU_NEVADA:
+		/* Cache error vector  */
+		memcpy((void *)(KSEG0 + 0x100), (void *) KSEG0, 0x80);
+
+nocache:
 		/* Debug TLB refill handler.  */
 		memcpy((void *)KSEG0, &except_vec0, 0x80);
 		memcpy((void *)KSEG0 + 0x080, &except_vec1_r10k, 0x80);
 
-		/* Cache error vector  */
-		memcpy((void *)(KSEG0 + 0x100), (void *) KSEG0, 0x80);
-
 		if (mips_cpu.options & MIPS_CPU_VCE) {
 			memcpy((void *)(KSEG0 + 0x180), &except_vec3_r4000,
-			       0x180);
+			       0x80);
 		} else {
 			memcpy((void *)(KSEG0 + 0x180), &except_vec3_generic,
-			       0x100);
+			       0x80);
 		}
 
 		set_except_vector(1, __xtlb_mod);

[Linux-mips-commits]CVS: linux/include/asm-mips64 ptrace.h,1.1,1.2

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/include/asm-mips64
In directory usw-pr-cvs1:/tmp/cvs-serv7093/include/asm-mips64

Modified Files:
	ptrace.h 
Log Message:
Unify show_regs() for all 64-bit processors.

Index: ptrace.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips64/ptrace.h,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- ptrace.h	12 Feb 2002 18:00:14 -0000	1.1
+++ ptrace.h	19 Feb 2002 17:43:02 -0000	1.2
@@ -76,9 +76,6 @@
 #ifndef _LANGUAGE_ASSEMBLY
 #define instruction_pointer(regs) ((regs)->cp0_epc)
 
-extern void (*_show_regs)(struct pt_regs *);
-#define show_regs(regs)	_show_regs(regs)
-
 #endif /* !(_LANGUAGE_ASSEMBLY__) */
 
 #endif

[Linux-mips-commits]CVS: linux/arch/mips/mm c-andes.c,1.3,1.4

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips/mm
In directory usw-pr-cvs1:/tmp/cvs-serv7093/arch/mips/mm

Modified Files:
	c-andes.c 
Log Message:
Unify show_regs() for all 64-bit processors.

Index: c-andes.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/mm/c-andes.c,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- c-andes.c	27 Nov 2001 17:53:47 -0000	1.3
+++ c-andes.c	19 Feb 2002 17:43:02 -0000	1.4
@@ -125,7 +125,5 @@
 			while(1);
 	}
     
-	update_mmu_cache = andes_update_mmu_cache;
-
         flush_cache_l1();
 }

[Linux-mips-commits]CVS: linux/arch/mips/mm c-r3k.c,1.5,1.6

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips/mm
In directory usw-pr-cvs1:/tmp/cvs-serv4046

Modified Files:
	c-r3k.c 
Log Message:
Fix flushing the cache for KUSEG/KSEG2.

Index: c-r3k.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/mm/c-r3k.c,v
retrieving revision 1.5
retrieving revision 1.6
diff -u -d -r1.5 -r1.6
--- c-r3k.c	28 Nov 2001 17:28:31 -0000	1.5
+++ c-r3k.c	19 Feb 2002 17:37:17 -0000	1.6
@@ -107,11 +107,14 @@
 static void r3k_flush_icache_range(unsigned long start, unsigned long end)
 {
 	unsigned long size, i, flags;
-	volatile unsigned char *p = (char *)start;
+	volatile unsigned char *p;
 
 	size = end - start;
-	if (size > icache_size)
+	if (size > icache_size || KSEGX(start) != KSEG0) {
+		start = KSEG0;
 		size = icache_size;
+	}
+	p = (char *)start;
 
 	flags = read_32bit_cp0_register(CP0_STATUS);
 
@@ -161,11 +164,14 @@
 static void r3k_flush_dcache_range(unsigned long start, unsigned long end)
 {
 	unsigned long size, i, flags;
-	volatile unsigned char *p = (char *)start;
+	volatile unsigned char *p;
 
 	size = end - start;
-	if (size > dcache_size)
+	if (size > dcache_size || KSEGX(start) != KSEG0) {
+		start = KSEG0;
 		size = dcache_size;
+	}
+	p = (char *)start;
 
 	flags = read_32bit_cp0_register(CP0_STATUS);
 
@@ -331,9 +337,7 @@
 	_flush_icache_page = r3k_flush_icache_page;
 	_flush_icache_range = r3k_flush_icache_range;
 
-#ifdef CONFIG_NONCOHERENT_IO
 	_dma_cache_wback_inv = r3k_dma_cache_wback_inv;
-#endif /* CONFIG_NONCOHERENT_IO */
 
 	printk("Primary instruction cache %dkb, linesize %d bytes\n",
 		(int) (icache_size >> 10), (int) icache_lsize);

[Linux-mips-commits]CVS: linux/arch/mips/sibyte/swarm smp.c,1.5,1.6

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips/sibyte/swarm
In directory usw-pr-cvs1:/tmp/cvs-serv3062

Modified Files:
	smp.c 
Log Message:
Initialize c0_context to 0. Seems like it always was just coincidence that any SMP kernel ever worked ...

Index: smp.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/sibyte/swarm/smp.c,v
retrieving revision 1.5
retrieving revision 1.6
diff -u -d -r1.5 -r1.6
--- smp.c	28 Jan 2002 20:31:57 -0000	1.5
+++ smp.c	19 Feb 2002 17:35:33 -0000	1.6
@@ -38,10 +38,12 @@
 int prom_boot_secondary(int cpu, unsigned long sp, unsigned long gp)
 {
 	int retval;
+
 	if ((retval = cfe_start_cpu(1, &smp_bootstrap, sp, gp, 0)) != 0) {
 		printk("cfe_start_cpu returned %i\n" , retval);
 		panic("secondary bootstrap failed");
 	}
+
 	return 1;
 }
 
@@ -84,6 +86,7 @@
 {
 	int i;
 
+	set_context(0);
 	smp_num_cpus = prom_setup_smp();
 	init_new_context(current, &init_mm);
 	current->processor = 0;
@@ -147,5 +150,6 @@
 
 	/* Wait for everyone to come up */
 	while (atomic_read(&cpus_booted) != smp_num_cpus);
+
 	smp_threads_ready = 1;
 }

[Linux-mips-commits]CVS: linux/arch/mips/sibyte/swarm setup.c,1.8,1.9

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips/sibyte/swarm
In directory usw-pr-cvs1:/tmp/cvs-serv2322

Modified Files:
	setup.c 
Log Message:
Set MAX_RAM_SIZE correctly for 64-bit kernel. Delete some more of the now unused standalone code.

Index: setup.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/sibyte/swarm/setup.c,v
retrieving revision 1.8
retrieving revision 1.9
diff -u -d -r1.8 -r1.9
--- setup.c	12 Feb 2002 18:04:27 -0000	1.8
+++ setup.c	19 Feb 2002 17:34:24 -0000	1.9
@@ -58,14 +58,17 @@
 /* Max ram addressable in 32-bit segments */
 #ifdef CONFIG_HIGHMEM
 #ifdef CONFIG_64BIT_PHYS_ADDR
-/* #define MAX_RAM_SIZE (0xffffffffffffffff) */
 #define MAX_RAM_SIZE (~0ULL)
 #else
 #define MAX_RAM_SIZE (0xffffffffULL)
 #endif
 #else
+#ifdef CONFIG_MIPS64
+#define MAX_RAM_SIZE (~0ULL)
+#else
 #define MAX_RAM_SIZE (0x1fffffffULL)
 #endif
+#endif
 
 
 #ifndef CONFIG_SWARM_STANDALONE
@@ -400,9 +403,6 @@
  */
 __init int prom_init(int argc, char **argv, char **envp, int *prom_vec)
 {
-#ifdef CONFIG_SWARM_STANDALONE
-	strcpy(arcs_cmdline, "root=/dev/ram0 ");
-#else	
 	/* 
 	 * This should go away.  Detect if we're booting
 	 * straight from cfe without a loader.  If we
@@ -427,7 +427,7 @@
 			panic("LINUX_CMDLINE not defined in cfe.");
 		}
 	}
-	
+
 #ifdef CONFIG_BLK_DEV_INITRD
 	{
 		char *ptr;
@@ -448,7 +448,6 @@
 		}
 	}
 #endif /* CONFIG_BLK_DEV_INITRD */
-#endif /* CONFIG_SWARM_STANDALONE */
 
 	/* Not sure this is needed, but it's the safe way. */
 	arcs_cmdline[CL_SIZE-1] = 0;

[Linux-mips-commits]CVS: linux/arch/mips/sibyte/swarm cfe_api.c,1.2,1.3

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips/sibyte/swarm
In directory usw-pr-cvs1:/tmp/cvs-serv1348

Modified Files:
	cfe_api.c 
Log Message:
Reformat.

Index: cfe_api.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/sibyte/swarm/cfe_api.c,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -d -r1.2 -r1.3
--- cfe_api.c	28 Jan 2002 20:31:57 -0000	1.2
+++ cfe_api.c	19 Feb 2002 17:32:53 -0000	1.3
@@ -55,10 +55,11 @@
 	return 0;
 }
 
-int cfe_iocb_dispatch(cfe_xiocb_t *xiocb);
 int cfe_iocb_dispatch(cfe_xiocb_t *xiocb)
 {
-	if (!cfe_dispfunc) return -1;
+	if (!cfe_dispfunc)
+		return -1;
+
 	return (*cfe_dispfunc)(cfe_handle,xiocb);
 }
 
@@ -343,7 +344,7 @@
 int cfe_start_cpu(int cpu, void (*fn)(void), long sp, long gp, long a1)
 {
 	cfe_xiocb_t xiocb;
-	
+
 	xiocb.xiocb_fcode = CFE_CMD_FW_CPUCTL;
 	xiocb.xiocb_status = 0;
 	xiocb.xiocb_handle = 0;
@@ -355,9 +356,9 @@
 	xiocb.plist.xiocb_cpuctl.sp_val = sp;
 	xiocb.plist.xiocb_cpuctl.a1_val = a1;
 	xiocb.plist.xiocb_cpuctl.start_addr = (long)fn;
-	
+
 	cfe_iocb_dispatch(&xiocb);
-	
+
 	return xiocb.xiocb_status;
 }
 
@@ -383,4 +384,3 @@
 		} while (len);
 	}
 }
-

[Linux-mips-commits]CVS: linux/arch/mips/sibyte/sb1250 time.c,1.3,1.4

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips/sibyte/sb1250
In directory usw-pr-cvs1:/tmp/cvs-serv929

Modified Files:
	time.c 
Log Message:
Reformat to 80 columns.

Index: time.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/sibyte/sb1250/time.c,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- time.c	17 Dec 2001 18:49:39 -0000	1.3
+++ time.c	19 Feb 2002 17:32:08 -0000	1.4
@@ -83,7 +83,9 @@
 	 * This interrupt is "special" in that it doesn't use the request_irq
 	 * way to hook the irq line.  The timer interrupt is initialized early
 	 * enough to make this a major pain, and it's also firing enough to
-	 * warrant a bit of special case code.  sb1250_timer_interrupt is called	 * directly from irq_handler.S when IP[4] is set during an interrupt
+	 * warrant a bit of special case code.  sb1250_timer_interrupt is
+	 * called directly from irq_handler.S when IP[4] is set during an
+	 * interrupt
 	 */
 }
 

[Linux-mips-commits]CVS: linux/arch/mips/sibyte/sb1250 irq_handler.S,1.5,1.6

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips/sibyte/sb1250
In directory usw-pr-cvs1:/tmp/cvs-serv690

Modified Files:
	irq_handler.S 
Log Message:
Include <linux/config.h>.

Index: irq_handler.S
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/sibyte/sb1250/irq_handler.S,v
retrieving revision 1.5
retrieving revision 1.6
diff -u -d -r1.5 -r1.6
--- irq_handler.S	28 Jan 2002 20:31:57 -0000	1.5
+++ irq_handler.S	19 Feb 2002 17:31:44 -0000	1.6
@@ -28,6 +28,8 @@
  * Note that we take care of all raised interrupts in one go at the handler.
  * This is more BSDish than the Indy code, and also, IMHO, more sane. 
  */
+#include <linux/config.h>
+
 #include <asm/addrspace.h>
 #include <asm/processor.h>
 #include <asm/asm.h>

[Linux-mips-commits]CVS: linux/arch/mips/sibyte/sb1 cache_err_handler.S,1.3,1.4

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips/sibyte/sb1
In directory usw-pr-cvs1:/tmp/cvs-serv32466

Modified Files:
	cache_err_handler.S 
Log Message:
Include <linux/config.h>.  Reformat.

Index: cache_err_handler.S
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/sibyte/sb1/cache_err_handler.S,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- cache_err_handler.S	28 Jan 2002 20:31:57 -0000	1.3
+++ cache_err_handler.S	19 Feb 2002 17:30:21 -0000	1.4
@@ -15,6 +15,7 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  */
+#include <linux/config.h>
 
 #include <asm/asm.h>
 #include <asm/regdef.h>
@@ -39,8 +40,9 @@
 	mfc0	k1, $26				# mfc0	k1, $26, 0
 	# check if error was recoverable
 	# XXXKW - count them
-	bltz	k1,leave_cerr
+	bltz	k1, leave_cerr
 	 nop
+
 #ifdef CONFIG_SB1_PASS_1_WORKAROUNDS
 	# look for signature of spurious CErr
 	lui	k0, 0x4000
@@ -65,11 +67,11 @@
 	eret
 
 real_cerr:
-	mfc0	k0,CP0_CONFIG
-	li	k1,~CONF_CM_CMASK
-	and	k0,k0,k1
-	ori	k0,k0,CONF_CM_UNCACHED
-	mtc0	k0,CP0_CONFIG
+	mfc0	k0, CP0_CONFIG
+	li	k1, ~CONF_CM_CMASK
+	and	k0, k0, k1
+	ori	k0, k0, CONF_CM_UNCACHED
+	mtc0	k0, CP0_CONFIG
 	/* Give it a few cycles to sink in... */
 	sll     zero, zero, 0x1			# ssnop
 	sll     zero, zero, 0x1			# ssnop

[Linux-mips-commits]CVS: linux/arch/mips64/mm tlb-sb1.c,1.1,1.2

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips64/mm
In directory usw-pr-cvs1:/tmp/cvs-serv31813

Modified Files:
	tlb-sb1.c 
Log Message:
Reformat.

Index: tlb-sb1.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips64/mm/tlb-sb1.c,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- tlb-sb1.c	28 Jan 2002 20:31:57 -0000	1.1
+++ tlb-sb1.c	19 Feb 2002 17:29:13 -0000	1.2
@@ -274,7 +274,7 @@
 	set_entrylo0(pte_val(*ptep++) >> 6);
 	set_entrylo1(pte_val(*ptep) >> 6);
 	set_entryhi(address | (pid));
-	if(idx < 0) {
+	if (idx < 0) {
 		tlb_write_random();
 	} else {
 		tlb_write_indexed();

[Linux-mips-commits]CVS: linux/include/asm-mips64 pgtable.h,1.10,1.11

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/include/asm-mips64
In directory usw-pr-cvs1:/tmp/cvs-serv30792

Modified Files:
	pgtable.h 
Log Message:
Fix non-R10k version of flush_icache_page(). For happyness of the build system include <linux/config.h> at the top.

Index: pgtable.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips64/pgtable.h,v
retrieving revision 1.10
retrieving revision 1.11
diff -u -d -r1.10 -r1.11
--- pgtable.h	12 Feb 2002 18:05:27 -0000	1.10
+++ pgtable.h	19 Feb 2002 17:27:39 -0000	1.11
@@ -9,13 +9,13 @@
 #ifndef _ASM_PGTABLE_H
 #define _ASM_PGTABLE_H
 
+#include <linux/config.h>
 #include <asm/addrspace.h>
 #include <asm/page.h>
 
 #ifndef _LANGUAGE_ASSEMBLY
 
 #include <linux/linkage.h>
-#include <linux/config.h>
 #include <linux/mmzone.h>
 #include <asm/cachectl.h>
 
@@ -78,15 +78,9 @@
 #define flush_cache_range(mm,start,end)	_flush_cache_range(mm,start,end)
 #define flush_cache_page(vma,page)	_flush_cache_page(vma, page)
 #define flush_page_to_ram(page)		_flush_page_to_ram(page)
+#define flush_icache_range(start, end)	_flush_icache_range(start, end)
+#define flush_icache_page(vma, page)	_flush_icache_page(vma, page)
 
-#define flush_icache_range(start, end)	_flush_cache_l1()
-
-#define flush_icache_page(vma, page)					\
-do {									\
-	unsigned long addr;						\
-	addr = (unsigned long) page_address(page);			\
-	_flush_cache_page(vma, addr);					\
-} while (0)                                                              
 #endif /* !CONFIG_CPU_R10000 */
 
 #define flush_cache_sigtramp(addr)	_flush_cache_sigtramp(addr)

[Linux-mips-commits]CVS: linux/include/asm-mips64 mipsregs.h,1.9,1.10

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/include/asm-mips64
In directory usw-pr-cvs1:/tmp/cvs-serv29634/asm-mips64

Modified Files:
	mipsregs.h 
Log Message:
Add pagemask and shift values for 64mb and 256mb pages. For mips64 implement get_xcontext() and set_xcontext() to access c0_xcontext. For mips32 remove pointless comment.

Index: mipsregs.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips64/mipsregs.h,v
retrieving revision 1.9
retrieving revision 1.10
diff -u -d -r1.9 -r1.10
--- mipsregs.h	28 Jan 2002 20:32:05 -0000	1.9
+++ mipsregs.h	19 Feb 2002 17:25:25 -0000	1.10
@@ -149,34 +149,40 @@
 #include <linux/config.h>
 #ifdef CONFIG_CPU_VR41XX
 
-#define PM_1K   0x00000000
-#define PM_4K   0x00001800
-#define PM_16K  0x00007800
-#define PM_64K  0x0001f800
-#define PM_256K 0x0007f800
+/* Why doesn't stupidity hurt ... */
+
+#define PM_1K		0x00000000
+#define PM_4K		0x00001800
+#define PM_16K		0x00007800
+#define PM_64K		0x0001f800
+#define PM_256K		0x0007f800
 
 #else
 
-#define PM_4K   0x00000000
-#define PM_16K  0x00006000
-#define PM_64K  0x0001e000
-#define PM_256K 0x0007e000
-#define PM_1M   0x001fe000
-#define PM_4M   0x007fe000
-#define PM_16M  0x01ffe000
+#define PM_4K		0x00000000
+#define PM_16K		0x00006000
+#define PM_64K		0x0001e000
+#define PM_256K		0x0007e000
+#define PM_1M		0x001fe000
+#define PM_4M		0x007fe000
+#define PM_16M		0x01ffe000
+#define PM_64M		0x07ffe000
+#define PM_256M		0x1fffe000
 
 #endif
 
 /*
  * Values used for computation of new tlb entries
  */
-#define PL_4K   12
-#define PL_16K  14
-#define PL_64K  16
-#define PL_256K 18
-#define PL_1M   20
-#define PL_4M   22
-#define PL_16M  24
+#define PL_4K		12
+#define PL_16K		14
+#define PL_64K		16
+#define PL_256K		18
+#define PL_1M		20
+#define PL_4M		22
+#define PL_16M		24
+#define PL_64M		26
+#define PL_256M		28
 
 /*
  * R4x00 interrupt enable / cause bits
@@ -743,7 +749,6 @@
 		: : "Jr" (val));
 }
 
-/* CP0_CONTEXT register */
 static inline unsigned long get_context(void)
 {
 	unsigned long val;
@@ -762,6 +767,28 @@
 	__asm__ __volatile__(
 		".set noreorder\n\t"
 		"dmtc0 %z0, $4\n\t"
+		".set reorder"
+		: : "Jr" (val));
+}
+
+static inline unsigned long get_xcontext(void)
+{
+	unsigned long val;
+
+	__asm__ __volatile__(
+		".set noreorder\n\t"
+		"dmfc0 %0, $20\n\t"
+		".set reorder"
+		: "=r" (val));
+
+	return val;
+}
+
+static inline void set_xcontext(unsigned long val)
+{
+	__asm__ __volatile__(
+		".set noreorder\n\t"
+		"dmtc0 %z0, $20\n\t"
 		".set reorder"
 		: : "Jr" (val));
 }