linux-mips-commits — CVS Commit Patches

[Linux-mips-commits]CVS: linux/include/asm-mips64 stackframe.h,NONE,1.1

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/include/asm-mips64
In directory usw-pr-cvs1:/tmp/cvs-serv23768/include/asm-mips64

Added Files:
	stackframe.h 
Log Message:
Most of it was a collection of fixes and cleanups for mips64 and SMP stuff

--- NEW FILE: stackframe.h ---
/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 1994, 1995, 1996, 1999 Ralf Baechle
 * Copyright (C) 1994, 1995, 1996 Paul M. Antoine.
 * Copyright (C) 1999 Silicon Graphics, Inc.
 */
#ifndef _ASM_STACKFRAME_H
#define _ASM_STACKFRAME_H

#include <linux/config.h>

#include <asm/asm.h>
#include <asm/offset.h>
#include <asm/processor.h>
#include <asm/addrspace.h>

#ifdef _LANGUAGE_C

#define __str2(x) #x
#define __str(x) __str2(x)

#define save_static(frame)                               \
	__asm__ __volatile__(                            \
		"sd\t$16,"__str(PT_R16)"(%0)\n\t"        \
		"sd\t$17,"__str(PT_R17)"(%0)\n\t"        \
		"sd\t$18,"__str(PT_R18)"(%0)\n\t"        \
		"sd\t$19,"__str(PT_R19)"(%0)\n\t"        \
		"sd\t$20,"__str(PT_R20)"(%0)\n\t"        \
		"sd\t$21,"__str(PT_R21)"(%0)\n\t"        \
		"sd\t$22,"__str(PT_R22)"(%0)\n\t"        \
		"sd\t$23,"__str(PT_R23)"(%0)\n\t"        \
		"sd\t$30,"__str(PT_R30)"(%0)\n\t"        \
		: /* No outputs */                       \
		: "r" (frame))

#endif /* _LANGUAGE_C */

#ifdef _LANGUAGE_ASSEMBLY

		.macro	SAVE_AT
		.set	push
		.set	noat
		sd	$1, PT_R1(sp)
		.set	pop
		.endm

		.macro	SAVE_TEMP
		mfhi	v1
		sd	$8, PT_R8(sp)
		sd	$9, PT_R9(sp)
		sd	v1, PT_HI(sp)
		mflo	v1
		sd	$10, PT_R10(sp)
		sd	$11, PT_R11(sp)
		sd	v1,  PT_LO(sp)
		sd	$12, PT_R12(sp)
		sd	$13, PT_R13(sp)
		sd	$14, PT_R14(sp)
		sd	$15, PT_R15(sp)
		sd	$24, PT_R24(sp)
		.endm

		.macro	SAVE_STATIC
		sd	$16, PT_R16(sp)
		sd	$17, PT_R17(sp)
		sd	$18, PT_R18(sp)
		sd	$19, PT_R19(sp)
		sd	$20, PT_R20(sp)
		sd	$21, PT_R21(sp)
		sd	$22, PT_R22(sp)
		sd	$23, PT_R23(sp)
		sd	$30, PT_R30(sp)
		.endm

#ifdef CONFIG_SMP
		.macro	get_saved_sp	/* R10000 variation */
		mfc0	k0, CP0_WATCHLO
		mfc0	k1, CP0_WATCHHI
		dsll32	k0, k0, 0	/* Get rid of sign extension */
		dsrl32	k0, k0, 0	/* Get rid of sign extension */
		dsll32	k1, k1, 0
		or	k1, k1, k0
		li	k0, K0BASE
		or	k1, k1, k0
		.endm

		.macro	set_saved_sp	stackp temp
		mtc0	\stackp, CP0_WATCHLO
		dsrl32	\temp, \stackp, 0
		mtc0	\temp, CP0_WATCHHI
		.endm

		.macro	declare_saved_sp
		# empty, stackpointer stored in a register
		.endm
#else
		.macro	get_saved_sp	/* Uniprocessor variation */
		lui	k1, %hi(kernelsp)
		ld	k1, %lo(kernelsp)(k1)
		.endm

		.macro	set_saved_sp	stackp temp
		sd	\stackp, kernelsp
		.endm

		.macro	declare_saved_sp
		.comm	kernelsp, 8, 8			# current stackpointer
		.endm
#endif

		.macro	SAVE_SOME
		.set	push
		.set	reorder
		mfc0	k0, CP0_STATUS
		sll	k0, 3		/* extract cu0 bit */
		.set	noreorder
		bltz	k0, 8f
		 move	k1, sp
		.set	reorder
		/* Called from user mode, new stack. */
		get_saved_sp
8:		move	k0, sp
		dsubu	sp, k1, PT_SIZE
		sd	k0, PT_R29(sp)
		sd	$3, PT_R3(sp)
		sd	$0, PT_R0(sp)
		dmfc0	v1, CP0_STATUS
		sd	$2, PT_R2(sp)
		sd	v1, PT_STATUS(sp)
		sd	$4, PT_R4(sp)
		dmfc0	v1, CP0_CAUSE
		sd	$5, PT_R5(sp)
		sd	v1, PT_CAUSE(sp)
		sd	$6, PT_R6(sp)
		dmfc0	v1, CP0_EPC
		sd	$7, PT_R7(sp)
		sd	v1, PT_EPC(sp)
		sd	$25, PT_R25(sp)
		sd	$28, PT_R28(sp)
		sd	$31, PT_R31(sp)
		ori	$28, sp, 0x3fff
		xori	$28, 0x3fff
		.set	pop
		.endm

		.macro	SAVE_ALL
		SAVE_SOME
		SAVE_AT
		SAVE_TEMP
		SAVE_STATIC
		.endm

		.macro	RESTORE_AT
		.set	push
		.set	noat
		ld	$1,  PT_R1(sp)
		.set	pop
		.endm

		.macro	RESTORE_SP
		ld	sp,  PT_R29(sp)
		.endm

		.macro	RESTORE_TEMP
		ld	$24, PT_LO(sp)
		ld	$8, PT_R8(sp)
		ld	$9, PT_R9(sp)
		mtlo	$24
		ld	$24, PT_HI(sp)
		ld	$10, PT_R10(sp)
		ld	$11, PT_R11(sp)
		mthi	$24
		ld	$12, PT_R12(sp)
		ld	$13, PT_R13(sp)
		ld	$14, PT_R14(sp)
		ld	$15, PT_R15(sp)
		ld	$24, PT_R24(sp)
		.endm

		.macro	RESTORE_STATIC
		ld	$16, PT_R16(sp)
		ld	$17, PT_R17(sp)
		ld	$18, PT_R18(sp)
		ld	$19, PT_R19(sp)
		ld	$20, PT_R20(sp)
		ld	$21, PT_R21(sp)
		ld	$22, PT_R22(sp)
		ld	$23, PT_R23(sp)
		ld	$30, PT_R30(sp)
		.endm

		.macro	RESTORE_SOME
		.set	push
		.set	reorder
		mfc0	t0, CP0_STATUS
		.set	pop
		ori	t0, 0x1f
		xori	t0, 0x1f
		mtc0	t0, CP0_STATUS
		li	v1, 0xff00
		and	t0, v1
		ld	v0, PT_STATUS(sp)
		nor	v1, $0, v1
		and	v0, v1
		or	v0, t0
		dmtc0	v0, CP0_STATUS
		ld	v1, PT_EPC(sp)
		dmtc0	v1, CP0_EPC
		ld	$31, PT_R31(sp)
		ld	$28, PT_R28(sp)
		ld	$25, PT_R25(sp)
		ld	$7,  PT_R7(sp)
		ld	$6,  PT_R6(sp)
		ld	$5,  PT_R5(sp)
		ld	$4,  PT_R4(sp)
		ld	$3,  PT_R3(sp)
		ld	$2,  PT_R2(sp)
		.endm

		.macro	RESTORE_ALL
		RESTORE_SOME
		RESTORE_AT
		RESTORE_TEMP
		RESTORE_STATIC
		RESTORE_SP
		.endm

/*
 * Move to kernel mode and disable interrupts.
 * Set cp0 enable bit as sign that we're running on the kernel stack
 */
		.macro	CLI
		mfc0	t0, CP0_STATUS
		li	t1, ST0_CU0|0x1f
		or	t0, t1
		xori	t0, 0x1f
		mtc0	t0, CP0_STATUS
		.endm

/*
 * Move to kernel mode and enable interrupts.
 * Set cp0 enable bit as sign that we're running on the kernel stack
 */
		.macro	STI
		mfc0	t0, CP0_STATUS
		li	t1, ST0_CU0 | 0x1f
		or	t0, t1
		xori	t0, 0x1e
		mtc0	t0, CP0_STATUS
		.endm

/*
 * Just move to kernel mode and leave interrupts as they are.
 * Set cp0 enable bit as sign that we're running on the kernel stack
 */
		.macro	KMODE
		mfc0	t0, CP0_STATUS
		li	t1, ST0_CU0 | 0x1e
		or	t0, t1
		xori	t0, 0x1e
		mtc0	t0, CP0_STATUS
		.endm

#endif /* _LANGUAGE_ASSEMBLY */

#endif /* _ASM_STACKFRAME_H */

[Linux-mips-commits]CVS: linux/arch/mips64/mm tlb-dbg-r4k.c,NONE,1.1 tlb-glue-r4k.S,NONE,1.1 tlbex-r4k.S,NONE,1.1

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips64/mm
In directory usw-pr-cvs1:/tmp/cvs-serv23768/arch/mips64/mm

Added Files:
	tlb-dbg-r4k.c tlb-glue-r4k.S tlbex-r4k.S 
Log Message:
Most of it was a collection of fixes and cleanups for mips64 and SMP stuff

--- NEW FILE: tlb-dbg-r4k.c ---
/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 1999 Ralf Baechle
 * Copyright (C) 1999 Silicon Graphics, Inc.
 *
 * TLB debugging routines.  These perform horribly slow but can easily be
 * modified for debugging purposes.
 */
#include <linux/linkage.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/mm.h>
#include <asm/page.h>
#include <asm/pgtable.h>
#include <asm/ptrace.h>
#include <asm/system.h>

asmlinkage void do_page_fault(struct pt_regs *regs, unsigned long write,
                              unsigned long address);

asmlinkage void tlb_refill_debug(struct pt_regs regs)
{
	show_regs(&regs);
	panic(__FUNCTION__ " called.  This Does Not Happen (TM).");
}

asmlinkage void xtlb_refill_debug(struct pt_regs *regs)
{
	unsigned long addr;
	pgd_t *pgd;
	pmd_t *pmd;
	pte_t *pte;

	addr = regs->cp0_badvaddr & ~((PAGE_SIZE << 1) - 1);
	pgd = pgd_offset(current->active_mm, addr);
	pmd = pmd_offset(pgd, addr);
	pte = pte_offset(pmd, addr);

	set_entrylo0(pte_val(pte[0]) >> 6);
	set_entrylo1(pte_val(pte[1]) >> 6);
	__asm__ __volatile__("nop;nop;nop");

	tlb_write_random();
}

asmlinkage void xtlb_mod_debug(struct pt_regs *regs)
{
	unsigned long addr;

	addr = regs->cp0_badvaddr;
	do_page_fault(regs, 1, addr);
}

asmlinkage void xtlb_tlbl_debug(struct pt_regs *regs)
{
	unsigned long addr;

	addr = regs->cp0_badvaddr;
	do_page_fault(regs, 0, addr);
}

asmlinkage void xtlb_tlbs_debug(struct pt_regs *regs)
{
	unsigned long addr;

	addr = regs->cp0_badvaddr;
	do_page_fault(regs, 1, addr);
}

--- NEW FILE: tlb-glue-r4k.S ---
/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 1999 Ralf Baechle
 * Copyright (C) 1999 Silicon Graphics, Inc.
 */
#define __ASSEMBLY__
#include <linux/init.h>
#include <asm/mipsregs.h>
#include <asm/regdef.h>
#include <asm/stackframe.h>

	.macro	__BUILD_cli
	CLI
	.endm

	.macro	__BUILD_sti
	STI
	.endm

	.macro	tlb_handler name interruptible writebit
	NESTED(__\name, PT_SIZE, sp)
	SAVE_ALL
	dmfc0	a2, CP0_BADVADDR
	__BUILD_\interruptible
	li	a1, \writebit
	sd	a2, PT_BVADDR(sp)
	move	a0, sp
	jal	do_page_fault
	j	ret_from_exception
	END(__\name)
	.endm

	tlb_handler	xtlb_mod sti 1
	tlb_handler	xtlb_tlbl sti 0
	tlb_handler	xtlb_tlbs sti 1

--- NEW FILE: tlbex-r4k.S ---
/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 2000 Silicon Graphics, Inc.
 * Written by Ulf Carlsson (ul...@en...)
 */
#define __ASSEMBLY__
#include <linux/config.h>
#include <linux/init.h>
#include <linux/threads.h>
#include <asm/asm.h>
#include <asm/regdef.h>
#include <asm/mipsregs.h>
#include <asm/pgtable.h>
#include <asm/stackframe.h>

	.data
	.comm	pgd_current, NR_CPUS * 8, 8

	/*
	 * After this macro runs we have a pointer to the pte of the address
	 * that caused the fault in in PTR.
	 */

	.macro	LOAD_PTE2, ptr, tmp
#ifdef CONFIG_SMP
	dmfc0	\tmp, CP0_CONTEXT
	dla	\ptr, pgd_current
	dsrl	\tmp, 23
	daddu	\ptr, \tmp
#else
	dla	\ptr, pgd_current
#endif
	dmfc0	\tmp, CP0_BADVADDR
	ld	\ptr, (\ptr)
	bltz	\tmp, kaddr
	 dsrl	\tmp, (PGDIR_SHIFT-3)		# get pgd offset in bytes
	andi	\tmp, ((PTRS_PER_PGD - 1)<<3)
	daddu	\ptr, \tmp			# add in pgd offset
	dmfc0	\tmp, CP0_BADVADDR
	ld	\ptr, (\ptr)			# get pmd pointer
	dsrl	\tmp, (PMD_SHIFT-3)		# get pmd offset in bytes
	andi	\tmp, ((PTRS_PER_PMD - 1)<<3)
	daddu	\ptr, \tmp			# add in pmd offset
	dmfc0	\tmp, CP0_XCONTEXT
	ld	\ptr, (\ptr)			# get pte pointer
	andi	\tmp, 0xff0			# get pte offset
	daddu	\ptr, \tmp
	.endm

	/*
	 * This places the even/odd pte pair in the page table at the pte
	 * entry pointed to by PTE into ENTRYLO0 and ENTRYLO1.
	 */
	.macro	PTE_RELOAD, pte0, pte1
	dsrl	\pte0, 6			# convert to entrylo0
	dmtc0	\pte0, CP0_ENTRYLO0		# load it
	dsrl	\pte1, 6			# convert to entrylo1
	dmtc0	\pte1, CP0_ENTRYLO1		# load it
	.endm

	.text
	.set	noreorder
	.set	mips3

	__INIT

	.align	5
FEXPORT(except_vec0)
	.set	noat
	PANIC("Unused vector called")
1:	b	1b
	 nop

	/*
	 * TLB refill handler for the R10000.
	 * Attention:  We may only use 32 instructions / 128 bytes.
	 */

	.align	5
LEAF(except_vec1_r10k)
	.set	noat
	LOAD_PTE2 k1 k0
	ld	k0, 0(k1)			# get even pte
	ld	k1, 8(k1)			# get odd pte
	PTE_RELOAD k0 k1
	nop
	tlbwr
	eret
kaddr:
	dla	k0, handle_vmalloc_address	# MAPPED kernel needs this
	jr	k0
	 nop
	END(except_vec1_r10k)

	__FINIT

	.align	5
LEAF(handle_vmalloc_address)
	.set	noat
	/*
	 * First, determine that the address is in/above vmalloc range.
	 */
	dmfc0	k0, CP0_BADVADDR
	dli	k1, VMALLOC_START

	/*
	 * Now find offset into kptbl.
	 */
	dsubu	k0, k0, k1
	dla	k1, kptbl
	dsrl	k0, (PAGE_SHIFT+1)		# get vpn2
	dsll	k0, 4				# byte offset of pte
	daddu	k1, k1, k0

	/*
	 * Determine that fault address is within vmalloc range.
	 */
	dla	k0, ekptbl
	sltu	k0, k1, k0
	beqz	k0, not_vmalloc

	/*
	 * Load cp0 registers.
	 */
	ld	k0, 0(k1)			# get even pte
	ld	k1, 8(k1)			# get odd pte

not_vmalloc:
	PTE_RELOAD k0 k1
	nop
	tlbwr
	eret
	END(handle_vmalloc_address)

[Linux-mips-commits]CVS: linux/arch/mips64/kernel syscall.c,1.2,1.3

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips64/kernel
In directory usw-pr-cvs1:/tmp/cvs-serv23768/arch/mips64/kernel

Added Files:
	syscall.c 
Log Message:
Most of it was a collection of fixes and cleanups for mips64 and SMP stuff

[Linux-mips-commits]CVS: linux/include/asm-mips64 pgtable.h,1.11,1.12 processor.h,1.8,1.9

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/include/asm-mips64
In directory usw-pr-cvs1:/tmp/cvs-serv23204/include/asm-mips64

Modified Files:
	pgtable.h processor.h 
Log Message:
Most of it was a collection of fixes and cleanups for mips64 and SMP stuff

Index: pgtable.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips64/pgtable.h,v
retrieving revision 1.11
retrieving revision 1.12
diff -u -d -r1.11 -r1.12
--- pgtable.h	19 Feb 2002 17:27:39 -0000	1.11
+++ pgtable.h	26 Feb 2002 17:34:15 -0000	1.12
@@ -137,7 +137,7 @@
 #define VMALLOC_START     XKSEG
 #define VMALLOC_VMADDR(x) ((unsigned long)(x))
 #define VMALLOC_END       \
-  (VMALLOC_START + ((1 << KPTBL_PAGE_ORDER) * PTRS_PER_PTE * PAGE_SIZE))
+	(VMALLOC_START + ((1 << KPTBL_PAGE_ORDER) * PTRS_PER_PTE * PAGE_SIZE))
 
 /* Note that we shift the lower 32bits of each EntryLo[01] entry
  * 6 bits to the left. That way we can convert the PFN into the

Index: processor.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips64/processor.h,v
retrieving revision 1.8
retrieving revision 1.9
diff -u -d -r1.8 -r1.9
--- processor.h	2 Dec 2001 19:05:32 -0000	1.8
+++ processor.h	26 Feb 2002 17:34:15 -0000	1.9
@@ -134,7 +134,7 @@
  * is limited to 1TB by the R4000 architecture; R10000 and better can
  * support 16TB.
  */
-#define TASK_SIZE32	   0x80000000UL
+#define TASK_SIZE32	   0x7fff8000UL
 #define TASK_SIZE	0x10000000000UL
 
 /* This decides where the kernel will search for a free chunk of vm

[Linux-mips-commits]CVS: linux/arch/mips64/mm c-sb1.c,1.3,1.4 fault.c,1.10,1.11 pg-sb1.c,1.1,1.2

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips64/mm
In directory usw-pr-cvs1:/tmp/cvs-serv23204/arch/mips64/mm

Modified Files:
	c-sb1.c fault.c pg-sb1.c 
Log Message:
Most of it was a collection of fixes and cleanups for mips64 and SMP stuff

Index: c-sb1.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips64/mm/c-sb1.c,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- c-sb1.c	14 Feb 2002 20:48:25 -0000	1.3
+++ c-sb1.c	26 Feb 2002 17:34:15 -0000	1.4
@@ -56,7 +56,7 @@
 {
 }
 
-static void local_sb1___flush_cache_all(void)
+static inline void local_sb1___flush_dcache_all(void)
 {
 	/*
 	 * Haven't worried too much about speed here; given that we're flushing
@@ -90,7 +90,10 @@
 		"sync                       \n"
 #endif
 		".set pop                   \n");
+}
 
+static inline void local_sb1___flush_icache_all(void)
+{
 	__asm__ __volatile__ (
 		".set push                  \n"
 		".set noreorder             \n"
@@ -107,6 +110,12 @@
 		  "r" (KSEG0), "i" (Index_Invalidate_I));
 }
 
+static void local_sb1___flush_cache_all(void)
+{
+	local_sb1___flush_dcache_all();
+	local_sb1___flush_icache_all();
+}
+
 #ifdef CONFIG_SMP
 extern void sb1___flush_cache_all_ipi(void *ignored);
 asm("sb1___flush_cache_all_ipi = local_sb1___flush_cache_all");
@@ -228,10 +237,17 @@
 /*
  * If there's no context yet, or the page isn't executable, no icache flush
  * is needed
+ *
+ * This is broken.  If there is no context yet we still have to writeback
+ * the d-cache to memory.
  */
-static void sb1_flush_icache_page(struct vm_area_struct *vma, struct page *page)
+static void sb1_flush_icache_page(struct vm_area_struct *vma,
+	struct page *page)
 {
-	if ((vma->vm_mm->context == 0) || !(vma->vm_flags & VM_EXEC)) {
+	unsigned int cpu = smp_processor_id();
+
+	if (!(vma->vm_flags & VM_EXEC)) {
+//		printk("sb1_flush_icache_page(): not exec\n");
 		return;
 	}
 
@@ -239,7 +255,10 @@
 	 * We're not sure of the virtual address(es) involved here, so
 	 * conservatively flush the entire caches on all processors
 	 * (ouch).
+	 *
+	 * Bumping the ASID may well be cheaper, need to experiment ...
 	 */
+//printk("sb1_flush_icache_page(): flushing exec page\n");
 	sb1___flush_cache_all();
 }
 
@@ -252,11 +271,10 @@
 		"1:  cache %1, (%0)           \n"
 		"2:  .set pop                 \n"
 		"    .section __ex_table,\"a\"\n"
-		"     .word  1b, 2b          \n"
+		"     .dword  1b, 2b          \n"
 		"     .previous"
 		:
-		: "r" (addr),
-		  "i" (Hit_Invalidate_I));
+		: "r" (addr), "i" (Hit_Invalidate_I));
 }
 
 static inline void protected_writeback_dcache_line(unsigned long addr)
@@ -273,12 +291,15 @@
 		"    .set push                \n"
 		"    .set noreorder           \n"
 		"    .set mips4               \n"
-		"1:                           \n"
+		"                             \n"
 #ifdef CONFIG_SB1_PASS_1_WORKAROUNDS
-		"     lw    $0,   (%0)        \n"
-		"     sync                  \n"
+		"1:   lw    $0,   (%0)        \n"
+		"     sync                    \n"
+		"     .section __ex_table,\"a\"\n"
+		"     .dword  1b, 3f           \n"
+		"     .previous               \n"
 #endif
-		"     cache  %1, 0(%0)    \n" /* Hit-WB{-inval} this address */
+		"2:   cache  %1, 0(%0)    \n" /* Hit-WB{-inval} this address */
 		/* XXX: should be able to do this after both dcache cache
 		   ops, but there's no guarantee that this will be inlined,
 		   and the pass1 restriction checker can't detect syncs
@@ -288,9 +309,9 @@
 #ifdef CONFIG_SB1_PASS_1_WORKAROUNDS		/* Bug 1384 */
 		"     sync                    \n"
 #endif
-		"2:  .set pop                 \n"
+		"3:  .set pop                 \n"
 		"    .section __ex_table,\"a\"\n"
-		"     .word  1b, 2b          \n"
+		"     .dword  2b, 3b          \n"
 		"     .previous"
 		:
 		: "r" (addr),
@@ -305,15 +326,10 @@
 #endif
 }
 
-/*
- * XXX - Still need to really understand this.  This is mostly just
- * derived from the r10k and r4k implementations, and seems to work
- * but things that "seem to work" when I don't understand *why* they
- * "seem to work" disturb me greatly...JDC
- */
 static void local_sb1_flush_cache_sigtramp(unsigned long addr)
 {
 	unsigned long daddr, iaddr;
+
 	
 	daddr = addr & ~(dcache_line_size - 1);
 	protected_writeback_dcache_line(daddr);

Index: fault.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips64/mm/fault.c,v
retrieving revision 1.10
retrieving revision 1.11
diff -u -d -r1.10 -r1.11
--- fault.c	19 Feb 2002 17:51:29 -0000	1.10
+++ fault.c	26 Feb 2002 17:34:15 -0000	1.11
@@ -196,6 +196,7 @@
 		       address,
 		       (unsigned long) regs->cp0_epc,
 		       (unsigned long) regs->regs[31]);
+while(1);
 #endif
 		info.si_signo = SIGSEGV;
 		info.si_errno = 0;

Index: pg-sb1.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips64/mm/pg-sb1.c,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- pg-sb1.c	28 Jan 2002 20:31:57 -0000	1.1
+++ pg-sb1.c	26 Feb 2002 17:34:15 -0000	1.2
@@ -34,13 +34,15 @@
 /* These are the functions hooked by the memory management function pointers */
 void sb1_clear_page(void *page)
 {
-	/* JDCXXX - This should be bottlenecked by the write buffer, but these
-	   things tend to be mildly unpredictable...should check this on the
-	   performance model */
-
-	/* We prefetch 4 lines ahead.  We're also "cheating" slightly here...
-	   since we know we're on an SB1, we force the assembler to take 
-	   64-bit operands to speed things up */
+	/*
+	 * JDCXXX - This should be bottlenecked by the write buffer, but these
+	 * things tend to be mildly unpredictable...should check this on the
+	 * performance model
+	 *
+	 * We prefetch 4 lines ahead.  We're also "cheating" slightly here...
+	 * since we know we're on an SB1, we force the assembler to take 
+	 * 64-bit operands to speed things up
+	 */
 	__asm__ __volatile__(
 		".set push                  \n"
 		".set noreorder             \n"
@@ -57,24 +59,22 @@
 		"     sd        $0, 24(%0)  \n"
 		"     pref       " SB1_PREF_STORE_STREAMED_HINT ",128(%0)  \n"  /* Prefetch 4 lines ahead     */
 		"     bne       $1, %0, 1b  \n"
-		"     daddiu     %0, %0, 32  \n"  /* Next cacheline (This instruction better be short piped!) */
+		"      daddiu     %0, %0, 32\n"  /* Next cacheline (This instruction better be short piped!) */
 		".set pop                   \n"
-		:"=r" (page)
-		:"0" (page),
-		 "I" (PAGE_SIZE-32)
-		:"$1","memory");
+		: "=r" (page)
+		: "0" (page), "I" (PAGE_SIZE-32)
+		: "memory");
 
 }
 
 void sb1_copy_page(void *to, void *from)
 {
-
-	/* This should be optimized in assembly...can't use ld/sd, though,
+	/*
+	 * This should be optimized in assembly...can't use ld/sd, though,
 	 * because the top 32 bits could be nuked if we took an interrupt
 	 * during the routine.	And this is not a good place to be cli()'ing 
-	 */
-
-	/* The pref's used here are using "streaming" hints, which cause the
+	 *
+	 * The pref's used here are using "streaming" hints, which cause the
 	 * copied data to be kicked out of the cache sooner.  A page copy often
 	 * ends up copying a lot more data than is commonly used, so this seems
 	 * to make sense in terms of reducing cache pollution, but I've no real
@@ -117,19 +117,7 @@
 		"     bne       $1, %0, 1b  \n"
 		"     daddiu     %0, %0, 32  \n"  /* Next cacheline */
 		".set pop                   \n" 
-		:"=r" (to),
-		"=r" (from)
-		:
-		"0" (from),
-		"1" (to),
-		"I" (PAGE_SIZE-32)
-		:"$1","$2","$3","$4","$5","$6","$7","$8","$9","memory");
-/*
-	unsigned long *src = from;
-	unsigned long *dest = to;
-	unsigned long *target = (unsigned long *) (((unsigned long)src) + PAGE_SIZE);
-	while (src != target) {
-		*dest++ = *src++;
-	}
-*/
+		: "=r" (to), "=r" (from)
+		: "0" (from), "1" (to), "I" (PAGE_SIZE-32)
+		: "$2","$3","$4","$5","$6","$7","$8","$9","memory");
 }

[Linux-mips-commits]CVS: linux/arch/mips/lib dump_tlb.c,1.4,1.5

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips/lib
In directory usw-pr-cvs1:/tmp/cvs-serv23204/arch/mips/lib

Modified Files:
	dump_tlb.c 
Log Message:
Most of it was a collection of fixes and cleanups for mips64 and SMP stuff

Index: dump_tlb.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/lib/dump_tlb.c,v
retrieving revision 1.4
retrieving revision 1.5
diff -u -d -r1.4 -r1.5
--- dump_tlb.c	15 Jan 2002 00:34:07 -0000	1.4
+++ dump_tlb.c	26 Feb 2002 17:34:15 -0000	1.5
@@ -4,29 +4,47 @@
  * Copyright (C) 1994, 1995 by Waldorf Electronics, written by Ralf Baechle.
  * Copyright (C) 1999 by Silicon Graphics, Inc.
  */
+#include <linux/config.h>
 #include <linux/kernel.h>
 #include <linux/mm.h>
 #include <linux/sched.h>
 #include <linux/string.h>
 
 #include <asm/bootinfo.h>
-#include <asm/cachectl.h>
 #include <asm/cpu.h>
+#include <asm/cachectl.h>
 #include <asm/mipsregs.h>
 #include <asm/page.h>
 #include <asm/pgtable.h>
 
-void
-dump_tlb(int first, int last)
+static inline const char *msg2str(unsigned int mask)
+{
+	switch (mask) {
+	case PM_4K:	return "4kb";
+	case PM_16K:	return "16kb";
+	case PM_64K:	return "64kb";
+	case PM_256K:	return "256kb";
+#ifndef CONFIG_CPU_VR41XX
+	case PM_1M:	return "1Mb";
+	case PM_4M:	return "4Mb";
+	case PM_16M:	return "16Mb";
+	case PM_64M:	return "64Mb";
+	case PM_256M:	return "256Mb";
+#endif
+	}
+}
+
+void dump_tlb(int first, int last)
 {
 	int	i;
 	unsigned int pagemask, c0, c1, asid;
-	unsigned long entryhi, entrylo0, entrylo1;
+	unsigned long long entrylo0, entrylo1;
+	unsigned long entryhi;
 
 	asid = get_entryhi() & 0xff;
 
-	for(i=first;i<=last;i++)
-	{
+	printk("\n");
+	for(i=first;i<=last;i++) {
 		write_32bit_cp0_register(CP0_INDEX, i);
 		__asm__ __volatile__(
 			".set\tmips3\n\t"
@@ -38,53 +56,50 @@
 			".set\tmips0\n\t");
 		pagemask = read_32bit_cp0_register(CP0_PAGEMASK);
 		entryhi  = read_32bit_cp0_register(CP0_ENTRYHI);
-		entrylo0 = read_32bit_cp0_register(CP0_ENTRYLO0);
-		entrylo1 = read_32bit_cp0_register(CP0_ENTRYLO1);
+		entrylo0 = get_entrylo0();
+		entrylo1 = get_entrylo1();
 
-		/* Unused entries have a virtual address of KSEG0.  */
-		if ((entryhi & 0xffffe000) != 0x80000000
+		/* Unused entries have a virtual address in KSEG0.  */
+		if ((entryhi & 0xf0000000) != 0x80000000
 		    && (entryhi & 0xff) == asid) {
 			/*
 			 * Only print entries in use
 			 */
-			printk("Index: %2d pgmask=%08x ", i, pagemask);
+			printk("Index: %2d pgmask=%s ", i, msg2str(pagemask));
 
 			c0 = (entrylo0 >> 3) & 7;
 			c1 = (entrylo1 >> 3) & 7;
 
-			printk("va=%08lx asid=%08lx"
-			       "  [pa=%06lx c=%d d=%d v=%d g=%ld]"
-			       "  [pa=%06lx c=%d d=%d v=%d g=%ld]\n",
-			       (entryhi & 0xffffe000),
-			       entryhi & 0xff,
-			       entrylo0 & PAGE_MASK, c0,
+			printk("va=%08lx asid=%02lx\n",
+			       (entryhi & 0xffffe000), (entryhi & 0xff));
+			printk("\t\t\t[pa=%08Lx c=%d d=%d v=%d g=%Ld]\n",
+			       (entrylo0 << 6) & PAGE_MASK, c0,
 			       (entrylo0 & 4) ? 1 : 0,
 			       (entrylo0 & 2) ? 1 : 0,
-			       (entrylo0 & 1),
-			       entrylo1 & PAGE_MASK, c1,
+			       (entrylo0 & 1));
+			printk("\t\t\t[pa=%08Lx c=%d d=%d v=%d g=%Ld]\n",
+			       (entrylo1 << 6) & PAGE_MASK, c1,
 			       (entrylo1 & 4) ? 1 : 0,
 			       (entrylo1 & 2) ? 1 : 0,
 			       (entrylo1 & 1));
-			       
+			printk("\n");
 		}
 	}
 
 	set_entryhi(asid);
 }
 
-void
-dump_tlb_all(void)
+void dump_tlb_all(void)
 {
 	dump_tlb(0, mips_cpu.tlbsize - 1);
 }
 
-void
-dump_tlb_wired(void)
+void dump_tlb_wired(void)
 {
 	int	wired;
 
 	wired = read_32bit_cp0_register(CP0_WIRED);
-	printk("Num wired entries: %d\n", wired);
+	printk("Wired: %d", wired);
 	dump_tlb(0, read_32bit_cp0_register(CP0_WIRED));
 }
 
@@ -138,12 +153,20 @@
 	addr = (unsigned int) address;
 
 	printk("Addr                 == %08x\n", addr);
-	printk("tasks->mm.pgd        == %08x\n", (unsigned int) t->mm->pgd);
+	printk("task                 == %08p\n", t);
+	printk("task->mm             == %08p\n", t->mm);
+	//printk("tasks->mm.pgd        == %08x\n", (unsigned int) t->mm->pgd);
 
-	page_dir = pgd_offset(t->mm, 0);
+	if (addr > KSEG0)
+		page_dir = pgd_offset_k(0);
+	else
+		page_dir = pgd_offset(t->mm, 0);
 	printk("page_dir == %08x\n", (unsigned int) page_dir);
 
-	pgd = pgd_offset(t->mm, addr);
+	if (addr > KSEG0)
+		pgd = pgd_offset_k(addr);
+	else
+		pgd = pgd_offset(t->mm, addr);
 	printk("pgd == %08x, ", (unsigned int) pgd);
 
 	pmd = pmd_offset(pgd, addr);
@@ -153,7 +176,11 @@
 	printk("pte == %08x, ", (unsigned int) pte);
 
 	page = *pte;
-	printk("page == %08x\n", (unsigned int) pte_val(page));
+#ifdef CONFIG_64BIT_PHYS_ADDR
+	printk("page == %08Lx\n", (unsigned long long) pte_val(page));
+#else
+	printk("page == %08lx\n", (unsigned int) pte_val(page));
+#endif
 
 	val = pte_val(page);
 	if (val & _PAGE_PRESENT) printk("present ");
@@ -196,9 +223,11 @@
 {
 	int i;
 
-	for (i=0;i<8;i++) {
-		printk("*%08lx == %08lx, ", (unsigned long)p, p[0]);
-		printk("*%08lx == %08lx\n", (unsigned long)p, p[1]);
-		p += 2;
+	for(i=0;i<8;i++)
+	{
+		printk("*%08lx == %08lx, ",
+		       (unsigned long)p, (unsigned long)*p++);
+		printk("*%08lx == %08lx\n",
+		       (unsigned long)p, (unsigned long)*p++);
 	}
 }

[Linux-mips-commits]CVS: linux/arch/mips64/sgi-ip27 ip27-init.c,1.7,1.8

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips64/sgi-ip27
In directory usw-pr-cvs1:/tmp/cvs-serv23204/arch/mips64/sgi-ip27

Modified Files:
	ip27-init.c 
Log Message:
Most of it was a collection of fixes and cleanups for mips64 and SMP stuff

Index: ip27-init.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips64/sgi-ip27/ip27-init.c,v
retrieving revision 1.7
retrieving revision 1.8
diff -u -d -r1.7 -r1.8
--- ip27-init.c	28 Jan 2002 20:31:57 -0000	1.7
+++ ip27-init.c	26 Feb 2002 17:34:15 -0000	1.8
@@ -360,7 +360,6 @@
 	int cpu = smp_processor_id();
 	cnodeid_t cnode = get_compact_nodeid();
 
-	current_cpu_data.asid_cache = ASID_FIRST_VERSION;
 	TLBMISS_HANDLER_SETUP();
 #if 0
 	intr_init();
@@ -423,10 +422,11 @@
 
 static volatile cpumask_t boot_barrier;
 
-void cboot(void)
+void __init start_secondary(void)
 {
 	CPUMASK_CLRB(boot_barrier, getcpuid());	/* needs atomicity */
 	per_cpu_init();
+	per_cpu_trap_init();
 #if 0
 	ecc_init();
 	bte_lateinit();
@@ -443,7 +443,7 @@
 	int		num_cpus = 0;
 	cpuid_t		cpu, mycpuid = getcpuid();
 	cnodeid_t	cnode;
-	extern void	bootstrap(void);
+	extern void	smp_bootstrap(void);
 
 	sn_mp_setup();
 	/* Master has already done per_cpu_init() */
@@ -485,16 +485,16 @@
 			/* Attach to the address space of init_task. */
 			atomic_inc(&init_mm.mm_count);
 			p->active_mm = &init_mm;
-			
+
 			/*
-		 	 * Launch a slave into bootstrap().
+		 	 * Launch a slave into smp_bootstrap().
 		 	 * It doesn't take an argument, and we
 			 * set sp to the kernel stack of the newly 
 			 * created idle process, gp to the proc struct
 			 * (so that current-> works).
 		 	 */
 			LAUNCH_SLAVE(cputonasid(num_cpus),cputoslice(num_cpus), 
-				(launch_proc_t)MAPPED_KERN_RW_TO_K0(bootstrap),
+				(launch_proc_t)MAPPED_KERN_RW_TO_K0(smp_bootstrap),
 				0, (void *)((unsigned long)p + 
 				KERNEL_STACK_SIZE - 32), (void *)p);
 
@@ -550,7 +550,10 @@
 }
 
 #else /* CONFIG_SMP */
-void cboot(void) {}
+void __init start_secondary(void)
+{
+	/* XXX Why do we need this empty definition at all?  */
+}
 #endif /* CONFIG_SMP */
 
 

[Linux-mips-commits]CVS: linux/arch/mips64/kernel head.S,1.4,1.5 r4k_switch.S,1.1,1.2 scall_o32.S,1.11,1.12 smp.c,1.14,1.15 traps.c,1.13,1.14 unaligned.c,1.4,1.5

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips64/kernel
In directory usw-pr-cvs1:/tmp/cvs-serv23204/arch/mips64/kernel

Modified Files:
	head.S r4k_switch.S scall_o32.S smp.c traps.c unaligned.c 
Log Message:
Most of it was a collection of fixes and cleanups for mips64 and SMP stuff

Index: head.S
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips64/kernel/head.S,v
retrieving revision 1.4
retrieving revision 1.5
diff -u -d -r1.4 -r1.5
--- head.S	19 Feb 2002 17:50:59 -0000	1.4
+++ head.S	26 Feb 2002 17:34:15 -0000	1.5
@@ -35,13 +35,13 @@
 
 #ifdef CONFIG_SGI_IP27
 	/*
-	 * outputs the local nasid into t1.
+	 * outputs the local nasid into res.  IP27 stuff.
 	 */
-	.macro GET_NASID_ASM
-	dli	t1, LOCAL_HUB_ADDR(NI_STATUS_REV_ID)
-	ld	t1, (t1)
-	and	t1, NSRI_NODEID_MASK
-	dsrl	t1, NSRI_NODEID_SHFT
+	.macro GET_NASID_ASM res
+	dli	\res, LOCAL_HUB_ADDR(NI_STATUS_REV_ID)
+	ld	\res, (\res)
+	and	\res, NSRI_NODEID_MASK
+	dsrl	\res, NSRI_NODEID_SHFT
 	.endm
 #endif /* CONFIG_SGI_IP27 */
 
@@ -97,7 +97,7 @@
 	xori	sp, 0xf
 
 #ifdef CONFIG_SGI_IP27
-	GET_NASID_ASM
+	GET_NASID_ASM	t1
 	move	t2, t1				# text and data are here
 	MAPPED_KERNEL_SETUP_TLB
 #endif /* IP27 */
@@ -107,25 +107,24 @@
 	CLI					# disable interrupts
 
 	la	$28, init_task_union		# init current pointer
-	daddiu	t0, $28, KERNEL_STACK_SIZE-32
-	sd	t0, kernelsp
-	dsubu	sp, t0, 4*SZREG			# init stack pointer
-	move	t0, $28
+	daddiu	sp, $28, KERNEL_STACK_SIZE-32
+	set_saved_sp	sp, t0
 
-#ifdef CONFIG_SMP
-	mtc0	t0, CP0_WATCHLO
-	dsrl32	t0, t0, 0
-	mtc0	t0, CP0_WATCHHI
-#endif
+	dsubu	sp, 4*SZREG			# init stack pointer
 
-	jal	init_arch
+	j	init_arch
 	END(kernel_entry)
 
 #ifdef CONFIG_SMP
+/*
+ * SMP slave cpus entry point.  Board specific code for bootstrap calls this
+ * function after setting up the stack and gp registers. 
+ */
+NESTED(smp_bootstrap, 16, sp)
 #ifdef CONFIG_SGI_IP27
-NESTED(bootstrap, 16, sp)
-	GET_NASID_ASM
-	li	t0, KLDIR_OFFSET + (KLI_KERN_VARS * KLDIR_ENT_SIZE) + KLDIR_OFF_POINTER + K0BASE
+	GET_NASID_ASM	t1
+	li	t0, KLDIR_OFFSET + (KLI_KERN_VARS * KLDIR_ENT_SIZE) + \
+		    KLDIR_OFF_POINTER + K0BASE
 	dsll	t1, NASID_SHFT
 	or	t0, t0, t1
 	ld	t0, 0(t0)			# t0 points to kern_vars struct
@@ -133,40 +132,29 @@
 	lh	t2, KV_RW_NASID_OFFSET(t0)
 	MAPPED_KERNEL_SETUP_TLB
 	ARC64_TWIDDLE_PC
-	CLI
-	mfc0	t0, CP0_STATUS
-	li	t1, ~(ST0_CU1|ST0_CU2|ST0_CU3)
-	and	t0, t1
-	or	t0, (ST0_CU0|ST0_KX|ST0_SX|ST0_FR) # Bogosity: cu0 indicates kernel
-	mtc0	t0, CP0_STATUS			   # thread in copy_thread.
-	jal	cboot
-	END(bootstrap)
-#else
-
-/*
- * SMP slave cpus entry point.  Board specific code for bootstrap calls this
- * function after setting up the stack and gp registers. 
- */
-	LEAF(smp_bootstrap)
-	.set push
-	.set noreorder
+#endif /* CONFIG_SGI_IP27 */
 
-	mtc0	zero, CP0_WIRED
 	CLI
-	mfc0	t0, CP0_STATUS
-	li	t1, ~(ST0_CU1|ST0_CU2|ST0_CU3|ST0_BEV)
-	and	t0, t1
-	or	t0, (ST0_CU0|ST0_FR|ST0_KX|ST0_SX);
-	jal	start_secondary
+
+	/*
+	 * For the moment set ST0_KU so the CPU will not spit fire when
+	 * executing 64-bit instructions.  The full initialization of the
+	 * CPU's status register is done later in per_cpu_trap_init().
+	 */
+        mfc0	t0, CP0_STATUS
+        or	t0, ST0_KX
 	mtc0	t0, CP0_STATUS
-	.set pop
+
+	set_saved_sp	sp, t0
+
+	jal	start_secondary			# XXX: IP27: cboot
+
 	END(smp_bootstrap)
-#endif /* CONFIG_SGI_IP27 */
 #endif /* CONFIG_SMP */
 
 	__FINIT
 
-	.comm	kernelsp, 8, 8			# current stackpointer
+	declare_saved_sp
 
 #undef PAGE_SIZE
 #define PAGE_SIZE	0x1000

Index: r4k_switch.S
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips64/kernel/r4k_switch.S,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- r4k_switch.S	12 Dec 2001 18:33:06 -0000	1.1
+++ r4k_switch.S	26 Feb 2002 17:34:15 -0000	1.2
@@ -42,14 +42,10 @@
 	 */
 	move	$28, a1
 	cpu_restore_nonscratch $28
-#ifndef CONFIG_SMP
-	daddiu	t0, $28, KERNEL_STACK_SIZE-32
-	sd	t0, kernelsp
-#else
-	mtc0	a1, CP0_WATCHLO
-	dsrl32	a1, a1, 0
-	mtc0	a1, CP0_WATCHHI
-#endif
+
+	daddiu	a1, $28, KERNEL_STACK_SIZE-32
+	set_saved_sp	a1 t0
+
 	mfc0	t1, CP0_STATUS		/* Do we really need this? */
 	li	a3, 0xff00
 	and	t1, a3

Index: scall_o32.S
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips64/kernel/scall_o32.S,v
retrieving revision 1.11
retrieving revision 1.12
diff -u -d -r1.11 -r1.12
--- scall_o32.S	2 Jan 2002 19:13:41 -0000	1.11
+++ scall_o32.S	26 Feb 2002 17:34:15 -0000	1.12
@@ -43,6 +43,12 @@
 	daddiu	t1, 4			# skip to next instruction
 	beqz	t0, not_o32_scall
 	sd	t1, PT_EPC(sp)
+#if 0
+ SAVE_ALL
+ move a1, v0
+ PRINT("Scall %ld\n")
+ RESTORE_ALL
+#endif
 
 	/* XXX Put both in one cacheline, should save a bit. */
 	dsll	t0, v0, 3		# offset into table
@@ -464,6 +470,19 @@
 	sys	sys_ni_syscall	0
 	sys	sys_gettid	0
 	sys	sys32_readahead	5
+	sys	sys_ni_syscall	0		/* reserved for setxattr */
+	sys	sys_ni_syscall	0		/* 4225 res. for lsetxattr */
+	sys	sys_ni_syscall	0		/* reserved for fsetxattr */
+	sys	sys_ni_syscall	0		/* reserved for getxattr */
+	sys	sys_ni_syscall	0		/* reserved for lgetxattr */
+	sys	sys_ni_syscall	0		/* reserved for fgetxattr */
+	sys	sys_ni_syscall	0		/* 4230 res. for listxattr */
+	sys	sys_ni_syscall	0		/* reserved for llistxattr */
+	sys	sys_ni_syscall	0		/* reserved for flistxattr */
+	sys	sys_ni_syscall	0		/* reserved for removexattr */
+	sys	sys_ni_syscall	0		/* reserved for lremovexattr */
+	sys	sys_ni_syscall	0		/* 4235 res. for fremovexattr */
+
 	.endm
 
 	.macro	sys function, nargs

Index: smp.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips64/kernel/smp.c,v
retrieving revision 1.14
retrieving revision 1.15
diff -u -d -r1.14 -r1.15
--- smp.c	19 Feb 2002 17:54:59 -0000	1.14
+++ smp.c	26 Feb 2002 17:34:15 -0000	1.15
@@ -56,6 +56,7 @@
 #endif
 }
 
+#ifndef CONFIG_SGI_IP27
 /*
  * Hook for doing final board-specific setup after the generic smp setup
  * is done
@@ -65,27 +66,21 @@
 	unsigned int cpu = smp_processor_id();
 
 	prom_init_secondary();
-
-	/* Do stuff that trap_init() did for the first processor */
-	clear_cp0_status(ST0_BEV);
-	if (mips_cpu.options & MIPS_CPU_DIVEC) {
-		set_cp0_cause(CAUSEF_IV);
-	}
+	per_cpu_trap_init();
 
 	/*
 	 * XXX parity protection should be folded in here when it's converted
 	 * to an option instead of something based on .cputype
 	 */
-	set_context(cpu << 23);
 	pgd_current[cpu] = init_mm.pgd;
 	cpu_data[cpu].udelay_val = loops_per_jiffy;
-	cpu_data[cpu].asid_cache = ASID_FIRST_VERSION;
 	prom_smp_finish();
 	printk("Slave cpu booted successfully\n");
 	CPUMASK_SETB(cpu_online_map, cpu);
 	atomic_inc(&cpus_booted);
 	cpu_idle();
 }
+#endif /* CONFIG_SGI_IP27 */
 
 void __init smp_commence(void)
 {

Index: traps.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips64/kernel/traps.c,v
retrieving revision 1.13
retrieving revision 1.14
diff -u -d -r1.13 -r1.14
--- traps.c	19 Feb 2002 17:43:02 -0000	1.13
+++ traps.c	26 Feb 2002 17:34:15 -0000	1.14
@@ -597,13 +597,24 @@
 	}
 }
 
-static inline void go_64(void)
+void __init per_cpu_trap_init(void)
 {
-	unsigned int bits;
+	unsigned int cpu = smp_processor_id();
 
-	bits = ST0_KX|ST0_SX|ST0_UX;
-	set_cp0_status(bits);
-	printk("Entering 64-bit mode.\n");
+	/* Some firmware leaves the BEV flag set, clear it.  */
+	clear_cp0_status(ST0_CU1|ST0_CU2|ST0_CU3|ST0_BEV);
+	set_cp0_status(ST0_CU0|ST0_FR|ST0_KX|ST0_SX|ST0_UX);
+
+	/*
+	 * Some MIPS CPUs have a dedicated interrupt vector which reduces the
+	 * interrupt processing overhead.  Use it where available.
+	 */
+	if (mips_cpu.options & MIPS_CPU_DIVEC)
+		set_cp0_cause(CAUSEF_IV);
+
+	cpu_data[cpu].asid_cache = ASID_FIRST_VERSION;
+	set_context(cpu << 23);
+	set_wired(0);
 }
 
 void __init trap_init(void)
@@ -617,10 +628,9 @@
 	unsigned long i;
 	int dummy;
 
-	/* Some firmware leaves the BEV flag set, clear it.  */
-	clear_cp0_status(ST0_BEV);
+	per_cpu_trap_init();
 
-	/* Copy the generic exception handler code to it's final destination. */
+	/* Copy the generic exception handlers to their final destination. */
 	memcpy((void *)(KSEG0 + 0x100), &except_vec2_generic, 0x80);
 	memcpy((void *)(KSEG0 + 0x180), &except_vec3_generic, 0x80);
 
@@ -640,12 +650,7 @@
 	 * Some MIPS CPUs have a dedicated interrupt vector which reduces the
 	 * interrupt processing overhead.  Use it where available.
 	 */
-	if (mips_cpu.options & MIPS_CPU_DIVEC) {
-		memcpy((void *)(KSEG0 + 0x200), &except_vec4, 8);
-		set_cp0_cause(CAUSEF_IV);
-	}
-
-	go_64();		/* In memoriam C128 ;-)  */
+	memcpy((void *)(KSEG0 + 0x200), &except_vec4, 8);
 
 	if (mips_cpu.options & MIPS_CPU_MCHECK)
 		set_except_vector(24, handle_mcheck);

Index: unaligned.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips64/kernel/unaligned.c,v
retrieving revision 1.4
retrieving revision 1.5
diff -u -d -r1.4 -r1.5
--- unaligned.c	2 Jan 2002 19:12:17 -0000	1.4
+++ unaligned.c	26 Feb 2002 17:34:15 -0000	1.5
@@ -361,15 +361,15 @@
 		return 1;
 	}
 
-	die_if_kernel("Unhandled kernel unaligned access", regs);
+	die_if_kernel ("Unhandled kernel unaligned access", regs);
 	send_sig(SIGSEGV, current, 1);
 	return 0;
 sigbus:
-	die_if_kernel("Unhandled kernel unaligned access", regs);
+	die_if_kernel ("Unhandled kernel unaligned access", regs);
 	send_sig(SIGBUS, current, 1);
 	return 0;
 sigill:
-	die_if_kernel("Unhandled kernel unaligned access or invalid instruction", regs);
+	die_if_kernel ("Unhandled kernel unaligned access or invalid instruction", regs);
 	send_sig(SIGILL, current, 1);
 	return 0;
 }
@@ -381,6 +381,10 @@
 asmlinkage void do_ade(struct pt_regs *regs)
 {
 	unsigned long pc;
+#if 0
+        printk("ade: Cpu%d[%s:%d:%0lx:%0lx]\n", smp_processor_id(),
+                current->comm, current->pid, regs->cp0_badvaddr, regs->cp0_epc);
+#endif
 
 	/*
 	 * Did we catch a fault trying to load an instruction?

[Linux-mips-commits]CVS: linux/arch/mips/kernel head.S,1.12,1.13 smp.c,1.14,1.15 traps.c,1.30,1.31

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips/kernel
In directory usw-pr-cvs1:/tmp/cvs-serv23204/arch/mips/kernel

Modified Files:
	head.S smp.c traps.c 
Log Message:
Most of it was a collection of fixes and cleanups for mips64 and SMP stuff

Index: head.S
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/kernel/head.S,v
retrieving revision 1.12
retrieving revision 1.13
diff -u -d -r1.12 -r1.13
--- head.S	4 Jan 2002 18:04:53 -0000	1.12
+++ head.S	26 Feb 2002 17:34:14 -0000	1.13
@@ -21,6 +21,7 @@
 #include <asm/asm.h>
 #include <asm/current.h>
 #include <asm/offset.h>
+#include <asm/pgtable.h>
 #include <asm/processor.h>
 #include <asm/regdef.h>
 #include <asm/cachectl.h>
@@ -153,9 +154,9 @@
 		mtc0	zero, CP0_WIRED
 		CLI
 		mfc0	t0, CP0_STATUS
-		li	t1, ~(ST0_CU1|ST0_CU2|ST0_CU3|ST0_BEV); 
+		li	t1, ~(ST0_CU1|ST0_CU2|ST0_CU3|ST0_KX|ST0_SX)
 		and	t0, t1
-		or	t0, (ST0_CU0|ST0_KX|ST0_SX|ST0_FR);
+		or	t0, (ST0_CU0|ST0_FR);
 		jal	start_secondary
 		mtc0	t0, CP0_STATUS
 		.set pop
@@ -167,28 +168,20 @@
 		.comm	kernelsp,    NR_CPUS * 8, 8
 		.comm	pgd_current, NR_CPUS * 8, 8
 
-		.text
-		.org	0x1000
-EXPORT(swapper_pg_dir)
-
-		.org	0x2000
-EXPORT(empty_bad_page)
-
-		.org	0x3000
-EXPORT(empty_bad_page_table)
+#undef PAGE_SIZE
+#define PAGE_SIZE	0x1000
 
-		.org	0x4000
-EXPORT(invalid_pte_table)
+	.macro	page name, order=0
+	.globl	\name
+\name:	.size	\name, (PAGE_SIZE << \order)
+	.org	. + (PAGE_SIZE << \order)
+	.type	\name, @object
+	.endm
 
-		.org	0x5000
-/*
- * Odd MIPS as behaviour but no bug - this label is required to keep as from
- * trying to be too clever ...
- */
-dummy:
+	.data
+	.align	12
 
-/*
- * Align to 8kb boundary for init_task_union which follows in the
- * .text segment.
- */
-		.align	13
+	page	swapper_pg_dir, PGD_ORDER
+	page	empty_bad_page, 0
+	page	empty_bad_page_table, 0
+	page	invalid_pte_table, 0

Index: smp.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/kernel/smp.c,v
retrieving revision 1.14
retrieving revision 1.15
diff -u -d -r1.14 -r1.15
--- smp.c	19 Feb 2002 17:57:11 -0000	1.14
+++ smp.c	26 Feb 2002 17:34:14 -0000	1.15
@@ -88,19 +88,15 @@
 	unsigned int cpu = smp_processor_id();
 
 	prom_init_secondary();
+	per_cpu_trap_init();
 
-	/* Do stuff that trap_init() did for the first processor */
-	clear_cp0_status(ST0_BEV);
-	if (mips_cpu.options & MIPS_CPU_DIVEC) {
-		set_cp0_cause(CAUSEF_IV);
-	}
-	/* XXX parity protection should be folded in here when it's converted to
-	   an option instead of something based on .cputype */
+	/*
+	 * XXX parity protection should be folded in here when it's converted
+	 * to an option instead of something based on .cputype
+	 */
 
-	set_context(cpu << 23);
 	pgd_current[cpu] = init_mm.pgd;
 	cpu_data[cpu].udelay_val = loops_per_jiffy;
-	cpu_data[cpu].asid_cache = ASID_FIRST_VERSION;
 	prom_smp_finish();
 	printk("Slave cpu booted successfully\n");
 	CPUMASK_SETB(cpu_online_map, cpu);

Index: traps.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/kernel/traps.c,v
retrieving revision 1.30
retrieving revision 1.31
diff -u -d -r1.30 -r1.31
--- traps.c	28 Jan 2002 19:23:57 -0000	1.30
+++ traps.c	26 Feb 2002 17:34:14 -0000	1.31
@@ -826,6 +826,24 @@
 extern asmlinkage int fpu_emulator_save_context(struct sigcontext *sc);
 extern asmlinkage int fpu_emulator_restore_context(struct sigcontext *sc);
 
+void __init per_cpu_trap_init(void)
+{
+	unsigned int cpu = smp_processor_id();
+
+	/* Some firmware leaves the BEV flag set, clear it.  */
+	clear_cp0_status(ST0_BEV);
+
+	/*
+	 * Some MIPS CPUs have a dedicated interrupt vector which reduces the
+	 * interrupt processing overhead.  Use it where available.
+	 */
+	if (mips_cpu.options & MIPS_CPU_DIVEC)
+		set_cp0_cause(CAUSEF_IV);
+
+	cpu_data[cpu].asid_cache = ASID_FIRST_VERSION;
+	set_context(cpu << 23);
+}
+
 void __init trap_init(void)
 {
 	extern char except_vec1_generic, except_vec2_generic;
@@ -833,9 +851,6 @@
 	extern char except_vec4;
 	extern char except_vec_ejtag_debug;
 	unsigned long i;
-
-	/* Some firmware leaves the BEV flag set, clear it.  */
-	clear_cp0_status(ST0_BEV);
 
 	/* Copy the generic exception handler code to it's final destination. */
 	memcpy((void *)(KSEG0 + 0x80), &except_vec1_generic, 0x80);

[Linux-mips-commits]CVS: linux/arch/mips/sibyte/sb1 cache_error.c,1.1,1.2

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips/sibyte/sb1
In directory usw-pr-cvs1:/tmp/cvs-serv23204/arch/mips/sibyte/sb1

Modified Files:
	cache_error.c 
Log Message:
Most of it was a collection of fixes and cleanups for mips64 and SMP stuff

Index: cache_error.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/sibyte/sb1/cache_error.c,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- cache_error.c	28 Jan 2002 20:31:57 -0000	1.1
+++ cache_error.c	26 Feb 2002 17:34:15 -0000	1.2
@@ -48,9 +48,10 @@
 asmlinkage void sb1_cache_error(void)
 {
 	unsigned int errctl, cerr_i, cerr_d, cerr_dpa;
-	unsigned int eepc;
+	unsigned long eepc;
+
+	eepc = get_errorepc();
 
-	eepc = read_32bit_cp0_register(CP0_ERROREPC);
 	__asm__ __volatile__ (
 		".set push\n"
 		"#.set mips64\n"
@@ -60,17 +61,19 @@
 		".word 0x4001D801; move %2, $1; # mfc0 %2, $27, 1\n"
 		".word 0x4001D803; move %3, $1; # mfc0 %3, $27, 3\n"
 		".set pop\n"
-		: "=r" (errctl), "=r" (cerr_i), "=r" (cerr_d), "=r" (cerr_dpa));
+		: "=r" (errctl), "=r" (cerr_i),
+		  "=r" (cerr_d), "=r" (cerr_dpa));
 
 	printk("Cache error exception:\n");
-	printk(" cp0_errorepc == %08x\n", eepc);
-	printk(" cp0_errctl   == %08x\n", errctl);
+	printk(" cp0_errorepc == 0x%0lx\n", eepc);
+	printk(" cp0_errctl   == 0x%08x\n", errctl);
+
 	if (errctl & CP0_ERRCTL_DCACHE) {
-		printk(" cp0_cerr_d   == %08x\n", cerr_d);
-		printk(" cp0_cerr_dpa == %08x\n", cerr_dpa);
+		printk(" cp0_cerr_d   == 0x%08x\n", cerr_d);
+		printk(" cp0_cerr_dpa == 0x%08x\n", cerr_dpa);
 	}
 	if (errctl & CP0_ERRCTL_ICACHE) {
-		printk(" cp0_cerr_i   == %08x\n", cerr_i);
+		printk(" cp0_cerr_i   == 0x%08x\n", cerr_i);
 	}
 
 	panic("Can't handle the cache error!");

[Linux-mips-commits]CVS: linux/arch/mips64/sgi-ip32 ip32-setup.c,1.6,1.7

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips64/sgi-ip32
In directory usw-pr-cvs1:/tmp/cvs-serv23204/arch/mips64/sgi-ip32

Modified Files:
	ip32-setup.c 
Log Message:
Most of it was a collection of fixes and cleanups for mips64 and SMP stuff

Index: ip32-setup.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips64/sgi-ip32/ip32-setup.c,v
retrieving revision 1.6
retrieving revision 1.7
diff -u -d -r1.6 -r1.7
--- ip32-setup.c	2 Jan 2002 19:12:18 -0000	1.6
+++ ip32-setup.c	26 Feb 2002 17:34:15 -0000	1.7
@@ -68,7 +68,6 @@
 #ifdef CONFIG_SERIAL_CONSOLE
 	char *ctype;
 #endif
-	current_cpu_data.asid_cache = ASID_FIRST_VERSION;
 	TLBMISS_HANDLER_SETUP ();
 
 	mips_io_port_base = UNCACHEDADDR(MACEPCI_HI_IO);;

[Linux-mips-commits]CVS: linux/arch/mips/vr4181/osprey reset.c,1.3,1.4

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips/vr4181/osprey
In directory usw-pr-cvs1:/tmp/cvs-serv23204/arch/mips/vr4181/osprey

Modified Files:
	reset.c 
Log Message:
Most of it was a collection of fixes and cleanups for mips64 and SMP stuff

Index: reset.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/vr4181/osprey/reset.c,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- reset.c	7 Oct 2001 16:57:20 -0000	1.3
+++ reset.c	26 Feb 2002 17:34:15 -0000	1.4
@@ -18,7 +18,7 @@
 
 void nec_osprey_restart(char *command)
 {
-	change_cp0_status((ST0_BEV | ST0_ERL), (ST0_BEV | ST0_ERL));
+	set_cp0_status(ST0_ERL);
 	change_cp0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);
 	flush_cache_all();
 	write_32bit_cp0_register(CP0_WIRED, 0);

[Linux-mips-commits]CVS: linux/arch/mips/sibyte/swarm smp.c,1.6,1.7

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips/sibyte/swarm
In directory usw-pr-cvs1:/tmp/cvs-serv23204/arch/mips/sibyte/swarm

Modified Files:
	smp.c 
Log Message:
Most of it was a collection of fixes and cleanups for mips64 and SMP stuff

Index: smp.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/sibyte/swarm/smp.c,v
retrieving revision 1.6
retrieving revision 1.7
diff -u -d -r1.6 -r1.7
--- smp.c	19 Feb 2002 17:35:33 -0000	1.6
+++ smp.c	26 Feb 2002 17:34:15 -0000	1.7
@@ -50,8 +50,6 @@
 
 void prom_init_secondary(void)
 {
-	
-
 	/* Set up kseg0 to be cachable coherent */
 	clear_cp0_config(CONF_CM_CMASK);
 	set_cp0_config(0x5);
@@ -86,7 +84,6 @@
 {
 	int i;
 
-	set_context(0);
 	smp_num_cpus = prom_setup_smp();
 	init_new_context(current, &init_mm);
 	current->processor = 0;

[Linux-mips-commits]CVS: linux/arch/mips/jmr3927/rbhma3100 setup.c,1.5,1.6

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips/jmr3927/rbhma3100
In directory usw-pr-cvs1:/tmp/cvs-serv23204/arch/mips/jmr3927/rbhma3100

Modified Files:
	setup.c 
Log Message:
Most of it was a collection of fixes and cleanups for mips64 and SMP stuff

Index: setup.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/jmr3927/rbhma3100/setup.c,v
retrieving revision 1.5
retrieving revision 1.6
diff -u -d -r1.5 -r1.6
--- setup.c	22 Jan 2002 22:08:13 -0000	1.5
+++ setup.c	26 Feb 2002 17:34:14 -0000	1.6
@@ -55,14 +55,11 @@
 #include <asm/gdb-stub.h>
 #include <asm/jmr3927/jmr3927.h>
 #include <asm/mipsregs.h>
-#include <asm/cpu.h>
 
 /* Tick Timer divider */
 #define JMR3927_TIMER_CCD	0	/* 1/2 */
 #define JMR3927_TIMER_CLK	(JMR3927_IMCLK / (2 << JMR3927_TIMER_CCD))
 
-extern struct ide_ops std_ide_ops; 
-
 unsigned char led_state = 0xf;
 
 struct {
@@ -144,7 +141,6 @@
 
 unsigned long jmr3927_do_gettimeoffset(void);
 extern int setup_irq(unsigned int irq, struct irqaction *irqaction);
-
 static void __init jmr3927_timer_setup(struct irqaction *irq)
 {
 	do_gettimeoffset = jmr3927_do_gettimeoffset;
@@ -159,7 +155,6 @@
 }
 
 #define USECS_PER_JIFFY (1000000/HZ)
-
 unsigned long jmr3927_do_gettimeoffset(void)
 {
        unsigned long count;
@@ -191,27 +186,22 @@
 extern unsigned long __rd_start, __rd_end, initrd_start, initrd_end;
 #endif 
 
+//#undef DO_WRITE_THROUGH
+#define DO_WRITE_THROUGH
 #define DO_ENABLE_CACHE
-int mips_config_cwfon;
-int mips_config_wbon;
 
 extern char * __init prom_getcmdline(void);
 static void jmr3927_board_init(void);
 extern void jmr3927_irq_setup(void);
 extern struct resource pci_io_resource;
 extern struct resource pci_mem_resource;
-
-void __init bus_error_init(void)
-{
-}
-
 void __init jmr3927_setup(void)
 {
 	extern int panic_timeout;
 	char *argptr;
 
 	irq_setup = jmr3927_irq_setup;
-	mips_io_port_base = JMR3927_PORT_BASE; 
+	mips_io_port_base = JMR3927_PORT_BASE + JMR3927_PCIIO;
 
 	board_time_init = jmr3927_time_init;
 	board_timer_setup = jmr3927_timer_setup;
@@ -240,24 +230,18 @@
 	/* cache setup */
 	{
 		unsigned int conf;
-		unsigned int processor_id;
 #ifdef DO_ENABLE_CACHE
 		int mips_ic_disable = 0, mips_dc_disable = 0;
 #else
 		int mips_ic_disable = 1, mips_dc_disable = 1;
 #endif
-		processor_id = read_32bit_cp0_register(CP0_PRID);
-		if ((processor_id & 0xff) <= PRID_REV_TX3927B) {
-			/* turn writeback off - see errata */
-			mips_config_cwfon = 0;
-			mips_config_wbon = 0;
-		}
-		else {
-			mips_config_cwfon = 1;
-			mips_config_wbon = 1;
-		}
-
-		clear_cp0_status(ST0_BEV);
+#ifdef DO_WRITE_THROUGH
+		int mips_config_cwfon = 0;
+		int mips_config_wbon = 0;
+#else
+		int mips_config_cwfon = 1;
+		int mips_config_wbon = 1;
+#endif
 
 		conf = read_32bit_cp0_register(CP0_CONF);
 		conf &= ~(TX39_CONF_ICE | TX39_CONF_DCE | TX39_CONF_WBON | TX39_CONF_CWFON);
@@ -279,6 +263,11 @@
 	if ((argptr = strstr(argptr, "toeon")) != NULL) {
 			jmr3927_ccfg_toeon = 1;
 	}
+	argptr = prom_getcmdline();
+	if ((argptr = strstr(argptr, "ip=")) == NULL) {
+		argptr = prom_getcmdline();
+		strcat(argptr, " ip=bootp");
+	}
 
 #ifdef CONFIG_TXX927_SERIAL_CONSOLE
 	argptr = prom_getcmdline();
@@ -300,8 +289,9 @@
 /* for legacy I/O, PCI I/O PCI Bus address must be 0 */
 unsigned long mips_pci_io_pciaddr = 0;
 #endif
-
-static void __init jmr3927_board_init()
+extern struct rtc_ops *rtc_ops;
+extern struct rtc_ops jmr3927_rtc_ops;
+static void jmr3927_board_init()
 {
 	char *argptr;
 
@@ -336,15 +326,17 @@
 		//not yet kbd_ops = &jmr3927_kbd_ops;
 #endif
 	}
+#ifdef USE_RTC_DS1742
+	if (jmr3927_have_nvram()) {
+		rtc_ops = &jmr3927_rtc_ops;
+	}
+#endif
 
 	/* SIO0 DTR on */
 	jmr3927_ioc_reg_out(0, JMR3927_IOC_DTR_ADDR);
 
 	jmr3927_led_set(0);
 
-#ifdef CONFIG_BLK_DEV_IDE
-	ide_ops = &std_ide_ops;
-#endif
 
 	if (jmr3927_have_isac()) 
 		jmr3927_io_led_set(0);
@@ -358,8 +350,7 @@
 		       jmr3927_isac_reg_in(JMR3927_ISAC_REV_ADDR) & JMR3927_REV_MASK,
 		       jmr3927_io_dipsw());
 }
-
-static void __init tx3927_setup(void)
+static void tx3927_setup(void)
 {
 	int i;
 
@@ -381,10 +372,10 @@
 	/* Disable PCI snoop */
 	tx3927_ccfgptr->ccfg &= ~TX3927_CCFG_PSNP;
 
-	if (!mips_config_wbon) { 
-		/* Enable PCI SNOOP - with write through only */
-		tx3927_ccfgptr->ccfg |= TX3927_CCFG_PSNP;
-	}
+#ifdef DO_WRITE_THROUGH
+	/* Enable PCI SNOOP - with write through only */
+	tx3927_ccfgptr->ccfg |= TX3927_CCFG_PSNP;
+#endif
 
 	/* Pin selection */
 	tx3927_ccfgptr->pcfg &= ~TX3927_PCFG_SELALL;
@@ -439,7 +430,6 @@
 	printk("TX3927 PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:",
 	       tx3927_pcicptr->did, tx3927_pcicptr->vid,
 	       tx3927_pcicptr->rid);
-
 	if (!(tx3927_ccfgptr->ccfg & TX3927_CCFG_PCIXARB)) {
 		printk("External\n");
 		/* XXX */
@@ -480,6 +470,7 @@
 		/* Enable Direct mapping Address Space Decoder */
 		tx3927_pcicptr->lbc |= TX3927_PCIC_LBC_ILMDE | TX3927_PCIC_LBC_ILIDE;
 #endif
+
 		/* Clear All Local Bus Status */
 		tx3927_pcicptr->lbstat = TX3927_PCIC_LBIM_ALL;
 		/* Enable All Local Bus Interrupts */

[Linux-mips-commits]CVS: linux/arch/mips/galileo-boards/ev64120 irq.c,1.5,1.6

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips/galileo-boards/ev64120
In directory usw-pr-cvs1:/tmp/cvs-serv23204/arch/mips/galileo-boards/ev64120

Modified Files:
	irq.c 
Log Message:
Most of it was a collection of fixes and cleanups for mips64 and SMP stuff

Index: irq.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/galileo-boards/ev64120/irq.c,v
retrieving revision 1.5
retrieving revision 1.6
diff -u -d -r1.5 -r1.6
--- irq.c	2 Jan 2002 18:01:13 -0000	1.5
+++ irq.c	26 Feb 2002 17:34:14 -0000	1.6
@@ -26,7 +26,6 @@
  *  You should have received a copy of the  GNU General Public License along
  *  with this program; if not, write  to the Free Software Foundation, Inc.,
  *  675 Mass Ave, Cambridge, MA 02139, USA.
- *
  */
 #include <linux/errno.h>
 #include <linux/init.h>
@@ -43,144 +42,414 @@
 #include <asm/bitops.h>
 #include <asm/bootinfo.h>
 #include <asm/io.h>
-#include <asm/irq.h>
 #include <asm/mipsregs.h>
 #include <asm/system.h>
 #include <asm/galileo-boards/ev64120int.h>
 
-extern void do_IRQ(int irq, struct pt_regs *regs);
+#undef IRQ_DEBUG
+
+#ifdef IRQ_DEBUG
+#define DBG(x...) printk(x)
+#else
+#define DBG(x...)
+#endif
+
+
+asmlinkage void do_IRQ(int irq, struct pt_regs *regs);
 
 #define MAX_AGENTS_PER_INT 21	/*  Random number  */
 unsigned char pci_int_irq[MAX_AGENTS_PER_INT];
 static int max_interrupts = 0;
 
-asmlinkage void pci_intA(struct pt_regs *regs)
+/*  Duplicate interrupt handlers.  */
+/********************************************************************
+ *pci_int(A/B/C/D) -
+ *	
+ *Calls all the handlers connected to PCI interrupt A/B/C/D
+ *
+ *Inputs :
+ *
+ *Outpus :
+ *
+ *********************************************************************/
+asmlinkage __inline__ void pci_intA(struct pt_regs *regs)
 {
 	unsigned int count = 0;
-
-	/* This must be a joke - Ralf  */
-	for (count = 0; count < max_interrupts; count++)
+	DBG(KERN_INFO "pci_intA, max_interrupts %d\n", max_interrupts);
+	for (count = 0; count < max_interrupts; count++) {
 		do_IRQ(pci_int_irq[count], regs);
+	}
 }
 
-asmlinkage void pci_intD(struct pt_regs *regs)
+asmlinkage __inline__ void pci_intD(struct pt_regs *regs)
 {
 	unsigned int count = 0;
-
-	/* Encore une fois - This must be a joke - Ralf  */
-	for (count = 0; count < max_interrupts; count++)
+	DBG(KERN_INFO "pci_intD, max_interrupts %d\n", max_interrupts);
+	for (count = 0; count < max_interrupts; count++) {
 		do_IRQ(pci_int_irq[count], regs);
+	}
 }
 
-/*
- * Now this is scarry.  A disable_irq(2) or disable_irq(5) would just
- * accidently disable a pci irq.  It shouldn't happen but may just leaving
- * these always enabled or use some reference counting wouldn't be such a
- * bad thing.
- */
-static void disable_ev64120_irq(unsigned int irq_nr)
+
+/* Function for careful CP0 interrupt mask access */
+static inline void modify_cp0_intmask(unsigned clr_mask, unsigned set_mask)
+{
+	unsigned long status = read_32bit_cp0_register(CP0_STATUS);
+	DBG(KERN_INFO "modify_cp0_intmask clr %x, set %x\n", clr_mask,
+	    set_mask);
+	DBG(KERN_INFO "modify_cp0_intmask status %x\n", status);
+	status &= ~((clr_mask & 0xFF) << 8);
+	status |= (set_mask & 0xFF) << 8;
+	DBG(KERN_INFO "modify_cp0_intmask status %x\n", status);
+	write_32bit_cp0_register(CP0_STATUS, status);
+}
+
+static inline void mask_irq(unsigned int irq_nr)
+{
+	modify_cp0_intmask(irq_nr, 0);
+}
+
+static inline void unmask_irq(unsigned int irq_nr)
+{
+	modify_cp0_intmask(0, irq_nr);
+}
+
+void disable_irq(unsigned int irq_nr)
 {
 	unsigned long flags;
 
-	__save_and_cli(flags);
-	if (irq_nr >= 8) {
-		/* All PCI interrupts are on line 5 or 2  */
-		clear_cp0_status(IE_IRQ0 | IE_IRQ3);
+	DBG(KERN_INFO "disable_irq, irq %d\n", irq_nr);
+	save_and_cli(flags);
+	if (irq_nr >= 8) {	// All PCI interrupts are on line 5 or 2
+		mask_irq(9 << 2);
 	} else {
-		clear_cp0_status(0x100 << irq_nr);
+		mask_irq(1 << irq_nr);
 	}
-	__restore_flags(flags);
+	restore_flags(flags);
 }
 
-#define mask_and_ack_ev64120_irq disable_ev64120_irq
-
-static inline void enable_ev64120_irq(unsigned int irq_nr)
+void enable_irq(unsigned int irq_nr)
 {
 	unsigned long flags;
 
-	__save_and_cli(flags);
-	if (irq_nr >= 8) {
-		/* All PCI interrupts are on line 5 or 2  */
-		set_cp0_status(IE_IRQ0 | IE_IRQ3);
+	DBG(KERN_INFO "enable_irq, irq %d\n", irq_nr);
+	save_and_cli(flags);
+	if (irq_nr >= 8) {	// All PCI interrupts are on line 5 or 2
+		DBG(KERN_INFO __FUNCTION__ " pci interrupt %d\n", irq_nr);
+		unmask_irq(9 << 2);
 	} else {
-		set_cp0_status(IE_SW0 << irq_nr);
+		DBG(KERN_INFO __FUNCTION__ " interrupt set mask %d\n",
+		    1 << irq_nr);
+		unmask_irq(1 << irq_nr);
 	}
-	__restore_flags(flags);
+	restore_flags(flags);
 }
 
-static unsigned int startup_ev64120_irq(unsigned int irq)
+/*
+ * Generic no controller code
+ */
+
+static void no_irq_enable_disable(unsigned int irq)
 {
-	if (irq >= 8) {
-		// NOTE:  Add error-handling if > max
-		pci_int_irq[max_interrupts++] = irq;
+}
+static unsigned int no_irq_startup(unsigned int irq)
+{
+	return 0;
+}
+
+#if 0
+static void no_irq_ack(unsigned int irq)
+{
+	printk(KERN_CRIT "Unexpected IRQ trap at vector %u\n", irq);
+}
+#endif
+
+struct hw_interrupt_type no_irq_type = {
+	typename:"none",
+	startup:no_irq_startup,
+	shutdown:no_irq_enable_disable,
+	enable:no_irq_enable_disable,
+	disable:no_irq_enable_disable,
+	ack:NULL,
+	end:no_irq_enable_disable,
+};
+
+//      ack:            no_irq_ack,                re-enable later -- SKJ  
+
+
+/*
+ * Controller mappings for all interrupt sources:
+ */
+irq_desc_t irq_desc[NR_IRQS];
+
+atomic_t irq_err_count;
+
+int get_irq_list(char *buf)
+{
+	int i, len = 0, j;
+	struct irqaction *action;
+
+	len += sprintf(buf + len, "           ");
+	for (j = 0; j < smp_num_cpus; j++)
+		len += sprintf(buf + len, "CPU%d       ", j);
+	*(char *) (buf + len++) = '\n';
+
+	for (i = 0; i < NR_IRQS; i++) {
+		action = irq_desc[i].action;
+		if (!action || !action->handler)
+			continue;
+		len += sprintf(buf + len, "%3d: ", i);
+		len += sprintf(buf + len, "%10u ", kstat_irqs(i));
+		if (irq_desc[i].handler)
+			len +=
+			    sprintf(buf + len, " %s ",
+				    irq_desc[i].handler->typename);
+		else
+			len += sprintf(buf + len, "  None      ");
+		len += sprintf(buf + len, "    %s", action->name);
+		for (action = action->next; action; action = action->next) {
+			len += sprintf(buf + len, ", %s", action->name);
+		}
+		len += sprintf(buf + len, "\n");
 	}
-	enable_ev64120_irq(irq);
+	len += sprintf(buf + len, "BAD: %10lu\n", atomic_read(&irq_err_count));
+	return len;
+}
 
+asmlinkage void do_IRQ(int irq, struct pt_regs *regs)
+{
+	struct irqaction *action;
+	int cpu;
+
+#ifdef IRQ_DEBUG
+	if (irq != TIMER)
+		DBG(KERN_INFO __FUNCTION__ " irq = %d\n", irq);
+	if (irq != TIMER)
+		DBG(KERN_INFO "cause register = %x\n",
+		    read_32bit_cp0_register(CP0_CAUSE));
+	if (irq != TIMER)
+		DBG(KERN_INFO "status register = %x\n",
+		    read_32bit_cp0_register(CP0_STATUS));
+#endif
+
+	cpu = smp_processor_id();
+	irq_enter(cpu, irq);
+	kstat.irqs[cpu][irq]++;
+
+	if (irq_desc[irq].handler->ack) {
+		irq_desc[irq].handler->ack(irq);
+	}
+
+	disable_irq(irq);
+
+	action = irq_desc[irq].action;
+	if (action && action->handler) {
+#ifdef IRQ_DEBUG
+		if (irq != TIMER)
+			DBG(KERN_INFO
+			    "rr: irq %d action %p and handler %p\n", irq,
+			    action, action->handler);
+#endif
+		if (!(action->flags & SA_INTERRUPT))
+			__sti();
+		do {
+			action->handler(irq, action->dev_id, regs);
+			action = action->next;
+		} while (action);
+		__cli();
+		if (irq_desc[irq].handler) {
+			if (irq_desc[irq].handler->end)
+				irq_desc[irq].handler->end(irq);
+			else if (irq_desc[irq].handler->enable)
+				irq_desc[irq].handler->enable(irq);
+		}
+	}
+
+	enable_irq(irq);
+	irq_exit(cpu, irq);
+
+	if (softirq_pending(cpu))
+		do_softirq();
+
+	/* unmasking and bottom half handling is done magically for us. */
+}
+
+int request_irq(unsigned int irq,
+		void (*handler) (int, void *, struct pt_regs *),
+		unsigned long irqflags, const char *devname, void *dev_id)
+{
+	struct irqaction *old, **p, *action;
+	unsigned long flags;
+
+	DBG(KERN_INFO "rr:dev %s irq %d handler %x\n", devname, irq,
+	    handler);
+	if (irq >= NR_IRQS)
+		return -EINVAL;
+
+	action = (struct irqaction *)
+	    kmalloc(sizeof(struct irqaction), GFP_KERNEL);
+	if (!action)
+		return -ENOMEM;
+
+	action->handler = handler;
+	action->flags = irqflags;
+	action->mask = 0;
+	action->name = devname;
+	action->dev_id = dev_id;
+	action->next = NULL;
+
+	save_flags(flags);
+	cli();
+
+	p = &irq_desc[irq].action;
+
+	if ((old = *p) != NULL) {
+		/* Can't share interrupts unless both agree to */
+		if (!(old->flags & action->flags & SA_SHIRQ))
+			return -EBUSY;
+		/* add new interrupt at end of irq queue */
+		do {
+			p = &old->next;
+			old = *p;
+		} while (old);
+	}
+	*p = action;
+
+	restore_flags(flags);
+	if (irq >= 8) {
+		DBG(KERN_INFO "request_irq, max_interrupts %d\n",
+		    max_interrupts);
+		pci_int_irq[max_interrupts++] = irq;	// NOTE:  Add error-handling if > max
+	}
+	enable_irq(irq);
 	return 0;
 }
 
-static void shutdown_ev64120_irq(unsigned int irq)
+
+void free_irq(unsigned int irq, void *dev_id)
 {
-	int count, tmp;
+	struct irqaction *p, *old = NULL;
+	unsigned long flags;
+	int count, tmp, removed = 0;
+
+	for (p = irq_desc[irq].action; p != NULL; old = p, p = p->next) {
+		/* Found the IRQ, is it the correct dev_id?  */
+		if (dev_id == p->dev_id) {
+			save_flags(flags);
+			cli();
+
+			// remove link from list
+			if (old)
+				old->next = p->next;
+			else
+				irq_desc[irq].action = p->next;
+
+			restore_flags(flags);
+			kfree(p);
+			removed = 1;
+			break;
+		}
+	}
 
 	/*
-	 * Remove PCI interrupts from the pci_int_irq list.  Make sure
-	 * that some handler was removed before decrementing max_interrupts.
+	   Remove PCI interrupts from the pci_int_irq list.  Make sure
+	   that some handler was removed before decrementing max_interrupts.
 	 */
-	if (irq >= 8) {
+	if ((irq >= 8) && (removed)) {
 		for (count = 0; count < max_interrupts; count++) {
 			if (pci_int_irq[count] == irq) {
-				for (tmp = count; tmp < max_interrupts; tmp++) {
+				for (tmp = count; tmp < max_interrupts;
+				     tmp++) {
 					pci_int_irq[tmp] =
 					    pci_int_irq[tmp + 1];
 				}
 			}
 		}
 		max_interrupts--;
+		DBG(KERN_INFO "free_irq, max_interrupts %d\n",
+		    max_interrupts);
 	}
 }
 
-static void end_ev64120_irq(unsigned int irq)
+unsigned long probe_irq_on(void)
 {
-	if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
-		enable_ev64120_irq(irq);
+	printk(KERN_INFO "probe_irq_on\n");
+	return 0;
 }
 
-static struct hw_interrupt_type ev64120_irq_type = {
-	"EV64120",
-	startup_ev64120_irq,
-	shutdown_ev64120_irq,
-	enable_ev64120_irq,
-	disable_ev64120_irq,
-	mask_and_ack_ev64120_irq,
-	end_ev64120_irq
-};
+int probe_irq_off(unsigned long irqs)
+{
+	printk(KERN_INFO "probe_irq_off\n");
+	return 0;
+}
 
-/*
- * galileo_irq_setup - Initializes CPU interrupts
- */
-void __init init_IRQ(void)
+/********************************************************************
+ *galileo_irq_setup -
+ *
+ *Initializes CPU interrupts
+ *
+ *
+ *Inputs :
+ *
+ *Outpus :
+ *
+ *********************************************************************/
+void galileo_irq_setup(void)
 {
 	extern asmlinkage void galileo_handle_int(void);
-	int i;
+	extern void galileo_irq_init(void);
 
-	init_generic_irq();
+	DBG(KERN_INFO "rr: galileo_irq_setup entry\n");
 
-	/* Yes, how many interrupts does this beast actually have?  -- Ralf */
-	for (i = 0; i < NR_IRQS; i++) {
-		irq_desc[i].status      = IRQ_DISABLED;
-		irq_desc[i].action      = 0;
-		irq_desc[i].depth       = 1;
-		irq_desc[i].handler     = &ev64120_irq_type;
-	}
+	galileo_irq_init();
 
 	/*
 	 * Clear all of the interrupts while we change the able around a bit.
-	 * Enable timer.  Other interrupts will be enabled as they are
-	 * registered.
 	 */
-	change_cp0_status(ST0_IM | ST0_BEV | IE_IRQ2, IE_IRQ2);
+	clear_cp0_status(ST0_IM);
 
 	/* Sets the exception_handler array. */
 	set_except_vector(0, galileo_handle_int);
+
+	cli();
+
+	/*
+	 * Enable timer.  Other interrupts will be enabled as they are
+	 * registered.
+	 */
+	set_cp0_status(IE_IRQ2);
+
+
+#ifdef CONFIG_REMOTE_DEBUG
+	{
+		extern int DEBUG_CHANNEL;
+		serial_init(DEBUG_CHANNEL);
+		serial_set(DEBUG_CHANNEL, 115200);
+		set_debug_traps();
+		breakpoint();	/* you may move this line to whereever you want :-) */
+	}
+#endif
+}
+
+void init_irq_proc(void)
+{
+	/* Nothing, for now.  */
+}
+
+void __init init_IRQ(void)
+{
+	int i;
+
+	DBG(KERN_INFO "rr:init_IRQ\n");
+
+	/*  Let's initialize our IRQ descriptors  */
+	for (i = 0; i < NR_IRQS; i++) {
+		irq_desc[i].status = 0;
+		irq_desc[i].handler = &no_irq_type;
+		irq_desc[i].action = NULL;
+		irq_desc[i].depth = 0;
+		irq_desc[i].lock = SPIN_LOCK_UNLOCKED;
+	}
+
+	galileo_irq_setup();
 }

[Linux-mips-commits]CVS: linux/arch/mips/cobalt reset.c,1.2,1.3

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips/cobalt
In directory usw-pr-cvs1:/tmp/cvs-serv23204/arch/mips/cobalt

Modified Files:
	reset.c 
Log Message:
Most of it was a collection of fixes and cleanups for mips64 and SMP stuff

Index: reset.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/cobalt/reset.c,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -d -r1.2 -r1.3
--- reset.c	9 Jul 2001 21:50:55 -0000	1.2
+++ reset.c	26 Feb 2002 17:34:14 -0000	1.3
@@ -1,5 +1,13 @@
 /*
- *  Reset a Cobalt Qube.
+ * Cobalt Reset operations
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995, 1996, 1997 by Ralf Baechle
+ * Copyright (C) 2001 by Liam Davies (ld...@ag...)
+ *
  */
 #include <linux/config.h>
 #include <linux/sched.h>
@@ -15,41 +23,41 @@
 {
 	*(volatile char *)0xbc000000 = 0x0f;
 
-       /*
-        * Ouch, we're still alive ... This time we take the silver bullet ...
-        * ... and find that we leave the hardware in a state in which the
-        * kernel in the flush locks up somewhen during of after the PCI
-        * detection stuff.
-        */
-       	set_cp0_status(ST0_BEV | ST0_ERL);
-       	set_cp0_config(CONF_CM_UNCACHED);
-       	flush_cache_all();
-       	write_32bit_cp0_register(CP0_WIRED, 0);
-       	__asm__ __volatile__(
-        	"jr\t%0"
-               	:
-               	: "r" (0xbfc00000));
+	/*
+	 * Ouch, we're still alive ... This time we take the silver bullet ...
+	 * ... and find that we leave the hardware in a state in which the
+	 * kernel in the flush locks up somewhen during of after the PCI
+	 * detection stuff.
+	 */
+	set_cp0_status(ST0_BEV | ST0_ERL);
+	change_cp0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);
+	flush_cache_all();
+	write_32bit_cp0_register(CP0_WIRED, 0);
+	__asm__ __volatile__(
+		"jr\t%0"
+		:
+		: "r" (0xbfc00000));
 }
 
 extern int led_state;
 #define kLED            0xBC000000
-#define LEDSet(x)       (*(volatile unsigned char *) kLED) = ((unsigned char)x)
+#define LEDSet(x)       (*(volatile unsigned char *) kLED) = (( unsigned char)x)
 
 void cobalt_machine_halt(void)
 {
-      	int mark;
+	int mark;
 
-       	// Blink our cute little LED (number 3)...
-       	while (1) {
-               	led_state = led_state | ( 1 << 3 );
-               	LEDSet(led_state);
-               	mark = jiffies;
-               	while (jiffies<(mark+HZ));
-               	led_state = led_state & ~( 1 << 3 );
-               	LEDSet(led_state);
-               	mark = jiffies;
-               	while (jiffies<(mark+HZ));
-       	}
+	/* Blink our cute? little LED (number 3)... */
+	while (1) {
+		led_state = led_state | ( 1 << 3 );
+		LEDSet(led_state);  
+		mark = jiffies;
+		while (jiffies<(mark+HZ));
+		led_state = led_state & ~( 1 << 3 );
+		LEDSet(led_state);
+		mark = jiffies;
+		while (jiffies<(mark+HZ));
+	} 
 }
 
 /*
@@ -57,6 +65,6 @@
  */
 void cobalt_machine_power_off(void)
 {
-       	printk("You can switch the machine off now.\n");
-       	cobalt_machine_halt();
+	printk("You can switch the machine off now.\n");
+	cobalt_machine_halt();
 }

[Linux-mips-commits]CVS: linux/arch/mips/galileo-boards/generic reset.c,1.2,1.3

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips/galileo-boards/generic
In directory usw-pr-cvs1:/tmp/cvs-serv23204/arch/mips/galileo-boards/generic

Modified Files:
	reset.c 
Log Message:
Most of it was a collection of fixes and cleanups for mips64 and SMP stuff

Index: reset.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/galileo-boards/generic/reset.c,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -d -r1.2 -r1.3
--- reset.c	16 Nov 2001 23:10:53 -0000	1.2
+++ reset.c	26 Feb 2002 17:34:14 -0000	1.3
@@ -1,5 +1,4 @@
 /*
- *
  * BRIEF MODULE DESCRIPTION
  *	Galileo EV96100 reset routines.
  *

[Linux-mips-commits]CVS: linux/arch/mips/gt64120/momenco_ocelot irq.c,1.3,1.4

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips/gt64120/momenco_ocelot
In directory usw-pr-cvs1:/tmp/cvs-serv23204/arch/mips/gt64120/momenco_ocelot

Modified Files:
	irq.c 
Log Message:
Most of it was a collection of fixes and cleanups for mips64 and SMP stuff

Index: irq.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/gt64120/momenco_ocelot/irq.c,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- irq.c	18 Dec 2001 00:34:13 -0000	1.3
+++ irq.c	26 Feb 2002 17:34:14 -0000	1.4
@@ -143,9 +143,8 @@
 
 	/*
 	 * Clear all of the interrupts while we change the able around a bit.
-	 * int-handler is not on bootstrap
 	 */
-	clear_cp0_status(ST0_IM | ST0_BEV);
+	clear_cp0_status(ST0_IM);
 	__cli();
 
 	/* Sets the first-level interrupt dispatcher. */

[Linux-mips-commits]CVS: linux/arch/mips/au1000/common reset.c,1.3,1.4

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips/au1000/common
In directory usw-pr-cvs1:/tmp/cvs-serv23204/arch/mips/au1000/common

Modified Files:
	reset.c 
Log Message:
Most of it was a collection of fixes and cleanups for mips64 and SMP stuff

Index: reset.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/au1000/common/reset.c,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- reset.c	15 Feb 2002 19:47:24 -0000	1.3
+++ reset.c	26 Feb 2002 17:34:14 -0000	1.4
@@ -86,7 +86,7 @@
 		break;
 	}
 
-	set_cp0_status((ST0_BEV | ST0_ERL));
+	set_cp0_status(ST0_BEV | ST0_ERL);
 	set_cp0_config(CONF_CM_UNCACHED);
 	flush_cache_all();
 	write_32bit_cp0_register(CP0_WIRED, 0);

[Linux-mips-commits]CVS: linux/include/asm-mips cpu.h,1.21,1.22 mipsregs.h,1.18,1.19

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/include/asm-mips
In directory usw-pr-cvs1:/tmp/cvs-serv14866/asm-mips

Modified Files:
	cpu.h mipsregs.h 
Log Message:
Implement {get,set}_errorepc() to access the c0_errorepc register.

Index: cpu.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/cpu.h,v
retrieving revision 1.21
retrieving revision 1.22
diff -u -d -r1.21 -r1.22
--- cpu.h	19 Jan 2002 21:17:35 -0000	1.21
+++ cpu.h	26 Feb 2002 17:08:29 -0000	1.22
@@ -137,7 +137,7 @@
 	CPU_R5000A, CPU_R4640, CPU_NEVADA, CPU_RM7000, CPU_R5432, CPU_4KC,
 	CPU_5KC, CPU_R4310, CPU_SB1, CPU_TX3912, CPU_TX3922, CPU_TX3927,
 	CPU_AU1000, CPU_4KEC, CPU_4KSC, CPU_VR41XX, CPU_R5500, CPU_TX49XX,
-	CPU_TX39XX, CPU_R5900, CPU_AU1500, CPU_RC32300, CPU_SR7100, CPU_LAST
+	CPU_TX39XX, CPU_AU1500, CPU_R5900, CPU_RC32300, CPU_SR7100, CPU_LAST
 };
 
 #endif

Index: mipsregs.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/mipsregs.h,v
retrieving revision 1.18
retrieving revision 1.19
diff -u -d -r1.18 -r1.19
--- mipsregs.h	19 Feb 2002 17:25:24 -0000	1.18
+++ mipsregs.h	26 Feb 2002 17:08:29 -0000	1.19
@@ -900,6 +900,30 @@
 		: : "Jr" (val));
 }
 
+static inline unsigned long get_errorepc(void)
+{
+	unsigned long val;
+
+	__asm__ __volatile__(
+		".set push\n\t"
+		".set reorder\n\t"
+		"mfc0 %0, $30\n\t"
+		".set pop"
+		: "=r" (val));
+
+	return val;
+}
+
+static inline void set_errorepc(unsigned long val)
+{
+	__asm__ __volatile__(
+		".set push\n\t"
+		".set reorder\n\t"
+		"mtc0 %z0, $30\n\t"
+		".set pop"
+		: : "Jr" (val));
+}
+
 /*
  * Manipulate the status register.
  * Mostly used to access the interrupt bits.

[Linux-mips-commits]CVS: linux/include/asm-mips64 mipsregs.h,1.10,1.11

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/include/asm-mips64
In directory usw-pr-cvs1:/tmp/cvs-serv14866/asm-mips64

Modified Files:
	mipsregs.h 
Log Message:
Implement {get,set}_errorepc() to access the c0_errorepc register.

Index: mipsregs.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips64/mipsregs.h,v
retrieving revision 1.10
retrieving revision 1.11
diff -u -d -r1.10 -r1.11
--- mipsregs.h	19 Feb 2002 17:25:25 -0000	1.10
+++ mipsregs.h	26 Feb 2002 17:08:29 -0000	1.11
@@ -793,6 +793,30 @@
 		: : "Jr" (val));
 }
 
+static inline unsigned long get_errorepc(void)
+{
+	unsigned long val;
+
+	__asm__ __volatile__(
+		".set push\n\t"
+		".set reorder\n\t"
+		"dmfc0 %0, $30\n\t"
+		".set pop"
+		: "=r" (val));
+
+	return val;
+}
+
+static inline void set_errorepc(unsigned long val)
+{
+	__asm__ __volatile__(
+		".set push\n\t"
+		".set reorder\n\t"
+		"dmtc0 %z0, $30\n\t"
+		".set pop"
+		: : "Jr" (val));
+}
+
 /*
  * Manipulate the status register.
  * Mostly used to access the interrupt bits.

[Linux-mips-commits]CVS: linux/arch/mips64/mm Makefile,1.1,1.2

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips64/mm
In directory usw-pr-cvs1:/tmp/cvs-serv4980/mm

Modified Files:
	Makefile 
Log Message:
Rearrange TLB exception handlers similarly to 32-bit kernel.

Index: Makefile
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips64/mm/Makefile,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- Makefile	28 Jan 2002 20:31:57 -0000	1.1
+++ Makefile	26 Feb 2002 16:36:12 -0000	1.2
@@ -2,18 +2,29 @@
 # Makefile for the Linux/MIPS-specific parts of the memory manager.
 #
 
+.S.o:
+	$(CC) $(CFLAGS) $(CFLAGS_$@) -c $< -o $*.o
+
 O_TARGET := mm.o
 
 export-objs			+= umap.o
 obj-y				:= extable.o init.o fault.o loadmmu.o
 
-obj-$(CONFIG_CPU_R4300)		+= r4xx0.o
-obj-$(CONFIG_CPU_R4X00)		+= r4xx0.o
-obj-$(CONFIG_CPU_R5000)		+= r4xx0.o
-obj-$(CONFIG_CPU_NEVADA)	+= r4xx0.o
-obj-$(CONFIG_CPU_R10000)	+= andes.o
-obj-$(CONFIG_CPU_SB1)		+= pg-sb1.o c-sb1.o tlb-sb1.o
+obj-$(CONFIG_CPU_R4300)		+= r4xx0.o tlbex-r4k.o tlb-glue-r4k.o
+obj-$(CONFIG_CPU_R4X00)		+= r4xx0.o tlbex-r4k.o tlb-glue-r4k.o
+obj-$(CONFIG_CPU_R5000)		+= r4xx0.o tlbex-r4k.o tlb-glue-r4k.o
+obj-$(CONFIG_CPU_NEVADA)	+= r4xx0.o tlbex-r4k.o tlb-glue-r4k.o
+obj-$(CONFIG_CPU_R10000)	+= andes.o tlbex-r4k.o tlb-glue-r4k.o
+obj-$(CONFIG_CPU_SB1)		+= pg-sb1.o c-sb1.o tlb-sb1.o tlbex-r4k.o \
+				   tlb-glue-r4k.o
+
+#
+# Debug TLB exception handler, currently unused
+#
+#obj-y				+=  tlb-dbg-r4k.o tlb-glue-r4k.o
 
 obj-$(CONFIG_SGI_IP22)		+= umap.o
+
+CFLAGS_tlb-glue-r4k.o := -P
 
 include $(TOPDIR)/Rules.make

[Linux-mips-commits]CVS: linux/arch/mips64/kernel Makefile,1.4,1.5 r4k_tlb_glue.S,1.2,NONE

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips64/kernel
In directory usw-pr-cvs1:/tmp/cvs-serv4980/kernel

Modified Files:
	Makefile 
Removed Files:
	r4k_tlb_glue.S 
Log Message:
Rearrange TLB exception handlers similarly to 32-bit kernel.

Index: Makefile
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips64/kernel/Makefile,v
retrieving revision 1.4
retrieving revision 1.5
diff -u -d -r1.4 -r1.5
--- Makefile	28 Jan 2002 20:31:57 -0000	1.4
+++ Makefile	26 Feb 2002 16:36:12 -0000	1.5
@@ -16,9 +16,9 @@
 export-objs = irq.o mips64_ksyms.o pci-dma.o smp.o
 
 obj-y	:= branch.o entry.o irq.o proc.o process.o ptrace.o r4k_cache.o \
-	   r4k_fpu.o r4k_genex.o r4k_switch.o r4k_tlb.o r4k_tlb_debug.o \
-	   r4k_tlb_glue.o reset.o scall_64.o semaphore.o setup.o signal.o \
-	   softfp.o syscall.o time.o traps.o unaligned.o
+	   r4k_fpu.o r4k_genex.o r4k_switch.o reset.o scall_64.o \
+	   semaphore.o setup.o signal.o softfp.o syscall.o time.o traps.o \
+	   unaligned.o
 
 obj-$(CONFIG_I8259)		+= i8259.o
 obj-$(CONFIG_IRQ_CPU)		+= irq_cpu.o
@@ -33,6 +33,5 @@
 endif
 
 CFLAGS_r4k_genex.o := -P
-CFLAGS_r4k_tlb_glue.o := -P
 
 include $(TOPDIR)/Rules.make

--- r4k_tlb_glue.S DELETED ---

[Linux-mips-commits]CVS: linux/arch/mips/kernel proc.c,1.14,1.15

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips/kernel
In directory usw-pr-cvs1:/tmp/cvs-serv23733

Modified Files:
	proc.c 
Log Message:
Synced to OSS proc

Index: proc.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/kernel/proc.c,v
retrieving revision 1.14
retrieving revision 1.15
diff -u -d -r1.14 -r1.15
--- proc.c	15 Feb 2002 19:47:27 -0000	1.14
+++ proc.c	19 Feb 2002 18:13:00 -0000	1.15
@@ -60,14 +60,14 @@
 	[CPU_TX3922]	"TX3922",
 	[CPU_TX3927]	"TX3927",
         [CPU_AU1000]	"Au1000",
+	[CPU_AU1500]	"Au1500",
 	[CPU_4KEC]	"MIPS 4KEc",
 	[CPU_4KSC]	"MIPS 4KSc",
 	[CPU_VR41XX]	"NEC Vr41xx",
 	[CPU_R5500]	"R5500",
 	[CPU_TX49XX]	"TX49xx",
         [CPU_TX39XX]	"TX39xx",
-	[CPU_R5900]	"R5900",
-	[CPU_AU1500]	"Au1500"
+	[CPU_R5900]	"R5900"
 };
 
 
@@ -86,11 +86,8 @@
 	/*
 	 * For the first processor also print the system type
 	 */
-#if 0
 	if (n == 0)
 		seq_printf(m, "system type\t\t: %s\n", get_system_type());
-#endif
-	
 
 	seq_printf(m, "processor\t\t: %ld\n", n);
 	sprintf(fmt, "cpu model\t\t: %%s V%%d.%%d%s\n",
@@ -105,6 +102,7 @@
 	seq_printf(m, "wait instruction\t: %s\n", cpu_wait ? "yes" : "no");
 	seq_printf(m, "microsecond timers\t: %s\n",
 	              (mips_cpu.options & MIPS_CPU_COUNTER) ? "yes" : "no");
+	seq_printf(m, "tlb_entries\t\t: %d\n", mips_cpu.tlbsize);
 	seq_printf(m, "extra interrupt vector\t: %s\n",
 	              (mips_cpu.options & MIPS_CPU_DIVEC) ? "yes" : "no");
 	seq_printf(m, "hardware watchpoint\t: %s\n",

[Linux-mips-commits]CVS: linux/include/asm-mips mc146818rtc.h,1.2,1.3

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/include/asm-mips
In directory usw-pr-cvs1:/tmp/cvs-serv20607

Added Files:
	mc146818rtc.h 
Log Message:
RTC changes