[rvm-commits] SF.net SVN: jikesrvm: [13831] rvmroot/trunk/rvm/src-generated/opt-burs/ia32 /IA32_SSE2.rules

[<cap...@us...>]

Revision: 13831
          http://jikesrvm.svn.sourceforge.net/jikesrvm/?rev=13831&view=rev
Author:   captain5050
Date:     2007-10-26 16:37:56 -0700 (Fri, 26 Oct 2007)

Log Message:
-----------
Must assign MOVQ to double register to ensure register allocator handles correctly.

Modified Paths:
--------------
    rvmroot/trunk/rvm/src-generated/opt-burs/ia32/IA32_SSE2.rules

Modified: rvmroot/trunk/rvm/src-generated/opt-burs/ia32/IA32_SSE2.rules
===================================================================
--- rvmroot/trunk/rvm/src-generated/opt-burs/ia32/IA32_SSE2.rules	2007-10-25 10:17:33 UTC (rev 13830)
+++ rvmroot/trunk/rvm/src-generated/opt-burs/ia32/IA32_SSE2.rules	2007-10-26 23:37:56 UTC (rev 13831)
@@ -278,23 +278,27 @@
 stm:	LONG_ASTORE(LONG_ALOAD(riv, riv), OTHER_OPERAND(riv, riv))
 40
 EMIT_INSTRUCTION
-EMIT(MIR_Move.mutate(PL(p), IA32_MOVQ, ALoad.getResult(PL(p)), MO_AL(PL(p), QW_S, QW))); \
-EMIT(MIR_Move.mutate(P(p), IA32_MOVQ, MO_AS(P(p), QW_S, QW), AStore.getValue(P(p))));
+OPT_RegisterOperand temp = regpool.makeTemp(VM_TypeReference.Double); \
+EMIT(MIR_Move.mutate(PL(p), IA32_MOVQ, temp, MO_AL(PL(p), QW_S, QW))); \
+EMIT(MIR_Move.mutate(P(p), IA32_MOVQ, MO_AS(P(p), QW_S, QW), temp.copyRO()));
 
 stm:	LONG_ASTORE(LONG_LOAD(riv, riv), OTHER_OPERAND(riv, riv))
 40
 EMIT_INSTRUCTION
-EMIT(MIR_Move.mutate(PL(p), IA32_MOVQ, Load.getResult(PL(p)), MO_L(PL(p), QW))); \
-EMIT(MIR_Move.mutate(P(p), IA32_MOVQ, MO_AS(P(p), QW_S, QW), AStore.getValue(P(p))));
+OPT_RegisterOperand temp = regpool.makeTemp(VM_TypeReference.Double); \
+EMIT(MIR_Move.mutate(PL(p), IA32_MOVQ, temp, MO_L(PL(p), QW))); \
+EMIT(MIR_Move.mutate(P(p), IA32_MOVQ, MO_AS(P(p), QW_S, QW),temp.copyRO()));
 
 stm:	LONG_STORE(LONG_ALOAD(riv, riv), OTHER_OPERAND(riv, riv))
 40
 EMIT_INSTRUCTION
-EMIT(MIR_Move.mutate(PL(p), IA32_MOVQ, ALoad.getResult(PL(p)), MO_AL(PL(p), QW_S, QW))); \
-EMIT(MIR_Move.mutate(P(p), IA32_MOVQ, MO_S(P(p), QW), AStore.getValue(P(p))));
+OPT_RegisterOperand temp = regpool.makeTemp(VM_TypeReference.Double); \
+EMIT(MIR_Move.mutate(PL(p), IA32_MOVQ, temp, MO_AL(PL(p), QW_S, QW))); \
+EMIT(MIR_Move.mutate(P(p), IA32_MOVQ, MO_S(P(p), QW), temp.copyRO()));
 
 stm:	LONG_STORE(LONG_LOAD(riv, riv), OTHER_OPERAND(riv, riv))
 40
 EMIT_INSTRUCTION
-EMIT(MIR_Move.mutate(PL(p), IA32_MOVQ, Load.getResult(PL(p)), MO_L(PL(p), QW))); \
-EMIT(MIR_Move.mutate(P(p), IA32_MOVQ, MO_S(P(p), QW), AStore.getValue(P(p))));
+OPT_RegisterOperand temp = regpool.makeTemp(VM_TypeReference.Double); \
+EMIT(MIR_Move.mutate(PL(p), IA32_MOVQ, temp, MO_L(PL(p), QW))); \
+EMIT(MIR_Move.mutate(P(p), IA32_MOVQ, MO_S(P(p), QW), temp.copyRO()));


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