Re: [Iverilog-devel] iverilog bug: module output treated as input

[Martin W. <mai...@ma...>]

Hi Stephan,

Stephan Boettcher wrote:
>
> Hi Martin, hi Itzok,
>
> thanks, ...
>
> Martin Whitaker <mai...@ma...> writes:
>
>> Yes, the simulator's behaviour is correct. The relevant sentence is in section
>> 12.3.8 of the 1364-2005 standard:
>>
>> "A port that is declared as input (output) but used as an output (input) or
>> inout may be coerced to inout. If not coerced to inout, a warning has to be
>> issued."
>
> A warning in not mandatory, because the port was coerced?
>
Yes, that's how I read it, and I know Verilog-XL and NC-Verilog don't generate 
a warning for this. But I agree with Steve and Cary, we should make Icarus 
generate a warning - anything that causes a synthesis vs. simulation mismatch 
is worthy of a warning. If nobody else volunteers, I'll see what I can do.

Martin