Re: [Iverilog-devel] Second piece of string code to test on other simulators

[Iztok J. <izt...@gm...>]

Hi Cary,

Here are the results with the error code commented out.

Regards,
Iztok Jeras


$ irun -sv test.v
irun: 12.10-p001: (c) Copyright 1995-2012 Cadence Design Systems, Inc.
file: test.v
module worklib.top:v
errors: 0, warnings: 0
Caching library 'worklib' ....... Done
Elaborating the design hierarchy:
Top level design units:
top
Building instance overlay tables: .................... Done
Generating native compiled code:
worklib.top:v <0x78b64363>
streams:   1, words:  1078
Loading native compiled code:     .................... Done
Building instance specific data structures.
Design hierarchy summary:
         Instances  Unique
Modules:         1       1
Initial blocks:  1       1
Writing initial simulation snapshot: worklib.top:v
Loading snapshot worklib.top:v .................... Done
ncsim> source /tools/opt/cadence/INCISIV12.10.003/tools/inca/files/ncsimrc
ncsim> run
3:    -:
4: -:
ncsim: *W,RNQUIE: Simulation is complete.
ncsim> exit




On Wed, Oct 17, 2012 at 5:05 PM, Cary R. <cy...@ya...> wrote:

> Thanks Iztok,
>
> I kind of expected that the first three test would fail, but what about
> this part of my email?
>
>
> If the 0 - 2 tests fail with an error then please note that and then
> comment them out so I can see the output from the other tests.
>
> Cary
>
>   ------------------------------
> *From:* Iztok Jeras <izt...@gm...>
> *To:* Cary R. <cy...@ya...>; Discussions concerning Icarus Verilog
> development <ive...@li...>
> *Sent:* Wednesday, October 17, 2012 5:26 AM
> *Subject:* Re: [Iverilog-devel] Second piece of string code to test on
> other simulators
>
> $ irun -sv test.v
> irun: 12.10-p001: (c) Copyright 1995-2012 Cadence Design Systems, Inc.
> file: test.v
> module worklib.top:v
>  errors: 0, warnings: 0
> Caching library 'worklib' ....... Done
> Elaborating the design hierarchy:
>  Top level design units:
> top
> Building instance overlay tables: ....................
>     $display("0:%s-",, ":");         // See above
>                    |
> ncelab: *E,NULFMA (./test.v,17|19): NULL argument supplied to (%s).
>     $display("1:%s-", `null1, ":");  // See above
>                    |
> ncelab: *E,NULFMA (./test.v,18|19): NULL argument supplied to (%s).
>     $display("2:%s-", `null2, ":");  // See above
>                    |
> ncelab: *E,NULFMA (./test.v,19|19): NULL argument supplied to (%s).
>  Done
> irun: *E,ELBERR: Error during elaboration (status 1), exiting.
>
>
>
>
>
>
> On Wed, Oct 17, 2012 at 1:03 AM, Cary R. <cy...@ya...> wrote:
>
> Here is a second piece of Verilog code that tests more corners of how
> strings are printed. Can I please get the output from other simulators. I
> have added comments with my understanding of the standard and what I expect
> to be output. The Icarus development git head code currently gets all the S
> tests and the 4 test correct. The patch I have to fix the problem discussed
> last week breaks tests 4 and S1-2 which I believe is really a compiler bug
> that was hidden by the run time bug.
>
>
> I can describe this in more detail if needed.
>
> If the 0 - 2 tests fail with an error then please note that and then
> comment them out so I can see the output from the other tests.
>
> Thanks
>
> Cary
>
>
> module top;
>
> `define null1 // null
> `define null2
> `define null3 0
> `define null4 ""
>
>   initial begin
>     /* The standard says an argument shall follow the %s. Some of these
>      * have a NULL argument after the %s and I would expect that to at
>      * least emit a warning message and treat the missing argument as an
>      * empty string. It is also possible that the adjacent commas would
>      * produce a space after the dash. */
>     /* I expect the first three lines to produce a warning or an error and
>      * if it is a warning to display either no spaces or a single space
>      * after the dash (e.g. "0:-:" or "0:- :). */
>     $display("0:%s-",, ":");         // See above
>     $display("1:%s-", `null1, ":");  // See above
>     $display("2:%s-", `null2, ":");  // See above
>     $display("3:%s-", `null3, ":");  // I expect "3:    -:" (32 bit
> integer)
>     $display("4:%s-", `null4, ":");  // I expect "4:-:"
>     /* Icarus can display the macro as a string. */
> `ifdef __ICARUS__
>     $display("S1:%s:", ``null1);  // I expect "S1::" (an empty string)
>     $display("S2:%s:", ``null2);  // I expect "S2::" (an empty string)
>     $display("S3:%s:", ``null3);  // I expect "S3:0:"
>     $display("S4:%s:", ``null4);  // I expect "S4:"":"
> `endif
>   end
> endmodule
>
>
>
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