[Iverilog-devel] Xilinx IP Cores

[John O B. <job...@gm...>]

-------- Original Message --------
Subject: Xilinx IP Cores
Date: Mon, 29 Aug 2011 20:46:32 -0700
From: John O Battle <job...@gm...>
Reply-To: job...@e6...
Organization: The E6B Group
To: ive...@li...

Hi

I have been using Xilinx ISE from the command line and have pretty well
figured out how to convert schematics to verilog, how to use the Xilinx
back end etc and now I want to replace xst with iVerilog.  However when
I try to compile my verilog files with iVerilog, I get errors like this:

synth.v:46: error: Unknown module type: BUFG
synth.v:48: error: Unknown module type: IBUFG
synth.v:50: error: Unknown module type: BUFG
synth.v:52: error: Unknown module type: DCM_SP
s3e_top.v:104: error: Unknown module type: GND

These errors all seem to be related to either gate core or ground.  I'm
not really sure what is missing.  I think I need to somehow instantiate
the missing cores but I don't know how to do that, or if its even
possible with iverilog.  And I have no idea what is wrong with GND.

I attached most of the relevant files.  Any help would be greatly
appreciated.
-
John O Battle, N4OE/6
2620-B Dove Creek Lane
Pasadena, CA 91107 USA
GPS:34.1738N 118.0960W
626-709-6208 (g)
626-407-1409 (c)
626-296-3237 (h)
Tail: N6208G
job...@gm...
job...@e6...