Re: [Iverilog-devel] Some code to test.

[Cary R. <cy...@ya...>]

I was assuming at a minimum, we would have a warning that said unsized constant 
in concatenation was converted to xx bits. Though we are going to need more 
discussion before I propose changing anything. Since Icarus allows greater than 
32 bit constants we can't just hard code the message to 32 bits. I agree that 
only sized constants should be allowed, but since all the other simulators 
appear to support this we may not have a choice.

Cary



----- Original Message ----
From: Martin Whitaker <mai...@ma...>
To: ive...@li...
Sent: Wed, April 20, 2011 12:30:35 PM
Subject: Re: [Iverilog-devel] Some code to test.

Steve's justification for the Icarus behaviour is here:

http://iverilog.wikia.com/wiki/Verilog_Portability_Notes#Unsized_Expressions_as_Arguments_to_Concatenation


On the whole I agree with him. At the very least I'd like to have a warning 
message.

The problem is that the standard is inconsistent. In section 5.1.14 it says:

"Unsized constant numbers shall not be allowed in concatenations. This is 
because the 

size of each operand in the concatenation is needed to calculate the complete 
size of 

the concatenation."

But then in table 5-22 it states that the bit length of an unsized constant is 
the 

same as that of an integer.

Martin

On 20/04/11 18:06, Cary R. wrote:
> While running some regression tests on Icarus using designs originally from
> opencores I ran across an issues that I need more information to know which 
way
> it should be handled. Icarus will not compile the attached code since it has 
an
> unsized constant, but veriwell and GPL cver both think the unsized number is 
32
> bit which is likely an acceptable interpretation as well. The issue is that 
>from
> the code it appears that the original author thought the addition would 
produce
> an 8 bit result. Here is the equation, {8'h7D, (i[7:0] + 1)}, it is being
> assigned to a 16 bit register.
>
> I'm interest to know if this compiles without error/warning and if it does
> compile is the one treated as 8 or 32 bits. The Verilog code should handle all
> this, so I just need simulation results.
>
> Thanks,
>
> Cary
>
>
>
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