Re: [Iverilog-devel] How to debug when simulation hangs

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I'm working on a new opcode for vvp that will print file, line and an optional description string to stderr. Once this is done we'll need to insert these as appropriate to get good debug coverage. This opcode only works with procedural statement. Continuous assignments need some other type of code. I think I'm also going to automatically add some other debug information when these opcodes are found (denote time change, etc.).

Cary

--- On Fri, 2/25/11, Stephen Williams <st...@ic...> wrote:

> From: Stephen Williams <st...@ic...>
> Subject: Re: [Iverilog-devel] How to debug when simulation hangs
> To: "Discussions concerning Icarus Verilog development" <ive...@li...>
> Date: Friday, February 25, 2011, 9:30 AM
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> 
> Burried deep in the vvp implementation is support for event
> tracing,
> which could in principle be used to put together time-0
> loop detection
> and other debug tasks. One way to manually deal with this
> is to use
> the interactive mode (Ctrl-C after you're in your loop and
> you'll get
> an interactive prompt) and use the "step" command to step
> events.
> 
> This feature is not fully fleshed out, so I'd be delighted
> if someone
> offers some patches to improve it. I'm currently pretty
> overwhelmed
> with day-job and some specific Icarus Verilog tasks of my
> own, but
> this problem has come up before, so tools to deal with it
> would be
> of value.
> 
> On 02/25/2011 09:23 AM, Cary R. wrote:
> > Yes, those system tasks are not implemented. I was
> hoping Steve would comment on 
> > this, but if he doesn't I'll try to look at what is
> available over the weekend.
> > 
> > Implementing these system tasks is likely tricky, but
> if you feel up to the 
> > challenge then please proceed. To do this correctly we
> probably need to insert a 
> > new opcode that contains the file and line number
> information instead of adding 
> > this to the raw commands. The advantage with this
> approach is that the debug 
> > information is only in the command stream when needed
> and it allows multiple vvp 
> > statements to be grouped back to the original
> statement. The vlog95 back end 
> > rebuilds some of the statements the compiler splits up
> and the vvp back end 
> > often adds even more statements per original line.
> Both of these will need to be 
> > looked at to understand where a statement really
> starts.
> > 
> > FYI, while working on the vlog95 back end I have
> verified that most of the 
> > objects have file/line information and that it is
> mostly correct, so we should 
> > have good information to work with.
> > 
> > Cary
> > 
> > 
> > 
> > ----- Original Message ----
> > From: Markus Lavin <mar...@gm...>
> > To: Discussions concerning Icarus Verilog development
> 
> > <ive...@li...>
> > Sent: Fri, February 25, 2011 12:50:11 AM
> > Subject: Re: [Iverilog-devel] How to debug when
> simulation hangs
> > 
> > Thanks for the comments. So I will try to enable line
> tracing to
> > figure out where my zero-time loop is.However I can't
> seem to find any
> > way to enable this sort of tracing, e.g. the
> $settrace/$setevtrace
> > system tasks do not seem to be present and I couldn't
> find any command
> > line options for this either.
> > 
> > If there is no support for this currently would it
> then maybe be
> > possible for me to implement a $settrace task myself
> via VPI?
> > 
> > Again, thanks for your help!
> > 
> > /Markus
> > 
> > 
> > 2011/2/25 Cary R. <cy...@ya...>:
> >> The comments from Guy are good. I thought Steve
> added some code to help with
> >> this, but I didn't notice it in a quick scan of
> the vvp directory. The
> >> interactive mode (^C) and then some poking may
> also help. I have hacked the
> >> event queue before to figure out what is going on,
> but that's somewhat
> >> complicated.
> >>
> >> Cary
> >>
> >>
> >>
> >> ----- Original Message ----
> >> From: Markus Lavin <mar...@gm...>
> >> To: ive...@li...
> >> Sent: Thu, February 24, 2011 2:54:52 AM
> >> Subject: [Iverilog-devel] How to debug when
> simulation hangs
> >>
> >> Hi,
> >>
> >> I have some problems running iverilog on a design.
> The problem is that
> >> simulation hangs (i.e. time stops) on certain test
> cases (the design
> >> is a CPU). The same design synthesizes with xilinx
> ise and simulates
> >> well with other simulators like e.g. cver. I am
> guessing that I am
> >> doing something stupid here but I would very much
> appreciate some
> >> hints on how I can debug this problem. E.g. when I
> see that time has
> >> stopped is there any special data structures that
> I can look at in gdb
> >> to determine what part of my design is causing the
> problems or how
> >> should I go about this issue?
> >>
> >> BR
> >> /Markus
> >>
> >>
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