Re: [Iverilog-devel] Brainstorming Support for VHDL

[Steven W. <Ste...@ta...>]

  I all - haven't posted for a long time -

Steve,  I would like to put a feature request in if possible.  IF you 
are essentially going to be translating into a verilog like equivalent.  
Is it possible to have the option of printing out the verilog equivalent 
on your way to code generation?  I realize this would duplicate some of 
the vhd2vl functionality.  However, if you get to the point where you 
are handling more stuff than vhd2vl does, we have a more capable tool 
.   I know that the times I've tried to use these tools (and 
Veritakwin's VHDL to verilog convertor) that packages and type 
conversions are killers.

Thanks for letting me put my two cents worth in.

Steve Wilson

On 10/18/2010 12:22 AM, Nick Gasson wrote:
> On 17/10/10 20:40, Larry Doolittle wrote:
>> 90% of the intended use cases are already covered by vhd2vl.
>> People's (including Steve's customers) interest in VHDL generally involves
>> synthesizable code, not test benches.  The trick to bounding this
>> problem IMHO is to handle the easy (and actually used) stuff cleanly,
>> and bomb with a clear error message when faced with the weird stuff
>> that triggers Evan's long list of corner cases and worse.
>>
> That seems like a very sensible strategy - there are a lot of esoteric
> features in VHDL that are rarely used. OpenCores is potentially a good
> source of "real world" VHDL examples.
>
> Another thing that might be tricky is that VHDL has a different
> compilation model to Verilog - e.g. units can be compiled into
> libraries. I'm not sure how easy this would be to implement in a
> preprocessor.
>
> As far as I know there is no open source mixed-language simulator
> available so this is a pretty exciting project. I'm keen to help out if
> I can!
>
>
> Nick
>
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