From: Larry D. <ldo...@re...> - 2010-04-29 17:45:35
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Hi - I'm fussing with vhd2vl again. There is a VHDL construct that I have trouble figuring out how to represent in Verilog. Ports can have default values. Here's an example taken from the wild: component gh_uart_16550 is port( clk : in std_logic; BR_clk : in std_logic; rst : in std_logic; CS : in std_logic; WR : in std_logic; ADD : in std_logic_vector(2 downto 0); D : in std_logic_vector(7 downto 0); sRX : in std_logic; CTSn : in std_logic := '1'; -- Look at me! DSRn : in std_logic := '1'; RIn : in std_logic := '1'; DCDn : in std_logic := '1'; sTX : out std_logic; DTRn : out std_logic; RTSn : out std_logic; OUT1n : out std_logic; OUT2n : out std_logic; TXRDYn : out std_logic; RXRDYn : out std_logic; IRQ : out std_logic; B_CLK : out std_logic; RD : out std_logic_vector(7 downto 0) ); end component; If I just ignore all those ":= '1'"s, at least iverilog will throw a warning when someone tries to take the default by not connecting that port. If I were really committed, I could try to keep track of the defaults myself and fill them in when the module is instantiated. That sounds like a lot of work. Any other ideas? - Larry P.S. My changelog so far is: * add array (not well tested) * add octal strings (O"777") * add one more "rem" * accept constants and bit ranges in port mappings * accept a single un-named generic map item * accept conv_integer function, treated as a no-op If any of you have (relatively simple) pet VHDL constructs you want added, now is a good time to ask. |