Re: [Iverilog-devel] Run a test?

[Jared C. <jar...@gm...>]

2010/4/27 Stephen Williams <st...@ic...>:
> OK, the attached test is an issue I encountered while fixing some
> bit width issues. The behavior of the code in foo2.vl (attached)
> is a really weird consequence of the expression width rules--weird
> enough that I'd like to double check my understanding with some
> other compilers. So can anybody with access with other Verilog
> simulators try out the attached program? Thanks.

You make it too easy to procrastinate. :)

Indeed, all three that I have give "PASSED".  Interesting.

Jared