Re: [Iverilog-devel] Compilation errors when using Icarus Verilog

[Cary R. <cy...@ya...>]

--- On Wed, 12/2/09, Nicholas Kinar <n....@us...> wrote:

> Argh! - Thank you so much for your response, Stephen. 
> I can't believe
> that I missed that simple little endmodule.

Icarus is trying to tell you what you did wrong. The problem
is that you did not understand what it was saying. The following
warning was triggered at the module statement in dac.v. Icarus is
saying that you are either trying to nest this module inside
another module or you have forgotten an endmodule some where.
I'm guessing you know you can't nest modules, so the missing
endmodule part applies.

> dac.v:2: error: missing endmodule or attempt to nest modules.

It then goes on to tell you that what it thinks is the current
module was started in signal.v, line 5. This should immediately
make you think that you probably forgot the closing endmodule
for that module definition and yes, that's exactly what happened.

> signal.v:5: error: original module (signal) defined here.

The rest of the messages are cause by this original mistake.
It is always best to look at the first few messages and exact
line numbers that Icarus prints to understand the base problem.
At times it tries to do too much, but that is helpful at times
to, so it is a trade off. The trick is read the messages and
figure out what they are telling you.

Good luck,

Cary