Re: [Iverilog-devel] Compilation errors when using Icarus Verilog

[Nicholas K. <n....@us...>]

Argh! - Thank you so much for your response, Stephen.  I can't believe 
that I missed that simple little endmodule.  Yes, after adding the 
endmodule, I get a number of more "normal" errors.  Time to move on to 
"productive" debugging.

We've probably all made this type of mistake before.  Your observation 
saved me plenty of grief, and so thank you so much for your help!


Nicholas


P.S. And thank you for making Icarus.  It is a great tool, and I don't 
know what I would do without it!


Stephen Williams wrote:
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> Nicholas Kinar wrote:
>
>   
>> dac.v:2: syntax error
>> dac.v:2: error: missing endmodule or attempt to nest modules.
>> signal.v:5: error: original module (signal) defined here.
>> dac.v:13: error: port rst already has a port declaration.
>> signal.v:41: error: Port ``rst'' has already been declared a port.
>> dac.v:14: error: port clk already has a port declaration.
>> signal.v:15: error: Port ``clk'' has already been declared a port.
>> dac.v:15: error: port load_word is not in the port list.
>> dac.v:17: error: port msb_data is not in the port list.
>> dac.v:18: error: port lsb_data is not in the port list.
>>
>>
>> Strangely enough, it appears that dac.v contains a module-endmodule 
>> block, and that load_word, msb_data, and lsb_data are in the port list.  
>> What am I doing wrong with this code, and why won't iverilog compile it?
>>     
>
> The endmodule is missing from your "signal" module.
>
> - --
> Steve Williams                "The woods are lovely, dark and deep.
> steve at icarus.com           But I have promises to keep,
> http://www.icarus.com         and lines to code before I sleep,
> http://www.picturel.com       And lines to code before I sleep."
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