Re: [Iverilog-devel] Too much memory usage when compling big netlist

[Bruce C. <bru...@gm...>]

> (You are doing this off git master, right?)
Yes. I am re-writing most part of the compiler so that I can compile
one of my school project.
In fact, I am planning  to re-write Icarus Compiler into a stand-alone
Verilog compiler library, with
rich API functions. These functions may even allow user to modify their design.
In order to do this, I am trying to re-construct my netlist data
structure, hoping to be more
effecient in memory and speed.

As you know, I am still re-writing the tgt-verilog code. And the new
tgt-verilog code would
re-construct design into my new netlist data structure. So the API
functions that I have
developed for my school project can be used by Icarus users as well.

> So first try the easy changes first, and even submit patches to the git master branch.
I am planning to do some big change first, because my project plan is
in a hurry.
After my school project, I think I would get a much clear
understanding of Icarus Compiler
code, and I would be more clear on what solution would be the best and
easiest to save
memory and improve compilation speed. Then I will be ready to do some
modification to
git master branch.


Bruce
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