[Iverilog-devel] Signal dumping pragmas

[Williams T. <pha...@gm...>]

Steve/Cary,

Does Icarus Verilog have any way to allow a coder to specify which  
signals should be excluded from dumping (without specifically  
specifying signal names in a $dumpvars call?  For example, if I have  
the following module:

module foo(...);

reg a;
reg b, c, d, e, f;

...

endmodule

I would like to have registers b, c, d, e and f be dumped but I would  
like to exclude register "a" from every being dumped.  A pragma such  
as the following:

module foo(...);

/* icarus trace_off */
reg a;
/* icarus trace_on */
reg b, c, d, e, f;

...

endmodule


would allow one to control this sort of dumping specification.

I know that Verilator has such a pragma and I was wondering (if it  
does not already exist) if IV could contain such a feature as well?

Any thoughts?

Thanks,
Trevor