Re: [Iverilog-devel] timescale warning too dumb?

[Cary R. <cy...@ya...>]

--- On Mon, 2/23/09, Stephen Williams <st...@ic...> wrote:

> I think that is indeed the case: Icarus Verilog only starts
> warning after it sees the first `timescale directive.

I think you missed Laryy's point. He said delay specification
not timescale. I basically agree with Larry on this and I was
thinking that we need code like this to effectively warn about
the bug/request in pr2590274. So if you don't have a delay
construct in a file we don't care about the timescale
information (inherited or not) and it should be safe to simply
omit it.

Cary