From: Cary R. <cy...@ya...> - 2008-12-14 16:40:51
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--- On Sun, 12/14/08, Martin Whitaker <mai...@ma...> wrote: > But then I generally write synthesisable code, so > I would > never use anything other than a pure function in a > continuous > assignment. Cary clearly uses Verilog quite differently > from me, so > may have a different opinion. It's my test suites and what I need to model in them that gets a little different. The only thing I'm really interested in for this is the time functions. > That a user function does not have to be a pure function. > See the > example below. Maybe we can get someone who has access to the big three simulators to test this and see what they return. Looking for implicit inputs seems like a stretch, but I have been surprised before. I would say that for now we need a .sfunc/t that takes an event trigger which is all the other inputs in the CA. Should this be .sfunc/e? It may be more consistent with the other vvp opcodes. The new .sfunc is only used for zero argument functions, except the random functions are prohibited. We also need checks in the normal .sfunc section to prohibit some of the other standard system functions (random, IO, etc.) I think this is a complete description of work. Cary |