[Iverilog-devel] VHDL code generator update

[Nick G. <nm...@yo...>]

Hi all,

The VHDL code generator now passes about 25% (270-ish tests) of the IVL 
regression suite. Most of the basic synthesisable features are now 
translated correctly, and some of the more advanced language features 
work too.

It's now possible to use the code generator on some non-trival Verilog 
code. As an example this is the output of the code generator when run on 
the I2C controller module from 
http://www.opencores.org/cvsweb.shtml/i2c/rtl/verilog/ : 
http://www.nickg.me.uk/~nick/i2c/i2c.vhd

The test bench, unfortunately, cannot be translated as it makes 
extensive use of hierarchical referencing, which has no equivalent in 
VHDL. However, the the VHDL does compile and initialise with no compile 
or run-time errors. I will also try to synthesise it when I have the chance.

What's interesting about this particular controller is that is has a 
manually written VHDL translation, for comparison, at: 
http://www.opencores.org/cvsweb.shtml/i2c/rtl/vhdl/
The two are fairly similar (structurally at least), although the 
automatically translated one is somewhat more verbose, and parts of the 
output could be optimised -- especially things like 
To_Integer(signed'("00")).

A few Verilog features (currently the reduction operators), which are 
tricky to implement `in-line' in VHDL are currently implemented by a 
package Verilog_Support (e.g. the OR reduction operator is implemeted by 
a Reduce_OR function). The idea is that this package would be shipped 
with the code generator, and the user would have to compile it alongside 
the generated output. Does this seem reasonable? An alternative might be 
to copy the complete contents into the generated output file (saving the 
need to compile two files), or to add function definitions to the 
generated architectures only if needed (so the Reduce_OR function would 
be pasted in only if that operator were used in the module).


Nick