iverilog-devel — Conversations on matters of Icarus Verilog development

[Iverilog-devel] Parallalization with GPU

[Arun P <aru...@gm...>]

Hi All,

This is Arun. I am trying to speed up Icarus Verilog with GPU parallel
processing for my academic project. I am looking for help . Which source
file I should start looking at or which part will be suitable to off-load
to GPU ? I am totally clueless. Please share your thoughts.

Thanks,
Arun.

Re: [Iverilog-devel] Some Sample SystemVerilog programs

[Stephen W. <st...@ic...>]

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1

On 02/18/2014 02:13 AM, Iztok Jeras wrote:
> The 'sv_unpacked_port.sv <http://sv_unpacked_port.sv>' needed some
> more changes. Array sizes where only the size [width-1], not the
> range [width-1:0] are specified, are only allowed for the unpacked 
> part of the array, so on the right side. Also the address was
> missing from the list in the display line. I did not check the
> intention of the test.

OK, The sv_unpacked_port.sv test needed more work, so I've attached
an update. This should fix it, and it should display "PASSED".

Thanks for running these tests.
- -- 
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."
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Re: [Iverilog-devel] Some Sample SystemVerilog programs

[Iztok J. <izt...@gm...>]

The 'sv_typedef_scope.sv' issue was a trivial typo. The 'sv_unpacked_port.sv'
needed some more changes. Array sizes where only the size [width-1], not
the range [width-1:0] are specified, are only allowed for the unpacked part
of the array, so on the right side. Also the address was missing from the
list in the display line. I did not check the intention of the test.
Updated test files are attached, so you can check the diff.

Regards,
Iztok Jeras

$ irun sv_typedef_scope.sv
irun: 13.10-s014: (c) Copyright 1995-2014 Cadence Design Systems, Inc.
file: sv_typedef_scope.sv
    module worklib.main:sv
        errors: 0, warnings: 0
        Caching library 'worklib' ....... Done
    Elaborating the design hierarchy:
    Top level design units:
        $unit_0x3fdf4418
        main
    Building instance overlay tables: .................... Done
    Generating native compiled code:
        worklib.main:sv <0x5a44e65c>
            streams:   1, words:  1444
    Building instance specific data structures.
    Loading native compiled code:     .................... Done
    Design hierarchy summary:
                    Instances  Unique
        Modules:            1       1
        Registers:          1       1
        Initial blocks:     1       1
        Compilation units:  1       1
    Writing initial simulation snapshot: worklib.main:sv
Loading snapshot worklib.main:sv .................... Done
ncsim> source /tools/opt/cadence/INCISIV13.10.014/tools/inca/files/ncsimrc
ncsim> run
PASSED
ncsim: *W,RNQUIE: Simulation is complete.
ncsim> exit



$ irun sv_unpacked_port.sv
irun: 13.10-s014: (c) Copyright 1995-2014 Cadence Design Systems, Inc.
file: sv_unpacked_port.sv
    module worklib.test:sv
        errors: 0, warnings: 0
    module worklib.main:sv
        errors: 0, warnings: 0
        Caching library 'worklib' ....... Done
    Elaborating the design hierarchy:
    Top level design units:
        main
    Building instance overlay tables: .................... Done
    Generating native compiled code:
        worklib.main:sv <0x1e933575>
            streams:   3, words:  2672
        worklib.test:sv <0x6e825af1>
            streams:   2, words:   349
    Building instance specific data structures.
    Loading native compiled code:     .................... Done
    Design hierarchy summary:
                     Instances  Unique
        Modules:             2       2
        Registers:           5       5
        Scalar wires:        1       -
        Vectored wires:      3       -
        Always blocks:       1       1
        Initial blocks:      1       1
        Pseudo assignments:  2       2
    Writing initial simulation snapshot: worklib.main:sv
Loading snapshot worklib.main:sv .................... Done
ncsim> source /tools/opt/cadence/INCISIV13.10.014/tools/inca/files/ncsimrc
ncsim> run
FAILED -- data[1]==01, Q==00
Simulation complete via $finish(1) at time 4 NS + 0
./sv_unpacked_port.sv:41         $finish;
ncsim> exit



On Tue, Feb 18, 2014 at 11:02 AM, Iztok Jeras <izt...@gm...> wrote:

> $ irun sv_for_variable.sv
> irun: 13.10-s014: (c) Copyright 1995-2014 Cadence Design Systems, Inc.
> file: sv_for_variable.sv
>     program worklib.main:sv
>         errors: 0, warnings: 0
>         Caching library 'worklib' ....... Done
>     Elaborating the design hierarchy:
>     Top level design units:
>         main
>     Building instance overlay tables: .................... Done
>     Generating native compiled code:
>         worklib.main:sv <0x0d85b4f9>
>             streams:   1, words:   900
>     Building instance specific data structures.
>     Loading native compiled code:     .................... Done
>     Design hierarchy summary:
>                  Instances  Unique
>         Programs:        1       1
>         Registers:       3       3
>         Initial blocks:  1       1
>     Writing initial simulation snapshot: worklib.main:sv
> Loading snapshot worklib.main:sv .................... Done
> ncsim> source /tools/opt/cadence/INCISIV13.10.014/tools/inca/files/ncsimrc
> ncsim> run
> PASSED
> Simulation complete via implicit call to $finish(1) at time 0 FS + 1
> ./sv_for_variable.sv:2 program main;
> ncsim> exit
>
>
> $ irun sv_typedef_scope.sv
> irun: 13.10-s014: (c) Copyright 1995-2014 Cadence Design Systems, Inc.
> file: sv_typedef_scope.sv
>     module worklib.main:sv
>         errors: 0, warnings: 0
>         Caching library 'worklib' ....... Done
>     Elaborating the design hierarchy:
>     Top level design units:
>         $unit_0x3fdf4418
>         main
>       if (foo.log_x !== 3'b000) begin
>                   |
> ncelab: *E,CUVUNF (./sv_typedef_scope.sv,35|18): Hierarchical name
> component lookup failed at 'log_x'.
> irun: *E,ELBERR: Error during elaboration (status 1), exiting.
>
>
> $ irun sv_unpacked_port.sv
> irun: 13.10-s014: (c) Copyright 1995-2014 Cadence Design Systems, Inc.
> file: sv_unpacked_port.sv
>     module worklib.test:sv
>         errors: 0, warnings: 0
>    logic [width-1] data [0:3];
>                  |
> ncvlog: *E,SVPKSN (sv_unpacked_port.sv,21|17): The single-bound form of a
> range is only allowed for array (i.e., unpacked) dimensions.
>    wire [width-1]  Q;
>                 |
> ncvlog: *E,SVPKSN (sv_unpacked_port.sv,23|16): The single-bound form of a
> range is only allowed for array (i.e., unpacked) dimensions.
>     module worklib.main:sv
>         errors: 2, warnings: 0
> irun: *E,VLGERR: An error occurred during parsing.  Review the log file
> for errors with the code *E and fix those identified problems to proceed.
> Exiting with code (status 1).
>
>
> I will try to fix the code if the errors are obvious.
>
> Regards,
> Iztok Jeras
>
>
> On Tue, Feb 18, 2014 at 5:17 AM, Stephen Williams <st...@ic...>wrote:
>
>> -----BEGIN PGP SIGNED MESSAGE-----
>> Hash: SHA1
>>
>>
>> Hi all,
>>
>> I'm looking at some more SystemVerilog features, and I would like
>> to check some test programs with some Big-3 simulators to make
>> sure I really am understanding things correctly. I've attached
>> the example that I'm planning to make work. Can someone send me
>> results from some other tools?
>>
>> Thanks,
>>
>> - --
>> Steve Williams                "The woods are lovely, dark and deep.
>> steve at icarus.com           But I have promises to keep,
>> http://www.icarus.com         and lines to code before I sleep,
>> http://www.picturel.com       And lines to code before I sleep."
>> -----BEGIN PGP SIGNATURE-----
>> Version: GnuPG v2.0.19 (GNU/Linux)
>> Comment: Using GnuPG with Thunderbird - http://www.enigmail.net/
>>
>> iEYEARECAAYFAlMC3tUACgkQrPt1Sc2b3im1nwCcCestQvk+jMeQEpqPDPKGbyJB
>> fQMAn0DnI3sx2wvHyvW6u98e0vabcMNb
>> =Wa0G
>> -----END PGP SIGNATURE-----
>>
>>
>> ------------------------------------------------------------------------------
>> Managing the Performance of Cloud-Based Applications
>> Take advantage of what the Cloud has to offer - Avoid Common Pitfalls.
>> Read the Whitepaper.
>>
>> http://pubads.g.doubleclick.net/gampad/clk?id=121054471&iu=/4140/ostg.clktrk
>> _______________________________________________
>> Iverilog-devel mailing list
>> Ive...@li...
>> https://lists.sourceforge.net/lists/listinfo/iverilog-devel
>>
>>
>

Re: [Iverilog-devel] Some Sample SystemVerilog programs

[Iztok J. <izt...@gm...>]

$ irun sv_for_variable.sv
irun: 13.10-s014: (c) Copyright 1995-2014 Cadence Design Systems, Inc.
file: sv_for_variable.sv
    program worklib.main:sv
        errors: 0, warnings: 0
        Caching library 'worklib' ....... Done
    Elaborating the design hierarchy:
    Top level design units:
        main
    Building instance overlay tables: .................... Done
    Generating native compiled code:
        worklib.main:sv <0x0d85b4f9>
            streams:   1, words:   900
    Building instance specific data structures.
    Loading native compiled code:     .................... Done
    Design hierarchy summary:
                 Instances  Unique
        Programs:        1       1
        Registers:       3       3
        Initial blocks:  1       1
    Writing initial simulation snapshot: worklib.main:sv
Loading snapshot worklib.main:sv .................... Done
ncsim> source /tools/opt/cadence/INCISIV13.10.014/tools/inca/files/ncsimrc
ncsim> run
PASSED
Simulation complete via implicit call to $finish(1) at time 0 FS + 1
./sv_for_variable.sv:2 program main;
ncsim> exit


$ irun sv_typedef_scope.sv
irun: 13.10-s014: (c) Copyright 1995-2014 Cadence Design Systems, Inc.
file: sv_typedef_scope.sv
    module worklib.main:sv
        errors: 0, warnings: 0
        Caching library 'worklib' ....... Done
    Elaborating the design hierarchy:
    Top level design units:
        $unit_0x3fdf4418
        main
      if (foo.log_x !== 3'b000) begin
                  |
ncelab: *E,CUVUNF (./sv_typedef_scope.sv,35|18): Hierarchical name
component lookup failed at 'log_x'.
irun: *E,ELBERR: Error during elaboration (status 1), exiting.


$ irun sv_unpacked_port.sv
irun: 13.10-s014: (c) Copyright 1995-2014 Cadence Design Systems, Inc.
file: sv_unpacked_port.sv
    module worklib.test:sv
        errors: 0, warnings: 0
   logic [width-1] data [0:3];
                 |
ncvlog: *E,SVPKSN (sv_unpacked_port.sv,21|17): The single-bound form of a
range is only allowed for array (i.e., unpacked) dimensions.
   wire [width-1]  Q;
                |
ncvlog: *E,SVPKSN (sv_unpacked_port.sv,23|16): The single-bound form of a
range is only allowed for array (i.e., unpacked) dimensions.
    module worklib.main:sv
        errors: 2, warnings: 0
irun: *E,VLGERR: An error occurred during parsing.  Review the log file for
errors with the code *E and fix those identified problems to proceed.
Exiting with code (status 1).


I will try to fix the code if the errors are obvious.

Regards,
Iztok Jeras


On Tue, Feb 18, 2014 at 5:17 AM, Stephen Williams <st...@ic...> wrote:

> -----BEGIN PGP SIGNED MESSAGE-----
> Hash: SHA1
>
>
> Hi all,
>
> I'm looking at some more SystemVerilog features, and I would like
> to check some test programs with some Big-3 simulators to make
> sure I really am understanding things correctly. I've attached
> the example that I'm planning to make work. Can someone send me
> results from some other tools?
>
> Thanks,
>
> - --
> Steve Williams                "The woods are lovely, dark and deep.
> steve at icarus.com           But I have promises to keep,
> http://www.icarus.com         and lines to code before I sleep,
> http://www.picturel.com       And lines to code before I sleep."
> -----BEGIN PGP SIGNATURE-----
> Version: GnuPG v2.0.19 (GNU/Linux)
> Comment: Using GnuPG with Thunderbird - http://www.enigmail.net/
>
> iEYEARECAAYFAlMC3tUACgkQrPt1Sc2b3im1nwCcCestQvk+jMeQEpqPDPKGbyJB
> fQMAn0DnI3sx2wvHyvW6u98e0vabcMNb
> =Wa0G
> -----END PGP SIGNATURE-----
>
>
> ------------------------------------------------------------------------------
> Managing the Performance of Cloud-Based Applications
> Take advantage of what the Cloud has to offer - Avoid Common Pitfalls.
> Read the Whitepaper.
>
> http://pubads.g.doubleclick.net/gampad/clk?id=121054471&iu=/4140/ostg.clktrk
> _______________________________________________
> Iverilog-devel mailing list
> Ive...@li...
> https://lists.sourceforge.net/lists/listinfo/iverilog-devel
>
>

[Iverilog-devel] Some Sample SystemVerilog programs

[Stephen W. <st...@ic...>]

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1


Hi all,

I'm looking at some more SystemVerilog features, and I would like
to check some test programs with some Big-3 simulators to make
sure I really am understanding things correctly. I've attached
the example that I'm planning to make work. Can someone send me
results from some other tools?

Thanks,

- -- 
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2.0.19 (GNU/Linux)
Comment: Using GnuPG with Thunderbird - http://www.enigmail.net/

iEYEARECAAYFAlMC3tUACgkQrPt1Sc2b3im1nwCcCestQvk+jMeQEpqPDPKGbyJB
fQMAn0DnI3sx2wvHyvW6u98e0vabcMNb
=Wa0G
-----END PGP SIGNATURE-----

Re: [Iverilog-devel] vec4-stack progress

[Stephen W. <st...@ic...>]

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1


Actually, the %store/vec4a works very much like you suggest
in that message, so the test for 'x' and the jump are folded
into a single instruction.

I think a gprof run will help pin down what is really wrong.
It is probably a matter of some vvp_vector4_t class handling
that is not optimal that this new behavior is triggering.

On 02/14/2014 01:03 PM, Martin Whitaker wrote:
> I was somewhat expecting a performance hit (which is why I checked
> for it!). I'll remind you of this
> 
> http://sourceforge.net/p/iverilog/mailman/message/31240085/
> 
> which could account for a lot of it.
> 
> Martin
> 
> Stephen Williams wrote:
> 
> Woah, that's interesting. (The performance hit, I mean.)
> 
> It is true, though, that some of the translation is simplistic, and
> my expectation is that with some optimization I should be able to
> turn that around. For example, I have done NO profiling yet. There
> are a few tests in the ivtest suite that broke, and I want to
> address those first, but then I want to do some profiles to really
> see what's bad. Honestly, I think I can get it faster than the
> existing mode.
> 
> On 02/14/2014 12:41 PM, Martin Whitaker wrote:
>>>> Running the subset of my production tests that Icarus can
>>>> handle has not exposed any functional bugs. However,
>>>> selecting a moderately sized test, I'm seeing ~32% increase
>>>> in run time and ~10% increase in number of vvp instructions.
>>>> This is too big a performance hit for my liking.
>>>> 
>>>> Martin
>>>> 
>>>> Stephen Williams wrote:
>>>> 
>>>> The vec4-stack branch of Icarus Verilog in the git repository
>>>> is almost complete. I've been merging in updates to master,
>>>> so it has been keeping up with other changes.
>>>> 
>>>> The actual vec4 work is almost complete; there are only a
>>>> few unusual corner cases that are not working, so I think it
>>>> is ready for folks to start trying it out. I'm not going to
>>>> merge it into master until it passes ALL the ivtest tests
>>>> that master current passes (there are a handful that fail)
>>>> but it is really close and I would like to get it out there
>>>> for people to mess with.
>>>> 
>>>>> 
>>>>> ------------------------------------------------------------------------------
>>>>>
>>>>>
>
>>>>> 
Android apps run on BlackBerry 10
>>>>> Introducing the new BlackBerry 10.2.1 Runtime for Android
>>>>> apps. Now with support for Jelly Bean, Bluetooth, Mapview
>>>>> and more. Get your Android app in front of a whole new
>>>>> audience.  Start now. 
>>>>> http://pubads.g.doubleclick.net/gampad/clk?id=124407151&iu=/4140/ostg.clktrk
>>>>>
>>>>>
>
>>>>> 
_______________________________________________
>>>>> Iverilog-devel mailing list
>>>>> Ive...@li... 
>>>>> https://lists.sourceforge.net/lists/listinfo/iverilog-devel
>>>>>
>>>>
>>>>
>>>>
>>>>> 
-
------------------------------------------------------------------------------
>>>> 
>>>> 
> Android apps run on BlackBerry 10
>>>> Introducing the new BlackBerry 10.2.1 Runtime for Android
>>>> apps. Now with support for Jelly Bean, Bluetooth, Mapview and
>>>> more. Get your Android app in front of a whole new audience.
>>>> Start now. 
>>>> http://pubads.g.doubleclick.net/gampad/clk?id=124407151&iu=/4140/ostg.clktrk
>>>>
>>>>
>
>>>> 
_______________________________________________
>>>> Iverilog-devel mailing list
>>>> Ive...@li... 
>>>> https://lists.sourceforge.net/lists/listinfo/iverilog-devel
>>>> 
> 
>> 
>> ------------------------------------------------------------------------------
>>
>> 
Android apps run on BlackBerry 10
>> Introducing the new BlackBerry 10.2.1 Runtime for Android apps. 
>> Now with support for Jelly Bean, Bluetooth, Mapview and more. Get
>> your Android app in front of a whole new audience.  Start now. 
>> http://pubads.g.doubleclick.net/gampad/clk?id=124407151&iu=/4140/ostg.clktrk
>>
>> 
_______________________________________________
>> Iverilog-devel mailing list Ive...@li... 
>> https://lists.sourceforge.net/lists/listinfo/iverilog-devel
>> 
> 
> 
> ------------------------------------------------------------------------------
>
> 
Android apps run on BlackBerry 10
> Introducing the new BlackBerry 10.2.1 Runtime for Android apps. Now
> with support for Jelly Bean, Bluetooth, Mapview and more. Get your
> Android app in front of a whole new audience.  Start now. 
> http://pubads.g.doubleclick.net/gampad/clk?id=124407151&iu=/4140/ostg.clktrk
>
> 
_______________________________________________
> Iverilog-devel mailing list Ive...@li... 
> https://lists.sourceforge.net/lists/listinfo/iverilog-devel
> 

- -- 
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."
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Comment: Using GnuPG with Thunderbird - http://www.enigmail.net/

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Re: [Iverilog-devel] vec4-stack progress

[Martin W. <mai...@ma...>]

I was somewhat expecting a performance hit (which is why I checked for it!). 
I'll remind you of this

   http://sourceforge.net/p/iverilog/mailman/message/31240085/

which could account for a lot of it.

Martin

Stephen Williams wrote:
> -----BEGIN PGP SIGNED MESSAGE-----
> Hash: SHA1
>
>
> Woah, that's interesting. (The performance hit, I mean.)
>
> It is true, though, that some of the translation is simplistic,
> and my expectation is that with some optimization I should be
> able to turn that around. For example, I have done NO profiling
> yet. There are a few tests in the ivtest suite that broke, and
> I want to address those first, but then I want to do some profiles
> to really see what's bad. Honestly, I think I can get it faster
> than the existing mode.
>
> On 02/14/2014 12:41 PM, Martin Whitaker wrote:
>> Running the subset of my production tests that Icarus can handle
>> has not exposed any functional bugs. However, selecting a
>> moderately sized test, I'm seeing ~32% increase in run time and
>> ~10% increase in number of vvp instructions. This is too big a
>> performance hit for my liking.
>>
>> Martin
>>
>> Stephen Williams wrote:
>>
>> The vec4-stack branch of Icarus Verilog in the git repository is
>> almost complete. I've been merging in updates to master, so it has
>> been keeping up with other changes.
>>
>> The actual vec4 work is almost complete; there are only a few
>> unusual corner cases that are not working, so I think it is ready
>> for folks to start trying it out. I'm not going to merge it into
>> master until it passes ALL the ivtest tests that master current
>> passes (there are a handful that fail) but it is really close and I
>> would like to get it out there for people to mess with.
>>
>>>
>>> ------------------------------------------------------------------------------
>>>
>>>
> Android apps run on BlackBerry 10
>>> Introducing the new BlackBerry 10.2.1 Runtime for Android apps.
>>> Now with support for Jelly Bean, Bluetooth, Mapview and more. Get
>>> your Android app in front of a whole new audience.  Start now.
>>> http://pubads.g.doubleclick.net/gampad/clk?id=124407151&iu=/4140/ostg.clktrk
>>>
>>>
> _______________________________________________
>>> Iverilog-devel mailing list Ive...@li...
>>> https://lists.sourceforge.net/lists/listinfo/iverilog-devel
>>>
>>
>>
>> ------------------------------------------------------------------------------
>>
>>
> Android apps run on BlackBerry 10
>> Introducing the new BlackBerry 10.2.1 Runtime for Android apps. Now
>> with support for Jelly Bean, Bluetooth, Mapview and more. Get your
>> Android app in front of a whole new audience.  Start now.
>> http://pubads.g.doubleclick.net/gampad/clk?id=124407151&iu=/4140/ostg.clktrk
>>
>>
> _______________________________________________
>> Iverilog-devel mailing list Ive...@li...
>> https://lists.sourceforge.net/lists/listinfo/iverilog-devel
>>
>
> - --
> Steve Williams                "The woods are lovely, dark and deep.
> steve at icarus.com           But I have promises to keep,
> http://www.icarus.com         and lines to code before I sleep,
> http://www.picturel.com       And lines to code before I sleep."
> -----BEGIN PGP SIGNATURE-----
> Version: GnuPG v2.0.19 (GNU/Linux)
> Comment: Using GnuPG with Thunderbird - http://www.enigmail.net/
>
> iEYEARECAAYFAlL+gKYACgkQrPt1Sc2b3ikXfgCfdJHO/jjYYLDIdxryfnmNyoGQ
> WsgAoMz+TwqjfjTCS2SkcoipRWF8q5Ys
> =lbE1
> -----END PGP SIGNATURE-----
>
> ------------------------------------------------------------------------------
> Android apps run on BlackBerry 10
> Introducing the new BlackBerry 10.2.1 Runtime for Android apps.
> Now with support for Jelly Bean, Bluetooth, Mapview and more.
> Get your Android app in front of a whole new audience.  Start now.
> http://pubads.g.doubleclick.net/gampad/clk?id=124407151&iu=/4140/ostg.clktrk
> _______________________________________________
> Iverilog-devel mailing list
> Ive...@li...
> https://lists.sourceforge.net/lists/listinfo/iverilog-devel
>

Re: [Iverilog-devel] vec4-stack progress

[Stephen W. <st...@ic...>]

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1


Woah, that's interesting. (The performance hit, I mean.)

It is true, though, that some of the translation is simplistic,
and my expectation is that with some optimization I should be
able to turn that around. For example, I have done NO profiling
yet. There are a few tests in the ivtest suite that broke, and
I want to address those first, but then I want to do some profiles
to really see what's bad. Honestly, I think I can get it faster
than the existing mode.

On 02/14/2014 12:41 PM, Martin Whitaker wrote:
> Running the subset of my production tests that Icarus can handle
> has not exposed any functional bugs. However, selecting a
> moderately sized test, I'm seeing ~32% increase in run time and
> ~10% increase in number of vvp instructions. This is too big a
> performance hit for my liking.
> 
> Martin
> 
> Stephen Williams wrote:
> 
> The vec4-stack branch of Icarus Verilog in the git repository is
> almost complete. I've been merging in updates to master, so it has
> been keeping up with other changes.
> 
> The actual vec4 work is almost complete; there are only a few 
> unusual corner cases that are not working, so I think it is ready
> for folks to start trying it out. I'm not going to merge it into
> master until it passes ALL the ivtest tests that master current
> passes (there are a handful that fail) but it is really close and I
> would like to get it out there for people to mess with.
> 
>> 
>> ------------------------------------------------------------------------------
>>
>> 
Android apps run on BlackBerry 10
>> Introducing the new BlackBerry 10.2.1 Runtime for Android apps. 
>> Now with support for Jelly Bean, Bluetooth, Mapview and more. Get
>> your Android app in front of a whole new audience.  Start now. 
>> http://pubads.g.doubleclick.net/gampad/clk?id=124407151&iu=/4140/ostg.clktrk
>>
>> 
_______________________________________________
>> Iverilog-devel mailing list Ive...@li... 
>> https://lists.sourceforge.net/lists/listinfo/iverilog-devel
>> 
> 
> 
> ------------------------------------------------------------------------------
>
> 
Android apps run on BlackBerry 10
> Introducing the new BlackBerry 10.2.1 Runtime for Android apps. Now
> with support for Jelly Bean, Bluetooth, Mapview and more. Get your
> Android app in front of a whole new audience.  Start now. 
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>
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> https://lists.sourceforge.net/lists/listinfo/iverilog-devel
> 

- -- 
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2.0.19 (GNU/Linux)
Comment: Using GnuPG with Thunderbird - http://www.enigmail.net/

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WsgAoMz+TwqjfjTCS2SkcoipRWF8q5Ys
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Re: [Iverilog-devel] vec4-stack progress

[Martin W. <mai...@ma...>]

Running the subset of my production tests that Icarus can handle has not 
exposed any functional bugs. However, selecting a moderately sized test, I'm 
seeing ~32% increase in run time and ~10% increase in number of vvp 
instructions. This is too big a performance hit for my liking.

Martin

Stephen Williams wrote:
> -----BEGIN PGP SIGNED MESSAGE-----
> Hash: SHA1
>
>
> The vec4-stack branch of Icarus Verilog in the git repository
> is almost complete. I've been merging in updates to master, so
> it has been keeping up with other changes.
>
> The actual vec4 work is almost complete; there are only a few
> unusual corner cases that are not working, so I think it is
> ready for folks to start trying it out. I'm not going to merge
> it into master until it passes ALL the ivtest tests that master
> current passes (there are a handful that fail) but it is really
> close and I would like to get it out there for people to mess
> with.
>
> - --
> Steve Williams                "The woods are lovely, dark and deep.
> steve at icarus.com           But I have promises to keep,
> http://www.icarus.com         and lines to code before I sleep,
> http://www.picturel.com       And lines to code before I sleep."
> -----BEGIN PGP SIGNATURE-----
> Version: GnuPG v2.0.19 (GNU/Linux)
> Comment: Using GnuPG with Thunderbird - http://www.enigmail.net/
>
> iEYEARECAAYFAlL9jrAACgkQrPt1Sc2b3ikERgCfYujagIh8cUTjzENqzPBQW0VW
> JyQAn1HtcLPh2YcFj2jWHGrBXI4jvwLb
> =thnL
> -----END PGP SIGNATURE-----
>
> ------------------------------------------------------------------------------
> Android apps run on BlackBerry 10
> Introducing the new BlackBerry 10.2.1 Runtime for Android apps.
> Now with support for Jelly Bean, Bluetooth, Mapview and more.
> Get your Android app in front of a whole new audience.  Start now.
> http://pubads.g.doubleclick.net/gampad/clk?id=124407151&iu=/4140/ostg.clktrk
> _______________________________________________
> Iverilog-devel mailing list
> Ive...@li...
> https://lists.sourceforge.net/lists/listinfo/iverilog-devel
>

[Iverilog-devel] vec4-stack progress

[Stephen W. <st...@ic...>]

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1


The vec4-stack branch of Icarus Verilog in the git repository
is almost complete. I've been merging in updates to master, so
it has been keeping up with other changes.

The actual vec4 work is almost complete; there are only a few
unusual corner cases that are not working, so I think it is
ready for folks to start trying it out. I'm not going to merge
it into master until it passes ALL the ivtest tests that master
current passes (there are a handful that fail) but it is really
close and I would like to get it out there for people to mess
with.

- -- 
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."
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Comment: Using GnuPG with Thunderbird - http://www.enigmail.net/

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Re: [Iverilog-devel] Interesting corner case

[Jared C. <jar...@gm...>]

VCS version G-2012.09-3, ncverilog 08.20-s006, and ModelSim 10.0a all print
"PASSED".

Jared


On Fri, Jan 17, 2014 at 4:56 PM, Stephen Williams <st...@ic...> wrote:

> -----BEGIN PGP SIGNED MESSAGE-----
> Hash: SHA1
>
>
> The attached test is something that caught me by surprise. The
> example tests the ability to continuous assign to part of a
> vector and behaviorally assign to other parts of the variable.
> This never comes up in baseline Verilog, but in SystemVerilog
> I think it is legal. Can someone double-check this test program
> for me on some big-name tools? Thanks.
>
> - --
> Steve Williams                "The woods are lovely, dark and deep.
> steve at icarus.com           But I have promises to keep,
> http://www.icarus.com         and lines to code before I sleep,
> http://www.picturel.com       And lines to code before I sleep."
> -----BEGIN PGP SIGNATURE-----
> Version: GnuPG v2.0.19 (GNU/Linux)
> Comment: Using GnuPG with Thunderbird - http://www.enigmail.net/
>
> iEYEARECAAYFAlLZ0TkACgkQrPt1Sc2b3im7HwCgsGdpF/ZgEu0kx5tt/4N1N3fs
> 4dwAoMy2jwGIyAaZXdNk3NrBXALYzqW+
> =+K85
> -----END PGP SIGNATURE-----
>
>
> ------------------------------------------------------------------------------
> CenturyLink Cloud: The Leader in Enterprise Cloud Services.
> Learn Why More Businesses Are Choosing CenturyLink Cloud For
> Critical Workloads, Development Environments & Everything In Between.
> Get a Quote or Start a Free Trial Today.
>
> http://pubads.g.doubleclick.net/gampad/clk?id=119420431&iu=/4140/ostg.clktrk
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> Ive...@li...
> https://lists.sourceforge.net/lists/listinfo/iverilog-devel
>
>

Re: [Iverilog-devel] Weird behaviour of Verilog addition/comparison

[Martin W. <mai...@ma...>]

Stephen Williams wrote:
> Yep, that's an Icarus Verilog bug and needs to be filed.
> ISim is correct that 2'b10 + 2'b10 == 2'b00.
>
> On 01/21/2014 10:19 AM, Sébastien Bourdeauducq wrote:
>> On 01/21/2014 07:17 PM, Stephen Williams wrote:
>>>> $display("%b", 2'd2 + 2'd2);
>>> I'm actually surprised that this displays 100, as that is 3 bits,
>>>   and the expression is only 2 bits.
>>
>> FWIW Xilinx ISim displays 00 here.

I'm guessing this is using v0.9. Development gives the correct result. There 
are a lot of expression width bugs in v0.9 which are fixed in development.

Martin

Re: [Iverilog-devel] Weird behaviour of Verilog addition/comparison

[Stephen W. <st...@ic...>]

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1


Yep, that's an Icarus Verilog bug and needs to be filed.
ISim is correct that 2'b10 + 2'b10 == 2'b00.

On 01/21/2014 10:19 AM, Sébastien Bourdeauducq wrote:
> On 01/21/2014 07:17 PM, Stephen Williams wrote:
>>> $display("%b", 2'd2 + 2'd2);
>> I'm actually surprised that this displays 100, as that is 3 bits,
>>  and the expression is only 2 bits.
> 
> FWIW Xilinx ISim displays 00 here.
> 
> 
> 
> ------------------------------------------------------------------------------
>
> 
CenturyLink Cloud: The Leader in Enterprise Cloud Services.
> Learn Why More Businesses Are Choosing CenturyLink Cloud For 
> Critical Workloads, Development Environments & Everything In
> Between. Get a Quote or Start a Free Trial Today. 
> http://pubads.g.doubleclick.net/gampad/clk?id=119420431&iu=/4140/ostg.clktrk
>
> 
_______________________________________________
> Iverilog-devel mailing list Ive...@li... 
> https://lists.sourceforge.net/lists/listinfo/iverilog-devel
> 


- -- 
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."
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=xwq5
-----END PGP SIGNATURE-----

Re: [Iverilog-devel] Weird behaviour of Verilog addition/comparison

[Sébastien B. <seb...@le...>]

On 01/21/2014 07:17 PM, Stephen Williams wrote:
>> $display("%b", 2'd2 + 2'd2);
> I'm actually surprised that this displays 100, as that is 3 bits, 
> and the expression is only 2 bits.

FWIW Xilinx ISim displays 00 here.

Re: [Iverilog-devel] Weird behaviour of Verilog addition/comparison

[Stephen W. <st...@ic...>]

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1

On 01/21/2014 09:24 AM, Sébastien Bourdeauducq wrote:
> Hi,
> 
> Running the following:
> 
> $display("%b", 2'd2 + 2'd2);

I'm actually surprised that this displays 100, as that is 3 bits,
and the expression is only 2 bits.

> $display("%b", 3'd4 >= 2'd1);

Yeah, that's fine. 3'b100 >= 2'b01  ---> 1'b1

> $display("%b", (2'd2 + 2'd2) >= 2'd1);

This is right: (2'b10 + 2'b10) >= 2'b01
Both sides are 2bits wide, and 10+10 == (1)00 == 2'b00, which
is not >= 01. The size of arithmetic expressions is the size
of the largest operand, in the case of "+" in your example,
that is 2bits.


- -- 
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."
-----BEGIN PGP SIGNATURE-----
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[Iverilog-devel] Weird behaviour of Verilog addition/comparison

[Sébastien B. <seb...@le...>]

Hi,

Running the following:

$display("%b", 2'd2 + 2'd2);
$display("%b", 3'd4 >= 2'd1);
$display("%b", (2'd2 + 2'd2) >= 2'd1);

produces this output:

100 (ok)
1 (ok)
0 (wtf?!)

The Verilog standard says that when comparing operands of different
lengths, the smaller one should be extended (I guess, sign-extended).

Is there yet another Verilog idiosyncrasy that I have missed out (e.g.
the right hand side of the comparison defines the width for the
addition), or is this a bug in Icarus Verilog?

Sébastien

[Iverilog-devel] Crazy goings on in iverilog development

[Stephen W. <st...@ic...>]

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1


I don't know if anyone noticed, but I've been busy for the last
two months working on a new branch, the vec4-stack branch. For
those who know how Icarus Verilog simulation works internally,
that branch is a complete rework of how vector expressions are
evaluated in behavioral code. The work is not done, it will be
merged into master when I am done, but it is done enough that
anyone working on the vvp engine or code generator will want to
check with what is going on in there.

My thinking for this change is that a stack based expression
engine is probably more efficient than the flat memory based
system that it is replacing, and is almost certainly simpler to
generate code for. The latter is turning out to be very true.
It remains to be seen if it will ultimately be faster, but I'm
thinking that it will, at least after some optimization.

anyhow, that's what's up with that branch. Thought you'd like
to know.

- -- 
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."
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[Iverilog-devel] Interesting corner case

[Stephen W. <st...@ic...>]

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1


The attached test is something that caught me by surprise. The
example tests the ability to continuous assign to part of a
vector and behaviorally assign to other parts of the variable.
This never comes up in baseline Verilog, but in SystemVerilog
I think it is legal. Can someone double-check this test program
for me on some big-name tools? Thanks.

- -- 
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2.0.19 (GNU/Linux)
Comment: Using GnuPG with Thunderbird - http://www.enigmail.net/

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4dwAoMy2jwGIyAaZXdNk3NrBXALYzqW+
=+K85
-----END PGP SIGNATURE-----

Re: [Iverilog-devel] Yet another SystemVerilog test

[Jared C. <jar...@gm...>]

All three tests pass in ModelSim 10.0a and VCS G-2012.09-3 as well.

Jared

On Wed, Dec 11, 2013 at 6:39 PM, Stephen Williams <st...@ic...> wrote:
> -----BEGIN PGP SIGNED MESSAGE-----
> Hash: SHA1
>
> This is actually a set of tests that check my understanding of
> how the $root scope should work for certain types of typedefs.
> I've encountered syntax like this in customer code so I'm pretty
> sure it is correct, but I'd like to have these programs in
> particular checked, just to be sure.
>
> Thanks,
>
> - --
> Steve Williams                "The woods are lovely, dark and deep.
> steve at icarus.com           But I have promises to keep,
> http://www.icarus.com         and lines to code before I sleep,
> http://www.picturel.com       And lines to code before I sleep."
> -----BEGIN PGP SIGNATURE-----
> Version: GnuPG v2.0.19 (GNU/Linux)
> Comment: Using GnuPG with Thunderbird - http://www.enigmail.net/
>
> iEYEARECAAYFAlKpIegACgkQrPt1Sc2b3ilsGQCglFv7pZmhGljFNux1xuEkAJSE
> sUwAoOpBTRj20J/UzSDVbhZq0qFuiW0k
> =SdV2
> -----END PGP SIGNATURE-----
>
> ------------------------------------------------------------------------------
> Rapidly troubleshoot problems before they affect your business. Most IT
> organizations don't have a clear picture of how application performance
> affects their revenue. With AppDynamics, you get 100% visibility into your
> Java,.NET, & PHP application. Start your 15-day FREE TRIAL of AppDynamics Pro!
> http://pubads.g.doubleclick.net/gampad/clk?id=84349831&iu=/4140/ostg.clktrk
> _______________________________________________
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> Ive...@li...
> https://lists.sourceforge.net/lists/listinfo/iverilog-devel
>

Re: [Iverilog-devel] [iverilog-devel] dump memory array ($dumpvars)

[<by...@nc...>]

"To dump an array word Icarus needs to escape the name so it is compatible with 
the VCD dump format. That's what \data[0][31:0] is. It is the zeroth? 32-bit 
word of the data array. Because an escaped name and an array name could now 
conflict Icarus produces the warning. It would be best if it could check for an 
escaped identifier conflict and only print a message when there is a problem, 
but as I remember this was not possible."

...I don't think that there's a need to escape the names.  Both VCS (followed by fsdb2vcd) and CVC emit the name directly with no problems.  Cut and paste example shown below:

$var wire 5 `' IC_DrAd0 [3][4:0] $end
$var wire 5 a' IC_DrAd0 [2][4:0] $end
$var wire 5 b' IC_DrAd0 [1][4:0] $end
$var wire 5 c' IC_DrAd0 [0][4:0] $end

I realize the VCD spec doesn't define this, but I've had to fold in a lot of these kinds of extensions into gtkwave over the years as other tools generate these constructs.  The escapes can cause save file incompatibilities (missing signals) when trying to simulate on iverilog versus VCS.

Over time, SV constructs likely will cause further things added to the VCD files.  AFAIK, the VCD part of the 1364 spec hasn't updated at all since Verilog-XL.  CVC gets around possible incompatibilities by adding a +dump_arrays plusarg (and no, you don't have to loop on each array element either).

-Tony

Re: [Iverilog-devel] Yet another SystemVerilog test

[Iztok J. <izt...@gm...>]

$ irun sv_union1b.sv
irun: 13.10-s008: (c) Copyright 1995-2013 Cadence Design Systems, Inc.
file: sv_union1b.sv
    module worklib.main:sv
        errors: 0, warnings: 0
        Caching library 'worklib' ....... Done
    Elaborating the design hierarchy:
    Top level design units:
        $unit_0x06988e28
        main
    Building instance overlay tables: .................... Done
    Generating native compiled code:
        worklib.main:sv <0x3f23628f>
            streams:   1, words:  1093
    Building instance specific data structures.
    Loading native compiled code:     .................... Done
    Design hierarchy summary:
                    Instances  Unique
        Modules:            1       1
        Registers:          1       1
        Initial blocks:     1       1
        Compilation units:  1       1
    Writing initial simulation snapshot: worklib.main:sv
Loading snapshot worklib.main:sv .................... Done
ncsim> source /tools/opt/cadence/INCISIV13.10.008/tools/inca/files/ncsimrc
ncsim> run
PASSED
ncsim: *W,RNQUIE: Simulation is complete.
ncsim> exit


$ irun sv_union2b.sv
irun: 13.10-s008: (c) Copyright 1995-2013 Cadence Design Systems, Inc.
file: sv_union2b.sv
    module worklib.main:sv
        errors: 0, warnings: 0
        Caching library 'worklib' ....... Done
    Elaborating the design hierarchy:
    Top level design units:
        $unit_0x069c2138
        main
    Building instance overlay tables: .................... Done
    Generating native compiled code:
        worklib.main:sv <0x4f0d5546>
            streams:   1, words:  1097
    Building instance specific data structures.
    Loading native compiled code:     .................... Done
    Design hierarchy summary:
                    Instances  Unique
        Modules:            1       1
        Registers:          1       1
        Initial blocks:     1       1
        Compilation units:  1       1
    Writing initial simulation snapshot: worklib.main:sv
Loading snapshot worklib.main:sv .................... Done
ncsim> source /tools/opt/cadence/INCISIV13.10.008/tools/inca/files/ncsimrc
ncsim> run
PASSED
ncsim: *W,RNQUIE: Simulation is complete.
ncsim> exit


$ irun sv_union3b.sv
irun: 13.10-s008: (c) Copyright 1995-2013 Cadence Design Systems, Inc.
file: sv_union3b.sv
    module worklib.main:sv
        errors: 0, warnings: 0
        Caching library 'worklib' ....... Done
    Elaborating the design hierarchy:
    Top level design units:
        $unit_0x069fb448
        main
    Building instance overlay tables: .................... Done
    Generating native compiled code:
        worklib.main:sv <0x3d228bc6>
            streams:   1, words:  1089
    Building instance specific data structures.
    Loading native compiled code:     .................... Done
    Design hierarchy summary:
                    Instances  Unique
        Modules:            1       1
        Registers:          1       1
        Initial blocks:     1       1
        Compilation units:  1       1
    Writing initial simulation snapshot: worklib.main:sv
Loading snapshot worklib.main:sv .................... Done
ncsim> source /tools/opt/cadence/INCISIV13.10.008/tools/inca/files/ncsimrc
ncsim> run
PASSED
ncsim: *W,RNQUIE: Simulation is complete.
ncsim> exit




On Thu, Dec 12, 2013 at 3:39 AM, Stephen Williams <st...@ic...> wrote:

> -----BEGIN PGP SIGNED MESSAGE-----
> Hash: SHA1
>
> This is actually a set of tests that check my understanding of
> how the $root scope should work for certain types of typedefs.
> I've encountered syntax like this in customer code so I'm pretty
> sure it is correct, but I'd like to have these programs in
> particular checked, just to be sure.
>
> Thanks,
>
> - --
> Steve Williams                "The woods are lovely, dark and deep.
> steve at icarus.com           But I have promises to keep,
> http://www.icarus.com         and lines to code before I sleep,
> http://www.picturel.com       And lines to code before I sleep."
> -----BEGIN PGP SIGNATURE-----
> Version: GnuPG v2.0.19 (GNU/Linux)
> Comment: Using GnuPG with Thunderbird - http://www.enigmail.net/
>
> iEYEARECAAYFAlKpIegACgkQrPt1Sc2b3ilsGQCglFv7pZmhGljFNux1xuEkAJSE
> sUwAoOpBTRj20J/UzSDVbhZq0qFuiW0k
> =SdV2
> -----END PGP SIGNATURE-----
>
>
> ------------------------------------------------------------------------------
> Rapidly troubleshoot problems before they affect your business. Most IT
> organizations don't have a clear picture of how application performance
> affects their revenue. With AppDynamics, you get 100% visibility into your
> Java,.NET, & PHP application. Start your 15-day FREE TRIAL of AppDynamics
> Pro!
> http://pubads.g.doubleclick.net/gampad/clk?id=84349831&iu=/4140/ostg.clktrk
> _______________________________________________
> Iverilog-devel mailing list
> Ive...@li...
> https://lists.sourceforge.net/lists/listinfo/iverilog-devel
>
>

[Iverilog-devel] Yet another SystemVerilog test

[Stephen W. <st...@ic...>]

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1

This is actually a set of tests that check my understanding of
how the $root scope should work for certain types of typedefs.
I've encountered syntax like this in customer code so I'm pretty
sure it is correct, but I'd like to have these programs in
particular checked, just to be sure.

Thanks,

- -- 
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2.0.19 (GNU/Linux)
Comment: Using GnuPG with Thunderbird - http://www.enigmail.net/

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sUwAoOpBTRj20J/UzSDVbhZq0qFuiW0k
=SdV2
-----END PGP SIGNATURE-----

Re: [Iverilog-devel] [iverilog-devel] dump memory array ($dumpvars)

[Cary R. <cy...@ya...>]

To dump an array word Icarus needs to escape the name so it is compatible with the VCD dump format. That's what \data[0][31:0] is. It is the zeroth  32-bit word of the data array. Because an escaped name and an array name could now conflict Icarus produces the warning. It would be best if it could check for an escaped identifier conflict and only print a message when there is a problem, but as I remember this was not possible.

We chose to use escaped identifiers so that all the dumpers could handle array words. The other common choice is to only support them using a special dump command that only works with certain dump formats.

I agree it would be nice if we could make the warning more accurate, but we are usually busy working on other things so minor annoyances that appear to be complicated to fix do not often get fixed. As I remember, and it has been a number of years, the issue is if you search for the escaped identifier it find the array element and there is no way in the VPI to search for the next occurrence. It's possible that finding the array element in the Icarus search by name implementation is a bug.


Cary




On Thursday, December 5, 2013 9:00 AM, Victor Lyuboslavsky <vi...@vi...> wrote:
 
Yes, the warning seems worrisome.

However, everything seems to be working fine: http://www.edaplayground.com/s/4/520




On Thu, Dec 5, 2013 at 8:12 AM, gon1332 <g1a...@ya...> wrote:

Hi!
>
>I try to dump an array (reg [31:0] data [31:0]) but I can't do it
>successfully.
>I've tried the way that is in the wiki:
>
>for (idx = 0; idx < 32; idx = idx + 1) $dumpvars(0,
>cpu_tb.cpu0.cpu_dp.cpu_regs.data[idx]);
>
>It works, but 2 things happen.
>1] A warning shows up: VCD warning: array word
>cpu_tb.cpu0.cpu_dp.cpu_regs.data[0] will conflict with an escaped
>identifier.
>2] In GTKWave I have something like this in SST window: \data[0][31:0]
>
>Is there any solution about that?
>
>Thanks in advance and sorry for my English.
>
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Re: [Iverilog-devel] [iverilog-devel] dump memory array ($dumpvars)

[Victor L. <vi...@vi...>]

Yes, the warning seems worrisome.

However, everything seems to be working fine:
http://www.edaplayground.com/s/4/520


On Thu, Dec 5, 2013 at 8:12 AM, gon1332 <g1a...@ya...> wrote:

> Hi!
>
> I try to dump an array (reg [31:0] data [31:0]) but I can't do it
> successfully.
> I've tried the way that is in the wiki:
>
> for (idx = 0; idx < 32; idx = idx + 1) $dumpvars(0,
> cpu_tb.cpu0.cpu_dp.cpu_regs.data[idx]);
>
> It works, but 2 things happen.
> 1] A warning shows up: VCD warning: array word
> cpu_tb.cpu0.cpu_dp.cpu_regs.data[0] will conflict with an escaped
> identifier.
> 2] In GTKWave I have something like this in SST window: \data[0][31:0]
>
> Is there any solution about that?
>
> Thanks in advance and sorry for my English.
>
>
> ------------------------------------------------------------------------------
> Sponsored by Intel(R) XDK
> Develop, test and display web and hybrid apps with a single code base.
> Download it for free now!
>
> http://pubads.g.doubleclick.net/gampad/clk?id=111408631&iu=/4140/ostg.clktrk
> _______________________________________________
> Iverilog-devel mailing list
> Ive...@li...
> https://lists.sourceforge.net/lists/listinfo/iverilog-devel
>
>

[Iverilog-devel] [iverilog-devel] dump memory array ($dumpvars)

[gon1332 <g1a...@ya...>]

Hi!

I try to dump an array (reg [31:0] data [31:0]) but I can't do it 
successfully.
I've tried the way that is in the wiki:

for (idx = 0; idx < 32; idx = idx + 1) $dumpvars(0, 
cpu_tb.cpu0.cpu_dp.cpu_regs.data[idx]);

It works, but 2 things happen.
1] A warning shows up: VCD warning: array word 
cpu_tb.cpu0.cpu_dp.cpu_regs.data[0] will conflict with an escaped 
identifier.
2] In GTKWave I have something like this in SST window: \data[0][31:0]

Is there any solution about that?

Thanks in advance and sorry for my English.