iverilog-devel — Conversations on matters of Icarus Verilog development

[Iverilog-devel] Huge FST files

[Stephen W. <st...@ic...>]

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This may be a Cary and/or Tony question. In my day job, we are
running long simulations using FST traces. It appears that the
dumper is cutting files off at 1Gig, though. Is this a feature?
What's weird, it seems to continue in a fresh file, but it is
called system_001.lxt, instead of .fst. Is this correct? Is
there a way to adjust this behavior?

- -- 
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."
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Re: [Iverilog-devel] instantiating undefined modules

[Martin W. <mai...@ma...>]

Martin Whitaker wrote:
> To expand a bit on what Steve said, for each library component you need to
> create a module that just defines the input/output pins of that component. For
> example:
>
>     module 74LS245(
>       input       nEN,
>       input       DIR,
>       inout [8:1] A,
>       inout [8:1] B
>     );
>     endmodule
>
And of course, to be legal Verilog, the module name must start with a letter 
or an underscore, so you would need to change this example to get it to compile.

Re: [Iverilog-devel] instantiating undefined modules

[Martin W. <mai...@ma...>]

To expand a bit on what Steve said, for each library component you need to 
create a module that just defines the input/output pins of that component. For 
example:

   module 74LS245(
     input       nEN,
     input       DIR,
     inout [8:1] A,
     inout [8:1] B
   );
   endmodule

To create a library, you can either create a separate file for each component 
in a common directory and use the -y command line option to get iverilog to 
search that directory (the file names must match the module names for this to 
work), or you can put a number of components in a single file and use the -v 
command line option to get iverilog to read that file and extract whatever 
components are needed.

One word of warning - Verilog does not enforce port directionality (e.g. it is 
perfectly legal to connect two output ports together), so you would need the 
backend to perform electrical rule checking.


Stephen Williams wrote:
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>
> I encountered the same issue with the "pcb" code generator,
> which is intended to do exactly what you are trying to do,
> but target PCB instead of Kicad. My conclusion at the time
> was it was best to make an empty module to act as a place-
> holder. This is handy anyhow as a place to attach default
> attributes such as footprint information.
>
> On 03/13/2014 04:17 PM, Cotton Seed wrote:
>> Is there a mechanism in iverlog to elaborate a design that
>> instantiates an undefined/external module?  Obviously, I don't
>> intend to simulate it. I'm potentially interested in using verilog
>> rather than schematic capture to do PCB design.  There would need
>> to be a library of discrete components, but I'm not sure how to
>> declare such a thing in verilog. (I'm still relatively new to
>> verilog.  My apologies if my question is naive.)  A backend would
>> convert the iverlog netlist to a netlist for something like Kicad.
>>
>> Best, Cotton
>
>
>
> - --
> Steve Williams                "The woods are lovely, dark and deep.
> steve at icarus.com           But I have promises to keep,
> http://www.icarus.com         and lines to code before I sleep,
> http://www.picturel.com       And lines to code before I sleep."
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>
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> "Graph Databases" is the definitive new guide to graph databases and their
> applications. Written by three acclaimed leaders in the field,
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Re: [Iverilog-devel] instantiating undefined modules

[Stephen W. <st...@ic...>]

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I encountered the same issue with the "pcb" code generator,
which is intended to do exactly what you are trying to do,
but target PCB instead of Kicad. My conclusion at the time
was it was best to make an empty module to act as a place-
holder. This is handy anyhow as a place to attach default
attributes such as footprint information.

On 03/13/2014 04:17 PM, Cotton Seed wrote:
> Is there a mechanism in iverlog to elaborate a design that
> instantiates an undefined/external module?  Obviously, I don't
> intend to simulate it. I'm potentially interested in using verilog
> rather than schematic capture to do PCB design.  There would need
> to be a library of discrete components, but I'm not sure how to
> declare such a thing in verilog. (I'm still relatively new to
> verilog.  My apologies if my question is naive.)  A backend would
> convert the iverlog netlist to a netlist for something like Kicad.
> 
> Best, Cotton



- -- 
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."
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[Iverilog-devel] instantiating undefined modules

[Cotton S. <co...@al...>]

Is there a mechanism in iverlog to elaborate a design that instantiates
an undefined/external module?  Obviously, I don't intend to simulate it.
 I'm potentially interested in using verilog rather than schematic
capture to do PCB design.  There would need to be a library of discrete
components, but I'm not sure how to declare such a thing in verilog.
(I'm still relatively new to verilog.  My apologies if my question is
naive.)  A backend would convert the iverlog netlist to a netlist for
something like Kicad.

Best,
Cotton

Re: [Iverilog-devel] SystemVerilog, continuous assignment and unpacked arrays

[Michael S. <mic...@gm...>]

After changing Q from wire to reg both ncsim and vcs passed.

Best regards,
Michael Strelnikov


On 13 March 2014 13:58, Stephen Williams <st...@ic...> wrote:

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> I cannot find any clarity on this in the IEEE1800 LRM. It seems
> to imply that continuous assignments of unpacked arrays are OK,
> as long as there is only a single driver. The attached test
> program tries to test that. Of course, the current Icarus Verilog
> reports an error on this, but I think big name SystemVerilog
> compilers will handle it.
>
> Can someone test this for me?
>
>
> - --
> Steve Williams                "The woods are lovely, dark and deep.
> steve at icarus.com           But I have promises to keep,
> http://www.icarus.com         and lines to code before I sleep,
> http://www.picturel.com       And lines to code before I sleep."
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>
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> =fmRV
> -----END PGP SIGNATURE-----
>
>
> ------------------------------------------------------------------------------
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> "Graph Databases" is the definitive new guide to graph databases and their
> applications. Written by three acclaimed leaders in the field,
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> _______________________________________________
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[Iverilog-devel] SystemVerilog, continuous assignment and unpacked arrays

[Stephen W. <st...@ic...>]

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I cannot find any clarity on this in the IEEE1800 LRM. It seems
to imply that continuous assignments of unpacked arrays are OK,
as long as there is only a single driver. The attached test
program tries to test that. Of course, the current Icarus Verilog
reports an error on this, but I think big name SystemVerilog
compilers will handle it.

Can someone test this for me?


- -- 
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."
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Re: [Iverilog-devel] Parallelization with GPU

[Cary R. <cy...@ya...>]

When I looked at this a few years ago it seemed like the GPU code/data model was too restrictive to provide much benefit. The newer GPUs may have more flexibility so realize my comments/conclusions may be slightly out of date.

I'm not certain how much benefit you can get from a GPU with an event driven simulation. You may be able to speed up specific operations if they can be forced to fit the GPU code/data model (e.g. large vector multiplication, division, modulus, power, etc. may benefit).

If the non-determinism and partitioning can be dealt with multi-threaded (multi-CPU) simulations could be beneficial, but that is a change relative to your original direction.

If you want to stick with a GPU approach you can create a simple code example using the current vvp_vector2_t class to test the speed of the various operations with various width data and then see if using the same vvp_vector2_t input data you can make a faster operation using the GPU for wide vector operations (vectors that have more than BITS_PER_WORD bits). The procedural vector operators are currently in flux since Steve is currently changing them to be stack based. When he is done with this they should also be looked at. The current operators may not be fully optimized so keep that in mind when looking at this (e.g. it may be better to optimize the current operator vs going to a GPU approach). Since this is likely a learning/educational endeavor for you this may not be that important, but you do need to keep it in mind regarding any conclusions you make. The most valid conclusion would be based on the comparison of two fully optimized routines. No
 matter your conclusion we would benefit if the current routines could be optimized.




On Wednesday, March 5, 2014 10:56 PM, Arun P <aru...@gm...> wrote:
 
Thanks a lot Jared and Steve for your kind response. Due to time constrain , I thought I can look for a function or block where the complex computation occurs. 

Now, as you have suggested I want to understand how the vvp runtime works. Is there any proper documentation to understand the flow of the simulation process ? so that I can know where the computation process occurs.( Is there any function or file involving complex computation  ? )  

Looking from the higher level , this might not give significant performance gain. But I think I can start with this to explore GPU processing. Looking for your suggestions. 

Thanks,
Arun. 

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Re: [Iverilog-devel] Parallelization with GPU

[Arun P <aru...@gm...>]

Thanks a lot Jared and Steve for your kind response. Due to time constrain
, I thought I can look for a function or block where the complex
computation occurs.

Now, as you have suggested I want to understand how the vvp runtime works.
Is there any proper documentation to understand the flow of the simulation
process ? so that I can know where the computation process occurs.( Is
there any function or file involving complex computation  ? )

Looking from the higher level , this might not give significant performance
gain. But I think I can start with this to explore GPU processing. Looking
for your suggestions.

Thanks,
Arun.

Re: [Iverilog-devel] Parallelization with GPU

[Stephen W. <st...@ic...>]

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On 03/04/2014 09:41 PM, Arun P wrote:
> What is the functionality of   "of_CMPS( )"   AND    "of_MOD_S ( )
> " functions in "vthread.cc" file .

They implement the %cmp/s and %mod/s instructions, respectively.
See the opcodes.txt file in the vvp/ directory for a description
of all the opcodes.

A word of warning: I'm doing a lot of work in that general area,
with many opcodes being replaced or rewritten so that the virtual
machine handling of 4-value vectors is handled differently. Keep
that in mind.

Also, Jared has posted a response that you maybe should read. I
am getting the impression that you may be in a bit over your head.
No shame in that, this is very specialized code, but you may want
to step back a bit and consider what you are getting yourself into.

Another point: You may want to try to understand a bit more about
how the runtime works, and the nature of GPU processing, and ask
yourself, realistically, how GPU processing (which I think is SIMD)
may even apply to this problem.

- -- 
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."
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Re: [Iverilog-devel] Parallelization with GPU

[Jared C. <jar...@gm...>]

Arun,

I think trying to accelerate Icarus using a GPU is an interesting (maybe a
bit ambitious) project, and I certainly don't want to discourage you from
giving it a go.  However, might I suggest a change of approach.  I'm no
expert on the internals of the vvp runtime (I'm more a user of the project
than a developer despite dabbling a bit here and there), but I really doubt
that you are going to achieve any speed up by trying to take individual
functions in the code and offloading them to a GPU.  The cost of
communication between the CPU and GPU requires a much more granular
approach to using GPUs.

Might I suggest that you first learn the basics of the vvp assembly
language and the overall architecture of how the runtime executes the code.
  After that do some research of techniques described in published
literature to accelerate logic simulation on GPUs (maybe start with a
search of "logic simulation gpu" on scholar.google.com, read a few
interesting looking papers, then look through the cited works in those
papers for others).  Then think about how any of those techniques could be
used or adapted to work with the vvp runtime (or they may inspire a novel
approach that works better with Icarus, but at least you'll have some
background).  Another place to look is the "Horrible Idea" page on the
iverilog wiki (
http://iverilog.wikia.com/wiki/A_Horrible_Idea_Multithreaded_Verilog_Simulator).
 Would that approach lend itself to acceleration on a GPU? (I have no
idea...)  I wouldn't be surprised if the initial artifact would be a near
re-write of vvp that only performs a tiny subset of the functionality as a
proof of concept.

Again, I don't mean to discourage your desire to do this project.  I just
thought I would offer some thoughts on an alternative approach to making it
happen.  (Although I would love to be proven wrong that there is a nice
little box that can be pulled out of the simulator and put into a GPU for
performance gains).

Jared


On Tue, Mar 4, 2014 at 9:41 PM, Arun P <aru...@gm...> wrote:

> What is the functionality of   "of_CMPS( )"   AND    "of_MOD_S ( ) "
> functions in "vthread.cc" file .
>
> I am trying understand those functions to make it parallel. Looking for
> your help.
>
> Thanks,
> Arun.
>
>
> ------------------------------------------------------------------------------
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Re: [Iverilog-devel] Parallelization with GPU

[Arun P <aru...@gm...>]

What is the functionality of   "of_CMPS( )"   AND    "of_MOD_S ( ) "
functions in "vthread.cc" file .

I am trying understand those functions to make it parallel. Looking for
your help.

Thanks,
Arun.

[Iverilog-devel] vec4-stack progress

[Stephen W. <st...@ic...>]

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Tonight I've pushed more updates to the vec4 stack. I'm at the
point now where the vast majority of the regression tests pass.
Those that don't are interesting and in some cases marginal, and
I'm considering merging the vec4-stack into master and accepting
a few new bug reports.

There is some code cleanup to do. I handled a lot of the changes
by ifdef'ing old code out (so that it can absorb mergings) and
putting the new code in. After the merge, a lot of dead code will
become ripe for removal. Also, I expect some cleanup, bug fixes,
and performance work will need to be done.

I've wanted to make this change for a long while now, so I'm eager
to get it merged into master, but I'm open to advice/suggestions
on how to proceed. I think one thing is for people to start trying
out this branch and getting a sense of where we are at.

The work is on the vec4-stack branch of the iverilog repository,
and the vec4-stack branch of the ivtest test suite repository.



- -- 
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."
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[Iverilog-devel] vec4-stack progress

[Stephen W. <st...@ic...>]

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I've updated the vecr-stack branch. I've merged the current master
changes that have been happening, and I've fixed up some expression
width issues. This is getting pretty close to the master, now. There
are only about a dozen tests left that pass the master and not the
vec4 branch.

One visible change has been that the vec4 branch hews more closely
to the standard for unsized numbers that are narrower then 32bits.
This has been a nagging issue for many people, so I'm taking this
opportunity to relent. Unsized literals will be widened to at least
32bits, although I'll still allow for more if needed to preserve
the value.

There have been reports that the vec4-stack branch runs slower,
but I think there is lots of room for optimization, so I'm not
worried about that yet. Overall, I think the result is cleaner
and will be faster after some obvious inefficiencies are cleaned
up.

I want to merge this into master soon, because it is getting
increasingly difficult to maintain separate master and vec4
branches.

- -- 
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."
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Re: [Iverilog-devel] Parallelization with GPU

[Arun P <aru...@gm...>]

Oh OK OK. Thank you , Guy.

Re: [Iverilog-devel] Parallelization with GPU

[Guy H. <ghu...@gm...>]

It does not currently support GPUs.  It does allow converting serial code
to parallel code with minimal effort and allows you to easily switch back
and forth between serial and parallel for debugging, which may be useful in
the short term even if you don't use it in the end.

The Wikipedia page has a good overview: http://en.wikipedia.org/wiki/OpenMP

Guy

On Monday, February 24, 2014, Arun P <aru...@gm...> wrote:

> Does OpenMP support GPU ?
>

Re: [Iverilog-devel] Parallelization with GPU

[Arun P <aru...@gm...>]

Hello Steve,

When I profiled "vvp" with different verilog codes, I was able to find some
functions like
thr_get_bit( ),
thr_put_bit( ),
of_MOD_S( ),
of_CMPS( )   got called several time and consumed relatively larger time.

But those functions did not seem to be involving complex computations. I am
looking for a compute intensive part to off-load to GPU rather  than
parallelizing the whole simulation process. What could be the possible
function or file I can look at ?

Thanks,
Arun.

Re: [Iverilog-devel] Parallelization with GPU

[Arun P <aru...@gm...>]

Does OpenMP support GPU ?

Re: [Iverilog-devel] Parallalization with GPU

[Guy H. <ghu...@gm...>]

If you are looking at parallelization you should look at OpenMP as well.
 Support is built in to recent versions of GCC and would potentially
address a wider market.

On Wednesday, February 19, 2014, Arun P <aru...@gm...> wrote:

> Hi All,
>
> This is Arun. I am trying to speed up Icarus Verilog with GPU parallel
> processing for my academic project. I am looking for help . Which source
> file I should start looking at or which part will be suitable to off-load
> to GPU ? I am totally clueless. Please share your thoughts.
>
> Thanks,
> Arun.
>

Re: [Iverilog-devel] Parallelization with GPU

[Arun P <aru...@gm...>]

Thank You, Steve.

Re: [Iverilog-devel] Parallelization with GPU

[Stephen W. <st...@ic...>]

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Yes, the "vvp" executable is what you should be profiling.
That is the run-time environment.

On 02/20/2014 02:19 AM, Arun P wrote:
> Hello Steve,
> 
> Which executable should be used for profiling? ( I am using GPROF).
>  The one which is in the "vvp" directory?
> 
> Thanks, Arun.
> 
> 
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- -- 
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."
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[Iverilog-devel] Parallelization with GPU

[Arun P <aru...@gm...>]

Hello Steve,

Which executable should be used for profiling? ( I am using GPROF).   The
one which is in the "vvp" directory?

Thanks,
Arun.

[Iverilog-devel] Parallelization with GPU

[Arun P <aru...@gm...>]

Thank you , Steve. I am happy to see your reply. I am gonna start looking
at the vvp directory.

Cheers,
Arun.

Re: [Iverilog-devel] Parallalization with GPU

[Stephen W. <st...@ic...>]

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The place to start is the "vvp" directory, which contains the
run time engine. You will want to dig deep into that to see how
the even queue works, and how the expression calculations work.
Then you will need to think through exactly how you think you
can divide up work between the host and the GPU.

I'm being vague at first because I think your first step will be
to figure out the generalities of how Icarus Verilog works. Write
some programs. Run some profiles.

On 02/18/2014 11:38 PM, Arun P wrote:
> Hi All,
> 
> This is Arun. I am trying to speed up Icarus Verilog with GPU
> parallel processing for my academic project. I am looking for help
> . Which source file I should start looking at or which part will be
> suitable to off-load to GPU ? I am totally clueless. Please share
> your thoughts.



- -- 
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."
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Re: [Iverilog-devel] Some Sample SystemVerilog programs

[Iztok J. <izt...@gm...>]

$ irun sv_unpacked_port.sv
irun: 13.10-s014: (c) Copyright 1995-2014 Cadence Design Systems, Inc.
file: sv_unpacked_port.sv
    module worklib.test:sv
        errors: 0, warnings: 0
    module worklib.main:sv
        errors: 0, warnings: 0
        Caching library 'worklib' ....... Done
    Elaborating the design hierarchy:
    Top level design units:
        main
    Building instance overlay tables: .................... Done
    Generating native compiled code:
        worklib.main:sv <0x1e933575>
            streams:   3, words:  2825
        worklib.test:sv <0x6e825af1>
            streams:   2, words:   349
    Building instance specific data structures.
    Loading native compiled code:     .................... Done
    Design hierarchy summary:
                     Instances  Unique
        Modules:             2       2
        Registers:           5       5
        Scalar wires:        1       -
        Vectored wires:      3       -
        Always blocks:       1       1
        Initial blocks:      1       1
        Pseudo assignments:  2       2
    Writing initial simulation snapshot: worklib.main:sv
Loading snapshot worklib.main:sv .................... Done
ncsim> source /tools/opt/cadence/INCISIV13.10.014/tools/inca/files/ncsimrc
ncsim> run
PASSED
ncsim: *W,RNQUIE: Simulation is complete.
ncsim> exit



On Tue, Feb 18, 2014 at 6:05 PM, Stephen Williams <st...@ic...> wrote:

> -----BEGIN PGP SIGNED MESSAGE-----
> Hash: SHA1
>
> On 02/18/2014 02:13 AM, Iztok Jeras wrote:
> > The 'sv_unpacked_port.sv <http://sv_unpacked_port.sv>' needed some
> > more changes. Array sizes where only the size [width-1], not the
> > range [width-1:0] are specified, are only allowed for the unpacked
> > part of the array, so on the right side. Also the address was
> > missing from the list in the display line. I did not check the
> > intention of the test.
>
> OK, The sv_unpacked_port.sv test needed more work, so I've attached
> an update. This should fix it, and it should display "PASSED".
>
> Thanks for running these tests.
> - --
> Steve Williams                "The woods are lovely, dark and deep.
> steve at icarus.com           But I have promises to keep,
> http://www.icarus.com         and lines to code before I sleep,
> http://www.picturel.com       And lines to code before I sleep."
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