iverilog-devel — Conversations on matters of Icarus Verilog development

[Iverilog-devel] iverilog - constant user function.

[<dp...@sw...>]

Hi All,

I am new to Verilog Xilinx and iverilog. 
I have made a design which builds OK in Xilinx ISE.

I am tiring to test if I can build this in Linux using iverilog.  

I am at the point now getting 

FIFO_GENERATOR_V8_2.v:3336: sorry: constant user functions are not currently supported: log2_val().
This is the original file from the Xilinx ISE 
Xilinx\14.7\ISE_DS\ISE\verilog\src\XilinxCoreLib\FIFO_GENERATOR_V8_2.v

Can you please give me some hint solving this ?

Assuming I manage to fix this is there a comand line tools in Linux able to implement bitstream for Xilinx XC6SLX9 devices

Thanks
Dimitar  

[Iverilog-devel] Assertion failure for system verilog structs

[<ni...@ly...>]

Hi,

I'm still trying to learn verilog and system verilog. This time playing
with struct (the idea is to define a combinatorial function which takes
an opcode and some other cpu state as input and returns a larger struct
more suitable for executing the instruction).

I'm using iverilog compiled from commit

  commit 437dc103416dd2bca99cccdaca4aacfec3411f36
  Merge: 102d2d5 d1dc98b
  Author: Stephen Williams <st...@ic...>
  Date:   Thu Mar 12 10:30:56 2015 -0700
  
      Merge pull request #55 from orsonmmz/const_record
      
      Const record

running on a debian gnu/linux box, x86_64. First I got compilation
failures with

  ex.vl:1: assert: pform_struct_type.cc:83: failed assertion 0
  Aborted

Looking up that line, it seems non-packed structs are not yet supported
(an error message saying so would be nicer than an assert...). So I
added the packed keyword, without understanding what it really means in
system verilog, and that made the compiler happy.

But now I get an assertion failure from vvp instead,

  vpi error: bad global property: 50
  vvp: vpi_priv.cc:281: int vpip_get_global(int): Assertion `0' failed.
  Aborted (core dumped)

The number 50 seems to be vpiAutomatic (from a call in sys_check_args).
But I'm a bit lost here. Backtrace is as follows:

  (gdb) bt
  #0  0x00007f6057bf8107 in __GI_raise (sig=sig@entry=6)
      at ../nptl/sysdeps/unix/sysv/linux/raise.c:56
  #1  0x00007f6057bf94e8 in __GI_abort () at abort.c:89
  #2  0x00007f6057bf1226 in __assert_fail_base (
      fmt=0x7f6057d27ce8 "%s%s%s:%u: %s%sAssertion `%s' failed.\n%n", 
      assertion=assertion@entry=0x4e188e "0", 
      file=file@entry=0x4e2c21 "vpi_priv.cc", line=line@entry=281, 
      function=function@entry=0x4e3690 <vpip_get_global(int)::__PRETTY_FUNCTION__> "int vpip_get_global(int)") at assert.c:92
  #3  0x00007f6057bf12d2 in __GI___assert_fail (assertion=0x4e188e "0", 
      file=0x4e2c21 "vpi_priv.cc", line=281, 
      function=0x4e3690 <vpip_get_global(int)::__PRETTY_FUNCTION__> "int vpip_get_global(int)") at assert.c:101
  #4  0x00000000004ac29f in vpip_get_global (property=50)
      at vpi_priv.cc:281
  #5  vpi_get (property=50, ref=0x0) at vpi_priv.cc:392
  #6  0x00000000004ac1b1 in vpi_get (property=50, ref=0x10eccd0)
      at vpi_priv.cc:406
  #7  0x00007f6057591bd2 in sys_check_args (callh=callh@entry=0x10ecf30, 
      argv=0x10c2f00, name=name@entry=0x7f60575b1106 "$monitor", 
      no_auto=no_auto@entry=1, is_monitor=is_monitor@entry=1)
      at sys_display.c:1076
  #8  0x00007f605759464e in sys_monitor_compiletf (
      name=0x7f60575b1106 "$monitor") at sys_display.c:1461
  #9  0x000000000045b616 in compile_cleanup () at compile.cc:784
  #10 0x0000000000442761 in main (argc=3, argv=0x7fff9180e368)
      at main.cc:457

My test and debugging code includes the command

     $monitor ("At time %t: pc: %x, instr: %x, instr_valid: %d\n  imm_value: %x, src_value: %x\n  imm_op: %d, prefix_active: %d, prefix: %x",
	       $time, main_cpu.pc, main_cpu.instr, main_cpu.instr_valid,
	       main_cpu.instr_op.imm_value, main_cpu.src_value,
	       main_cpu.instr_op.imm_op, main_cpu.prefix_active, main_cpu.prefix);

where main_cpu.instr_op is a struct type defined by

  typedef struct packed {
     bit [63:0] imm_value;
     bit        imm_op;
     bit        imm_sign;
     bit [3:0]  dreg;
     bit [3:0]  sreg;
     bit        write_dst;
     bit [3:0]  op_type;
     bit [3:0]  op;
  } DECODED_INSTR;

Dropping these references from the $monitor command makes the problem go
away, but then it is more difficult to track down the bugs in my own
code...

Best regards,
/Niels

-- 
Niels Möller. PGP-encrypted email is preferred. Keyid C0B98E26.
Internet email is subject to wholesale government surveillance.

Re: [Iverilog-devel] Update

[Maciej S. <mac...@ce...>]

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Excuse the lack of clarity. Steve got it right, I had problems with
regular (non-indexed) part selects, for example: local_data[ipn+8:ipn].

I have not used indexed part select before, therefore I am grateful to
Larry for his excellent suggestion. It is alread applied in the pull
request [1].

Regards,
Orson

1.
https://github.com/orsonmmz/iverilog/commit/d1dc98b7f73c21e4eae4bde91855ef5f41059dde

On 03/06/2015 11:14 PM, Stephen Williams wrote:
> 
> INDEXED part select can be non-constant. The width part of index
> part select must be strictly constant.
> 
> Regular part select indices must be strictly constant. I think if
> we don't use the work "indexed" then the part select is the regular
> kind. Is that really what you mean, Orson?
> 
> 
> On 03/06/2015 12:32 PM, Larry Doolittle wrote:
>> Orson -
> 
>> On Fri, Mar 06, 2015 at 08:57:35PM +0100, Maciej Sumiński wrote:
>>> I had to correct the previous implementation for accessing 
>>> constant arrays of vectors. I did not realize that ranges in
>>> part selection have to be constant, and variables are simply
>>> forbidden even if the difference between indices is constant.
>>> This makes the solution useless if one wants to implement e.g.
>>> a multiplexer.
> 
>> Maybe I don't fully understand the terminology, but I build 
>> multiplexers "all the time" using indexed part select, e.g.,
> 
>> module foo( input clk, input [3:0] ipn, output reg [7:0] ip1 );
>> reg [127:0] local_data; // stuff to set local_data not shown
>> always @(posedge clk) ip1 <= local_data[{ipn,3'b0}+:8];
>> endmodule
> 
>> - Larry
> 
>> ------------------------------------------------------------------------------
>
>> 
> 
> Dive into the World of Parallel Programming The Go Parallel
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> 
> 
> 
> 
> ------------------------------------------------------------------------------
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Re: [Iverilog-devel] Update

[Stephen W. <st...@ic...>]

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Hash: SHA1


INDEXED part select can be non-constant.
The width part of index part select must be strictly constant.

Regular part select indices must be strictly constant. I think
if we don't use the work "indexed" then the part select is the
regular kind. Is that really what you mean, Orson?


On 03/06/2015 12:32 PM, Larry Doolittle wrote:
> Orson -
> 
> On Fri, Mar 06, 2015 at 08:57:35PM +0100, Maciej Sumiński wrote:
>> I had to correct the previous implementation for accessing
>> constant arrays of vectors. I did not realize that ranges in part
>> selection have to be constant, and variables are simply forbidden
>> even if the difference between indices is constant. This makes
>> the solution useless if one wants to implement e.g. a
>> multiplexer.
> 
> Maybe I don't fully understand the terminology, but I build 
> multiplexers "all the time" using indexed part select, e.g.,
> 
> module foo( input clk, input [3:0] ipn, output reg [7:0] ip1 ); reg
> [127:0] local_data; // stuff to set local_data not shown always
> @(posedge clk) ip1 <= local_data[{ipn,3'b0}+:8]; endmodule
> 
> - Larry
> 
> ------------------------------------------------------------------------------
>
> 
Dive into the World of Parallel Programming The Go Parallel Website,
sponsored
> by Intel and developed in partnership with Slashdot Media, is your
> hub for all things parallel software development, from weekly
> thought leadership blogs to news, videos, case studies, tutorials
> and more. Take a look and join the conversation now.
> http://goparallel.sourceforge.net/ 
> _______________________________________________ Iverilog-devel
> mailing list Ive...@li... 
> https://lists.sourceforge.net/lists/listinfo/iverilog-devel
> 


- -- 
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."
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Re: [Iverilog-devel] Update

[Larry D. <ldo...@re...>]

Orson -

On Fri, Mar 06, 2015 at 08:57:35PM +0100, Maciej Sumiński wrote:
> I had to correct the previous implementation for accessing constant
> arrays of vectors. I did not realize that ranges in part selection have
> to be constant, and variables are simply forbidden even if the
> difference between indices is constant. This makes the solution useless
> if one wants to implement e.g. a multiplexer.

Maybe I don't fully understand the terminology, but I build
multiplexers "all the time" using indexed part select, e.g.,

module foo(
    input clk,
    input [3:0] ipn,
    output reg [7:0] ip1
);
reg [127:0] local_data;
// stuff to set local_data not shown
always @(posedge clk) ip1 <= local_data[{ipn,3'b0}+:8];
endmodule

  - Larry

Re: [Iverilog-devel] Update

[Maciej S. <mac...@ce...>]

I had to correct the previous implementation for accessing constant
arrays of vectors. I did not realize that ranges in part selection have
to be constant, and variables are simply forbidden even if the
difference between indices is constant. This makes the solution useless
if one wants to implement e.g. a multiplexer.

New pull request [1] resolves the problem by expanding the right side
value to a concatenation of selected signals. Also, the method has been
improved to handle constant records (and arrays of records or any other
combination).

There are $ivlh_{rising,falling}_edge() VPI functions to implement
VHDL's rising_edge() and falling_edge().

Attributes are evaluated to constants whenever possible. Thanks to that
it is possible to use quite common expressions as 'left and 'right as
index. Also generic parameters are evaluated whenever possible, as I
have found at least one case where the evaluation helped.

All the mentioned changes are supported with tests [2].

Have a nice weekend,
Orson

1. https://github.com/steveicarus/iverilog/pull/55
2. https://github.com/orsonmmz/ivtest/tree/const_record_test

Re: [Iverilog-devel] vvp runtime error

[Lonnie L G. <lg...@sr...>]

Hi Cary,

Do you know if this is in a snapshot yet. How can I check?

Thanks

Lonnie

 

From: Cary R. [mailto:cy...@ya...] 
Sent: Monday, February 02, 2015 6:27 PM
To: Discussions concerning Icarus Verilog development
Subject: Re: [Iverilog-devel] vvp runtime error

 

Okay, there are still a few other issues since nested replications do not correctly check for a zero replication at a lower level which was why I thought I may have to keep the zero width check. (e.g. {{2{{0{sign}}}}, 16'h0001} should report that a zero width (zero replication) cannot be replicated. A zero replication is only allowed in a concatenation/replication if it is also included with another non-zero width element. There are likely other degenerate cases (e.g. {{0{sign}}, {0{lsb}}}, etc.) that need to be checked and reported in the compiler.

 

And then all this needs to be check for constant and non-constant values being replicated. Constant-constant is done in the compiler, constant-variable is done in the run time.

 

Cary

 

On Monday, February 2, 2015 4:00 PM, Stephen Williams <st...@ic...> wrote:

 

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I kinda think this should be restricted to zero-replications,
and NOT zero-width expressions in general. I would rather catch
the latter is an error, or something.

On 02/02/2015 03:43 PM, Cary R. wrote:
> A patch for this has been pushed to git.
> 
> The issues was that zero replications inside of concatenations
> were generating incorrect vvp code for the new stack based vector
> operators. For the moment this code checks to see if the
> sub-expression width is zero. A more specific fix would check to
> see if the sub-expression was a concatenation that had a zero
> replication. I can easily change the code if needed, but the zero
> width may be better if other things can also generate a zero width
> result. I don't know of any, but there may be SystemVerilog
> constructs that can do this. Does anyone have an opinion on this or
> know of a construct that can do this?
> 
> Cary
> 
> 
> On Monday, February 2, 2015 10:20 AM, Cary R. <cy...@ya...>
> wrote:
> 
> 
> Hi Lonnie,
> 
> I was able to reduce this example down even further. It looks like
> the problem is that when Steve switched to the new stack code
> something broke concerning zero replications. At the moment an
> input width of 32 is getting a sign bit added which gives a width
> of 33 instead of 32. I will try to look at this later today.
> 
> Cary
> 
> 
> On Monday, February 2, 2015 9:03 AM, Lonnie Gliem 
> <lg...@sr...> wrote:
> 
> 
> Hi Cary, I found the code causing the error and have attahced a
> small verilog file that causes it.
> 
> iverilog iverilog_core.v
> 
> Then run it. [lgliem@ajax <mailto:lgliem@ajax> ulogic_sim]$


> ./a.out Fun: 0x7ba500 is for variable clk Fun: 0x7ba550 is for
> variable data_in_tmp Current vector
> is:32'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX New value
> is:33'bZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ vvp: vvp_net_sig.cc:185:
> virtual void vvp_fun_signal4_sa::recv_vec4(vvp_net_ptr_t, const
> vvp_vector4_t&, void**): Assertion `bit.size() == bits4_.size()'
> failed. Aborted (core dumped)
> 
> Lonnie


> 
> 
> 
> 
> 
> 
> 
> ------------------------------------------------------------------------------
>
> 
Dive into the World of Parallel Programming. The Go Parallel Website,
> sponsored by Intel and developed in partnership with Slashdot
> Media, is your hub for all things parallel software development,
> from weekly thought leadership blogs to news, videos, case studies,
> tutorials and more. Take a look and join the conversation now.
> http://goparallel.sourceforge.net/
> 
> 
> 
> _______________________________________________ Iverilog-devel
> mailing list Ive...@li... 
> https://lists.sourceforge.net/lists/listinfo/iverilog-devel
> 


- -- 
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com          But I have promises to keep,
http://www.icarus.com  <http://www.icarus.com/>         and lines to code before I sleep,
http://www.picturel.com  <http://www.picturel.com/>       And lines to code before I sleep."
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Re: [Iverilog-devel] The string type and $value$plusargs

[<ni...@ly...>]

"Cary R." <cy...@ya...> writes:

> I have pushed a patch that fixes the oversight in updating the
> plusargs routine to allow SV strings and add support to put a string
> value to a SV string from the VPI. If you get the latest code from git
> this should now work correctly.

I've tested it now, and I can confirm that it works fine. To recap, the
usecase was

   string img;
   if (!$value$plusargs("img=%s", img)) begin
      $display("Specify image file with +img=<image>.");
      $finish_and_return(1);
   end
   $readmemh(img, main_storage.mem);

Thanks!
/Niels

-- 
Niels Möller. PGP-encrypted email is preferred. Keyid C0B98E26.
Internet email is subject to wholesale government surveillance.

Re: [Iverilog-devel] The string type and $value$plusargs

[Cary R. <cy...@ya...>]

I have pushed a patch that fixes the oversight in updating the plusargs routine to allow SV strings and add support to put a string value to a SV string from the VPI. If you get the latest code from git this should now work correctly.
Cary
 

     On Wednesday, February 25, 2015 6:12 PM, Cary R. <cy...@ya...> wrote:
   

 Hi Niels,
Yes this should work. The problem is the plusargs code was not updated to know that a SystemVerilog string is a variable. Once that was done there is still a problem in that the string is not being updated correctly. I will look at why that is next and post again when I have this working correctly.

Interfaces are not currently supported in Icarus. Once they are I hope that the vlog95 code generator can be enhanced to emit them as normal Verilog. I think it will work, but the internal representation may put constraints on how well that will work.
Cary
 

     On Tuesday, February 10, 2015 6:35 AM, Niels Möller <ni...@ly...> wrote:
   

 I'm now trying to read a memory dump, using a command line argument for
the file name (as hinted at the end of
http://iverilog.wikia.com/wiki/Simulation).

System verilog has a string type, so I tried this program,

  module main;
    reg [64:0] mem [0:100];
    string img;
    initial begin
        if (!$value$plusargs("img=%s", img)) begin
          $display("Specify image file with +img=<image>.");
          $finish_and_return(1);
        end
        $display("Using image: %s", img);
        $readmemh(img, mem);      
        $display("Initial memory word: mem[0] = %x", mem[0]);
        $finish;
    end
  endmodule // main

I compile using

  $ iverilog -g2005-sv main.vl -o main

(with iverilog compiled from git eariler today). Works fine, so far. But
running it fails,

  $ ./main +img=../examples/hello.hex
  ERROR: main.vl:5: $value$plusargs's second argument must be a variable, found a vpiStringVar.

If I change "string img;" to "reg [300:0] img;" it works, and I get the output

  Using image:                  ../examples/hello.hex
  WARNING: main.vl:10: $readmemh(../examples/hello.hex): Not enough words in the file for the requested range [0:100].
  Initial memory word: mem[0] = 07000b4a08408e500

But that doesn't seem like a very good solution, since I have to put an
arbitrary size on the register, and it will fail with filenames which
exceed this size.

If I try the System verilog support in iverilog (primarily, I would like
to use the interface abstraction), I should be able to use the vlog95
target to generate plain verilog code which I could feed to, e.g.,
yosys, right?

Regards,
/Niels

-- 
Niels Möller. PGP-encrypted email is preferred. Keyid C0B98E26.
Internet email is subject to wholesale government surveillance.


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hub for all things parallel software development, from weekly thought
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_______________________________________________
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Re: [Iverilog-devel] The string type and $value$plusargs

[Cary R. <cy...@ya...>]

Hi Niels,
Yes this should work. The problem is the plusargs code was not updated to know that a SystemVerilog string is a variable. Once that was done there is still a problem in that the string is not being updated correctly. I will look at why that is next and post again when I have this working correctly.

Interfaces are not currently supported in Icarus. Once they are I hope that the vlog95 code generator can be enhanced to emit them as normal Verilog. I think it will work, but the internal representation may put constraints on how well that will work.
Cary
 

     On Tuesday, February 10, 2015 6:35 AM, Niels Möller <ni...@ly...> wrote:
   

 I'm now trying to read a memory dump, using a command line argument for
the file name (as hinted at the end of
http://iverilog.wikia.com/wiki/Simulation).

System verilog has a string type, so I tried this program,

  module main;
    reg [64:0] mem [0:100];
    string img;
    initial begin
        if (!$value$plusargs("img=%s", img)) begin
          $display("Specify image file with +img=<image>.");
          $finish_and_return(1);
        end
        $display("Using image: %s", img);
        $readmemh(img, mem);      
        $display("Initial memory word: mem[0] = %x", mem[0]);
        $finish;
    end
  endmodule // main

I compile using

  $ iverilog -g2005-sv main.vl -o main

(with iverilog compiled from git eariler today). Works fine, so far. But
running it fails,

  $ ./main +img=../examples/hello.hex
  ERROR: main.vl:5: $value$plusargs's second argument must be a variable, found a vpiStringVar.

If I change "string img;" to "reg [300:0] img;" it works, and I get the output

  Using image:                  ../examples/hello.hex
  WARNING: main.vl:10: $readmemh(../examples/hello.hex): Not enough words in the file for the requested range [0:100].
  Initial memory word: mem[0] = 07000b4a08408e500

But that doesn't seem like a very good solution, since I have to put an
arbitrary size on the register, and it will fail with filenames which
exceed this size.

If I try the System verilog support in iverilog (primarily, I would like
to use the interface abstraction), I should be able to use the vlog95
target to generate plain verilog code which I could feed to, e.g.,
yosys, right?

Regards,
/Niels

-- 
Niels Möller. PGP-encrypted email is preferred. Keyid C0B98E26.
Internet email is subject to wholesale government surveillance.


------------------------------------------------------------------------------
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hub for all things parallel software development, from weekly thought
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look and join the conversation now. http://goparallel.sourceforge.net/
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[Iverilog-devel] Update

[Maciej S. <mac...@ce...>]

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Hash: SHA256

Hi Steve,

I have another update[1] along with tests[2] that brings:
- - enum can be used as a port type in modules (SystemVerilog)
- - shift operators (SRL/SLL/SRA/SLA) (VHDL)
- - labeled assignments (VHDL)
- - fixed accessing words in constant arrays of vectors (VHDL)
- - 'natural' type translated as 'int unsigned' (VHDL)
- - a bunch of minor fixes

The implementation of the fourth point may seem a bit twisted,
therefore deserves a word of explanation:

Currently, constant arrays of vectors are flattened to single
one-dimensional localparams, as there is no support for constant
unpacked arrays. Therefore, if the user wants to access a particular
word, then it is necessary to extract the adequate part of the
localparam, and it is done by adjusting the indices. Without the
adjustment, only a single bit would be returned.
To give an example:

== VHDL ==
type uns_array is array (natural range <>) of unsigned(7 downto 0);

constant const_array : uns_array(2 downto 0) :=
    (0 => "00110011", 1 => "101010101", 2=> "00001111");

target_var := const_array(1);

== SystemVerilog ==
localparam const_array = { 8'b00110011, 8'b10101010, 8'b00001111 };

target_var = const_array[15:8]; // <- indices adjusted to pick the word

It can be easily changed once the unpacked constant arrays are supported.

Regards,
Orson

1. https://github.com/steveicarus/iverilog/pull/54
2. https://github.com/orsonmmz/ivtest/tree/const_array_test
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Re: [Iverilog-devel] System Verilog and interfaces

[<ni...@ly...>]

Martin Whitaker <mai...@ma...> writes:

> I'm working on adding support for interfaces as and when I have free
> time.

I really appreciate that. And I take it the progress will be reported on
this list.

Thanks,
/Niels

-- 
Niels Möller. PGP-encrypted email is preferred. Keyid C0B98E26.
Internet email is subject to wholesale government surveillance.

Re: [Iverilog-devel] System Verilog and interfaces

[Martin W. <mai...@ma...>]

I'm working on adding support for interfaces as and when I have free time. As 
you have found, at present you can define and instantiate an interface, but 
nothing more.

ni...@ly... (Niels Möller) wrote:
> Speaking of System Verilog and interfaces, what's the current status of
> System Verilog support?
>
> Consider the first example on
> http://www.doulos.com/knowhow/sysverilog/tutorial/interfaces/, which
> could be cut down a bit to the following:
>
>    // Interface definition
>    interface Bus;
>      logic [7:0] Addr, Data;
>      logic RWn;
>    endinterface
>
>    module RAM (Bus MemBus); /* ! */
>    endmodule
>
> This gives a syntax error on the line marked /* ! */,
>
>    $ iverilog -g2005-sv interface.vl
>    interface.vl:7: syntax error
>    interface.vl:7: Errors in port declarations.
>
> I had a quick look in the source code, and I see nothing in parse.y to
> allow a named interface as a data type. I'm a bit in the dark as to how
> these things work. Maybe pform.cc:pform_test_type_identifier should look
> up known interfaces? In the grammar for the non-terminal
> port_declaration, it looks like a named interface, which I guess is just
> an IDENTIFIER to the lexer, ought to be parsed as part of the
> data_type_or_implicit non-terminal.
>
> Currently, it seems defining an interface (at top-level) adds the
> interface to pform_modules, as an instance of Module with is_interface
> == true. While defining other types (typedef, struct, or class) adds an
> entry to pform_typedefs.
>
> Regards,
> /Niels
>

[Iverilog-devel] System Verilog and interfaces

[<ni...@ly...>]

Speaking of System Verilog and interfaces, what's the current status of
System Verilog support?

Consider the first example on
http://www.doulos.com/knowhow/sysverilog/tutorial/interfaces/, which
could be cut down a bit to the following:

  // Interface definition
  interface Bus;
    logic [7:0] Addr, Data;
    logic RWn;
  endinterface
  
  module RAM (Bus MemBus); /* ! */
  endmodule

This gives a syntax error on the line marked /* ! */,

  $ iverilog -g2005-sv interface.vl
  interface.vl:7: syntax error
  interface.vl:7: Errors in port declarations.

I had a quick look in the source code, and I see nothing in parse.y to
allow a named interface as a data type. I'm a bit in the dark as to how
these things work. Maybe pform.cc:pform_test_type_identifier should look
up known interfaces? In the grammar for the non-terminal
port_declaration, it looks like a named interface, which I guess is just
an IDENTIFIER to the lexer, ought to be parsed as part of the
data_type_or_implicit non-terminal.

Currently, it seems defining an interface (at top-level) adds the
interface to pform_modules, as an instance of Module with is_interface
== true. While defining other types (typedef, struct, or class) adds an
entry to pform_typedefs.

Regards,
/Niels

-- 
Niels Möller. PGP-encrypted email is preferred. Keyid C0B98E26.
Internet email is subject to wholesale government surveillance.

[Iverilog-devel] The string type and $value$plusargs

[<ni...@ly...>]

I'm now trying to read a memory dump, using a command line argument for
the file name (as hinted at the end of
http://iverilog.wikia.com/wiki/Simulation).

System verilog has a string type, so I tried this program,

  module main;
     reg [64:0] mem [0:100];
     string img;
     initial begin
        if (!$value$plusargs("img=%s", img)) begin
           $display("Specify image file with +img=<image>.");
           $finish_and_return(1);
        end
        $display("Using image: %s", img);
        $readmemh(img, mem);      
        $display("Initial memory word: mem[0] = %x", mem[0]);
        $finish;
     end
  endmodule // main

I compile using

  $ iverilog -g2005-sv main.vl -o main

(with iverilog compiled from git eariler today). Works fine, so far. But
running it fails,

  $ ./main +img=../examples/hello.hex
  ERROR: main.vl:5: $value$plusargs's second argument must be a variable, found a vpiStringVar.

If I change "string img;" to "reg [300:0] img;" it works, and I get the output

  Using image:                  ../examples/hello.hex
  WARNING: main.vl:10: $readmemh(../examples/hello.hex): Not enough words in the file for the requested range [0:100].
  Initial memory word: mem[0] = 07000b4a08408e500

But that doesn't seem like a very good solution, since I have to put an
arbitrary size on the register, and it will fail with filenames which
exceed this size.

If I try the System verilog support in iverilog (primarily, I would like
to use the interface abstraction), I should be able to use the vlog95
target to generate plain verilog code which I could feed to, e.g.,
yosys, right?

Regards,
/Niels

-- 
Niels Möller. PGP-encrypted email is preferred. Keyid C0B98E26.
Internet email is subject to wholesale government surveillance.

[Iverilog-devel] Unbounded vectors in VHDL functions

[Maciej S. <mac...@ce...>]

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA256

Hereby I would like to gleefully announce that I have just completed
the quest for the Unbounded Vectors in Functions in VHDL [1,2]. It was
the most challenging task so far, and even though the path was long
and full of thorns, the Mt Doom is still far ahead. Drenched with
faith, I continue the adventure to confront VHDL gremlins..

It turned out that casting between dynamic arrays and vectors does not
solve the problem, as it requires dynamic memory allocation which is not
feasible for continuous assignments. Maybe it could have been solved
with a bit of VPI sorcery, but the gain is not worth it.

Once I had implemented the mentioned solution and discovered its
problem, I switched to the other idea: function instances. It also has
its limitations, but IMHO much more reasonable. It will not allow to
return vectors of different sizes, if the size depends on the execution
path. For example:

if a > b then
  return B"1001";
else
  return B"1001010101";

Fortunately, I have never seen such code in real-life examples.

One minor addition is support for case statements alternatives with
multiple choices in VHDL (e.g. "when A|B|C|D =>").

The pull request also includes the previously proposed changes (mostly
related to type casting and dynamic arrays in SystemVerilog), with one
problematic commit excluded (dynamic arrays with words of arbitrary size).

Regards,
Orson

1. https://github.com/steveicarus/iverilog/pull/52
2. https://github.com/orsonmmz/ivtest/tree/unbounded_function_test
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Re: [Iverilog-devel] vvp runtime error

[Martin W. <mai...@ma...>]

Cary R. wrote:
> Okay, there are still a few other issues since nested replications do not
> correctly check for a zero replication at a lower level which was why I
> thought I may have to keep the zero width check. (e.g. {{2{{0{sign}}}},
> 16'h0001} should report that a zero width (zero replication) cannot be
> replicated. A zero replication is only allowed in a
> concatenation/replication if it is also included with another non-zero
> width element. There are likely other degenerate cases (e.g. {{0{sign}},
> {0{lsb}}}, etc.) that need to be checked and reported in the compiler.
>
> And then all this needs to be check for constant and non-constant values
> being replicated. Constant-constant is done in the compiler,
> constant-variable is done in the run time. Cary

Another case that bypasses the zero replication check is a concatenation 
within a concatenation, e.g. {a, b & {0{c}}}.

I'd try fixing the compiler check by using the elab_expr flags to flag
whether we are elaborating a singleton concatenation (I can have a go at this 
if you don't have time).

Trying some other things, I find Icarus accepts a zero width literal number 
(which isn't legal Verilog). It then gives different results for {a, 0'b0, b} 
and {a, {0'b0}, b}. The first case is sensible (collapses to {a, b}), the 
second case is not.

Martin

Re: [Iverilog-devel] vvp runtime error

[Lonnie L G. <lg...@sr...>]

Hi Cary,

How long until this fix will show up in a src.rpm?

Lonnie

 

From: Cary R. [mailto:cy...@ya...] 
Sent: Monday, February 02, 2015 6:27 PM
To: Discussions concerning Icarus Verilog development
Subject: Re: [Iverilog-devel] vvp runtime error

 

Okay, there are still a few other issues since nested replications do not correctly check for a zero replication at a lower level which was why I thought I may have to keep the zero width check. (e.g. {{2{{0{sign}}}}, 16'h0001} should report that a zero width (zero replication) cannot be replicated. A zero replication is only allowed in a concatenation/replication if it is also included with another non-zero width element. There are likely other degenerate cases (e.g. {{0{sign}}, {0{lsb}}}, etc.) that need to be checked and reported in the compiler.

 

And then all this needs to be check for constant and non-constant values being replicated. Constant-constant is done in the compiler, constant-variable is done in the run time.

 

Cary

 

On Monday, February 2, 2015 4:00 PM, Stephen Williams <st...@ic...> wrote:

 

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1


I kinda think this should be restricted to zero-replications,
and NOT zero-width expressions in general. I would rather catch
the latter is an error, or something.

On 02/02/2015 03:43 PM, Cary R. wrote:
> A patch for this has been pushed to git.
> 
> The issues was that zero replications inside of concatenations
> were generating incorrect vvp code for the new stack based vector
> operators. For the moment this code checks to see if the
> sub-expression width is zero. A more specific fix would check to
> see if the sub-expression was a concatenation that had a zero
> replication. I can easily change the code if needed, but the zero
> width may be better if other things can also generate a zero width
> result. I don't know of any, but there may be SystemVerilog
> constructs that can do this. Does anyone have an opinion on this or
> know of a construct that can do this?
> 
> Cary
> 
> 
> On Monday, February 2, 2015 10:20 AM, Cary R. <cy...@ya...>
> wrote:
> 
> 
> Hi Lonnie,
> 
> I was able to reduce this example down even further. It looks like
> the problem is that when Steve switched to the new stack code
> something broke concerning zero replications. At the moment an
> input width of 32 is getting a sign bit added which gives a width
> of 33 instead of 32. I will try to look at this later today.
> 
> Cary
> 
> 
> On Monday, February 2, 2015 9:03 AM, Lonnie Gliem 
> <lg...@sr...> wrote:
> 
> 
> Hi Cary, I found the code causing the error and have attahced a
> small verilog file that causes it.
> 
> iverilog iverilog_core.v
> 
> Then run it. [lgliem@ajax <mailto:lgliem@ajax> ulogic_sim]$


> ./a.out Fun: 0x7ba500 is for variable clk Fun: 0x7ba550 is for
> variable data_in_tmp Current vector
> is:32'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX New value
> is:33'bZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ vvp: vvp_net_sig.cc:185:
> virtual void vvp_fun_signal4_sa::recv_vec4(vvp_net_ptr_t, const
> vvp_vector4_t&, void**): Assertion `bit.size() == bits4_.size()'
> failed. Aborted (core dumped)
> 
> Lonnie


> 
> 
> 
> 
> 
> 
> 
> ------------------------------------------------------------------------------
>
> 
Dive into the World of Parallel Programming. The Go Parallel Website,
> sponsored by Intel and developed in partnership with Slashdot
> Media, is your hub for all things parallel software development,
> from weekly thought leadership blogs to news, videos, case studies,
> tutorials and more. Take a look and join the conversation now.
> http://goparallel.sourceforge.net/
> 
> 
> 
> _______________________________________________ Iverilog-devel
> mailing list Ive...@li... 
> https://lists.sourceforge.net/lists/listinfo/iverilog-devel
> 


- -- 
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com          But I have promises to keep,
http://www.icarus.com  <http://www.icarus.com/>         and lines to code before I sleep,
http://www.picturel.com  <http://www.picturel.com/>       And lines to code before I sleep."
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------------------------------------------------------------------------------
Dive into the World of Parallel Programming. The Go Parallel Website,
sponsored by Intel and developed in partnership with Slashdot Media, is your
hub for all things parallel software development, from weekly thought
leadership blogs to news, videos, case studies, tutorials and more. Take a
look and join the conversation now. http://goparallel.sourceforge.net/
_______________________________________________
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Ive...@li...
https://lists.sourceforge.net/lists/listinfo/iverilog-devel

 

 

Re: [Iverilog-devel] vvp runtime error

[Cary R. <cy...@ya...>]

Okay, there are still a few other issues since nested replications do not correctly check for a zero replication at a lower level which was why I thought I may have to keep the zero width check. (e.g. {{2{{0{sign}}}}, 16'h0001} should report that a zero width (zero replication) cannot be replicated. A zero replication is only allowed in a concatenation/replication if it is also included with another non-zero width element. There are likely other degenerate cases (e.g. {{0{sign}}, {0{lsb}}}, etc.) that need to be checked and reported in the compiler.

And then all this needs to be check for constant and non-constant values being replicated. Constant-constant is done in the compiler, constant-variable is done in the run time.
Cary


     On Monday, February 2, 2015 4:00 PM, Stephen Williams <st...@ic...> wrote:
   

 -----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1


I kinda think this should be restricted to zero-replications,
and NOT zero-width expressions in general. I would rather catch
the latter is an error, or something.

On 02/02/2015 03:43 PM, Cary R. wrote:
> A patch for this has been pushed to git.
> 
> The issues was that zero replications inside of concatenations
> were generating incorrect vvp code for the new stack based vector
> operators. For the moment this code checks to see if the
> sub-expression width is zero. A more specific fix would check to
> see if the sub-expression was a concatenation that had a zero
> replication. I can easily change the code if needed, but the zero
> width may be better if other things can also generate a zero width
> result. I don't know of any, but there may be SystemVerilog
> constructs that can do this. Does anyone have an opinion on this or
> know of a construct that can do this?
> 
> Cary
> 
> 
> On Monday, February 2, 2015 10:20 AM, Cary R. <cy...@ya...>
> wrote:
> 
> 
> Hi Lonnie,
> 
> I was able to reduce this example down even further. It looks like
> the problem is that when Steve switched to the new stack code
> something broke concerning zero replications. At the moment an
> input width of 32 is getting a sign bit added which gives a width
> of 33 instead of 32. I will try to look at this later today.
> 
> Cary
> 
> 
> On Monday, February 2, 2015 9:03 AM, Lonnie Gliem 
> <lg...@sr...> wrote:
> 
> 
> Hi Cary, I found the code causing the error and have attahced a
> small verilog file that causes it.
> 
> iverilog iverilog_core.v
> 
> Then run it. [lgliem@ajax <mailto:lgliem@ajax> ulogic_sim]$
> ./a.out Fun: 0x7ba500 is for variable clk Fun: 0x7ba550 is for
> variable data_in_tmp Current vector
> is:32'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX New value
> is:33'bZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ vvp: vvp_net_sig.cc:185:
> virtual void vvp_fun_signal4_sa::recv_vec4(vvp_net_ptr_t, const
> vvp_vector4_t&, void**): Assertion `bit.size() == bits4_.size()'
> failed. Aborted (core dumped)
> 
> Lonnie
> 
> 
> 
> 
> 
> 
> 
> ------------------------------------------------------------------------------
>
> 
Dive into the World of Parallel Programming. The Go Parallel Website,
> sponsored by Intel and developed in partnership with Slashdot
> Media, is your hub for all things parallel software development,
> from weekly thought leadership blogs to news, videos, case studies,
> tutorials and more. Take a look and join the conversation now.
> http://goparallel.sourceforge.net/
> 
> 
> 
> _______________________________________________ Iverilog-devel
> mailing list Ive...@li... 
> https://lists.sourceforge.net/lists/listinfo/iverilog-devel
> 


- -- 
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com          But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."
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=qK5u
-----END PGP SIGNATURE-----

------------------------------------------------------------------------------
Dive into the World of Parallel Programming. The Go Parallel Website,
sponsored by Intel and developed in partnership with Slashdot Media, is your
hub for all things parallel software development, from weekly thought
leadership blogs to news, videos, case studies, tutorials and more. Take a
look and join the conversation now. http://goparallel.sourceforge.net/
_______________________________________________
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https://lists.sourceforge.net/lists/listinfo/iverilog-devel


   

Re: [Iverilog-devel] vvp runtime error

[Stephen W. <st...@ic...>]

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1


I kinda think this should be restricted to zero-replications,
and NOT zero-width expressions in general. I would rather catch
the latter is an error, or something.

On 02/02/2015 03:43 PM, Cary R. wrote:
> A patch for this has been pushed to git.
> 
> The issues was that zero replications inside of concatenations
> were generating incorrect vvp code for the new stack based vector
> operators. For the moment this code checks to see if the
> sub-expression width is zero. A more specific fix would check to
> see if the sub-expression was a concatenation that had a zero
> replication. I can easily change the code if needed, but the zero
> width may be better if other things can also generate a zero width
> result. I don't know of any, but there may be SystemVerilog
> constructs that can do this. Does anyone have an opinion on this or
> know of a construct that can do this?
> 
> Cary
> 
> 
> On Monday, February 2, 2015 10:20 AM, Cary R. <cy...@ya...>
> wrote:
> 
> 
> Hi Lonnie,
> 
> I was able to reduce this example down even further. It looks like
> the problem is that when Steve switched to the new stack code
> something broke concerning zero replications. At the moment an
> input width of 32 is getting a sign bit added which gives a width
> of 33 instead of 32. I will try to look at this later today.
> 
> Cary
> 
> 
> On Monday, February 2, 2015 9:03 AM, Lonnie Gliem 
> <lg...@sr...> wrote:
> 
> 
> Hi Cary, I found the code causing the error and have attahced a
> small verilog file that causes it.
> 
> iverilog iverilog_core.v
> 
> Then run it. [lgliem@ajax <mailto:lgliem@ajax> ulogic_sim]$
> ./a.out Fun: 0x7ba500 is for variable clk Fun: 0x7ba550 is for
> variable data_in_tmp Current vector
> is:32'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX New value
> is:33'bZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ vvp: vvp_net_sig.cc:185:
> virtual void vvp_fun_signal4_sa::recv_vec4(vvp_net_ptr_t, const
> vvp_vector4_t&, void**): Assertion `bit.size() == bits4_.size()'
> failed. Aborted (core dumped)
> 
> Lonnie
> 
> 
> 
> 
> 
> 
> 
> ------------------------------------------------------------------------------
>
> 
Dive into the World of Parallel Programming. The Go Parallel Website,
> sponsored by Intel and developed in partnership with Slashdot
> Media, is your hub for all things parallel software development,
> from weekly thought leadership blogs to news, videos, case studies,
> tutorials and more. Take a look and join the conversation now.
> http://goparallel.sourceforge.net/
> 
> 
> 
> _______________________________________________ Iverilog-devel
> mailing list Ive...@li... 
> https://lists.sourceforge.net/lists/listinfo/iverilog-devel
> 


- -- 
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."
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=qK5u
-----END PGP SIGNATURE-----

Re: [Iverilog-devel] vvp runtime error

[Cary R. <cy...@ya...>]

A patch for this has been pushed to git.
The issues was that zero replications inside of concatenations were generating incorrect vvp code for the new stack based vector operators. For the moment this code checks to see if the sub-expression width is zero. A more specific fix would check to see if the sub-expression was a concatenation that had a zero replication. I can easily change the code if needed, but the zero width may be better if other things can also generate a zero width result. I don't know of any, but there may be SystemVerilog constructs that can do this. Does anyone have an opinion on this or know of a construct that can do this?
Cary 

     On Monday, February 2, 2015 10:20 AM, Cary R. <cy...@ya...> wrote:
   

 Hi Lonnie,
I was able to reduce this example down even further. It looks like the problem is that when Steve switched to the new stack code something broke concerning zero replications. At the moment an input width of 32 is getting a sign bit added which gives a width of 33 instead of 32. I will try to look at this later today.

Cary
 

     On Monday, February 2, 2015 9:03 AM, Lonnie Gliem <lg...@sr...> wrote:
   

 Hi Cary,
I found the code causing the error and have attahced a small verilog
file that causes it. 

iverilog iverilog_core.v 

Then run it. 
[lgliem@ajax ulogic_sim]$ ./a.out
Fun: 0x7ba500 is for variable clk
Fun: 0x7ba550 is for variable data_in_tmp
Current vector is:32'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
New value is:33'bZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ
vvp: vvp_net_sig.cc:185: virtual void
vvp_fun_signal4_sa::recv_vec4(vvp_net_ptr_t, const vvp_vector4_t&,
void**): Assertion `bit.size() == bits4_.size()' failed.
Aborted (core dumped)

Lonnie



    

    

Re: [Iverilog-devel] vvp runtime error

[Cary R. <cy...@ya...>]

Hi Lonnie,
I was able to reduce this example down even further. It looks like the problem is that when Steve switched to the new stack code something broke concerning zero replications. At the moment an input width of 32 is getting a sign bit added which gives a width of 33 instead of 32. I will try to look at this later today.

Cary
 

     On Monday, February 2, 2015 9:03 AM, Lonnie Gliem <lg...@sr...> wrote:
   

 Hi Cary,
I found the code causing the error and have attahced a small verilog
file that causes it. 

iverilog iverilog_core.v 

Then run it. 
[lgliem@ajax ulogic_sim]$ ./a.out
Fun: 0x7ba500 is for variable clk
Fun: 0x7ba550 is for variable data_in_tmp
Current vector is:32'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
New value is:33'bZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ
vvp: vvp_net_sig.cc:185: virtual void
vvp_fun_signal4_sa::recv_vec4(vvp_net_ptr_t, const vvp_vector4_t&,
void**): Assertion `bit.size() == bits4_.size()' failed.
Aborted (core dumped)

Lonnie



    

Re: [Iverilog-devel] vvp runtime error

[Lonnie G. <lg...@sr...>]

Hi Cary,
I found the code causing the error and have attahced a small verilog
file that causes it. 

iverilog iverilog_core.v 

Then run it. 
[lgliem@ajax ulogic_sim]$ ./a.out
Fun: 0x7ba500 is for variable clk
Fun: 0x7ba550 is for variable data_in_tmp
Current vector is:32'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
New value is:33'bZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ
vvp: vvp_net_sig.cc:185: virtual void
vvp_fun_signal4_sa::recv_vec4(vvp_net_ptr_t, const vvp_vector4_t&,
void**): Assertion `bit.size() == bits4_.size()' failed.
Aborted (core dumped)

Lonnie

Re: [Iverilog-devel] vvp runtime error

[Cary R. <cy...@ya...>]

Good point Martin,
Lonnie says that this was working in the 20140801 snapshot so this is something relatively recent.
Cary
 

     On Wednesday, January 28, 2015 1:50 PM, Martin Whitaker <mai...@ma...> wrote:
   

 Cary R. wrote:
> The iverilog flag Steve mentioned is -pfileline=1. This will help if the
> problem is in the procedural code, but does nothing for continuous
> assignments.

If -pfileline=1 doesn't help, I resort to gdb and a stack trace, e.g.

shell> gdb vvp
gdb>  run a.out
gdb>  bt

(where a.out is the compiled Verilog). The call chain that led to the assert 
can give some clues to what was responsible for the fault.

Martin


   

Re: [Iverilog-devel] vvp runtime error

[Martin W. <mai...@ma...>]

Cary R. wrote:
> The iverilog flag Steve mentioned is -pfileline=1. This will help if the
> problem is in the procedural code, but does nothing for continuous
> assignments.

If -pfileline=1 doesn't help, I resort to gdb and a stack trace, e.g.

shell> gdb vvp
gdb>   run a.out
gdb>   bt

(where a.out is the compiled Verilog). The call chain that led to the assert 
can give some clues to what was responsible for the fault.

Martin