iverilog-devel — Conversations on matters of Icarus Verilog development

Re: [Iverilog-devel] Thinking of Icarus Verilog 10

[Martin W. <mai...@ma...>]

Stephen Williams wrote:
> -----BEGIN PGP SIGNED MESSAGE-----
> Hash: SHA1
>
>
> I know this has been discussed before, but I want to bring it up
> again. I think we are due for a new release.
>
> I've been noting that a huge portion of users are finding that
> their needs are met by recent snapshots that are not otherwise
> handled by the 0.9 release. We've been spending some amount of
> our support time just telling people that "it's been fixed" in
> the master branch.
>
> But there are many users out there who get their Icarus Verilog
> fix from package managers, and so are using the 0.9 release. These
> people are not particularly motivated to build from source, and
> after all they shouldn't need to. Our making a release is our
> way to say that this is what we recommend.
>
> Since we've been recommending git master for a while now, maybe
> it is time to make a release.
>
You know this will get my vote! Development is a huge advance over v0.9 - time 
to get it in the hands of all our users.

Martin

Re: [Iverilog-devel] Thinking of Icarus Verilog 10

[<dp...@sw...>]

Hello,

I am very new to Icarus so I am not in a position to say something in this 
thread.

But just to mentioned that I needed  "Constant user functions" support so I 
had to compile the trunk.

Best Regards
Dimitar



-----Original Message----- 
From: Stephen Williams
Sent: Wednesday, April 8, 2015 23:38
To: Discussions concerning Icarus Verilog development
Subject: [Iverilog-devel] Thinking of Icarus Verilog 10

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1


I know this has been discussed before, but I want to bring it up
again. I think we are due for a new release.

I've been noting that a huge portion of users are finding that
their needs are met by recent snapshots that are not otherwise
handled by the 0.9 release. We've been spending some amount of
our support time just telling people that "it's been fixed" in
the master branch.

But there are many users out there who get their Icarus Verilog
fix from package managers, and so are using the 0.9 release. These
people are not particularly motivated to build from source, and
after all they shouldn't need to. Our making a release is our
way to say that this is what we recommend.

Since we've been recommending git master for a while now, maybe
it is time to make a release.

Also, name change. Rather then go to 0.10.x, let's simple call
it version 10. Somewhere along the line, Icarus Verilog became
production ready while we weren't looking. I think the leading
zero is no longer informative.

- -- 
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."
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[Iverilog-devel] Thinking of Icarus Verilog 10

[Stephen W. <st...@ic...>]

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Hash: SHA1


I know this has been discussed before, but I want to bring it up
again. I think we are due for a new release.

I've been noting that a huge portion of users are finding that
their needs are met by recent snapshots that are not otherwise
handled by the 0.9 release. We've been spending some amount of
our support time just telling people that "it's been fixed" in
the master branch.

But there are many users out there who get their Icarus Verilog
fix from package managers, and so are using the 0.9 release. These
people are not particularly motivated to build from source, and
after all they shouldn't need to. Our making a release is our
way to say that this is what we recommend.

Since we've been recommending git master for a while now, maybe
it is time to make a release.

Also, name change. Rather then go to 0.10.x, let's simple call
it version 10. Somewhere along the line, Icarus Verilog became
production ready while we weren't looking. I think the leading
zero is no longer informative.

- -- 
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."
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=/jyw
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Re: [Iverilog-devel] Pull request

[Stephen W. <st...@ic...>]

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Hash: SHA1


I'll look at it fairly promptly.

Thanks,

On 03/27/2015 01:17 PM, Maciej Sumiński wrote:
> Hi Steve,
> 
> This time I have just a minor update that brings support for using 
> function calls in concatenations and a few fixes [1,2].
> 
> I would be grateful if you could review at least the two commits
> related to ivl. Nothing is broken according to the test suite
> (moreover, the changes seem to fix some problems), but I am not
> always sure if I put solutions in the right place. Thank you in
> advance.
> 
> Regards, Orson
> 
> 1. https://github.com/steveicarus/iverilog/pull/56 2.
> https://github.com/orsonmmz/ivtest/tree/expfunc_test
> 


- -- 
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."
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=iMEN
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[Iverilog-devel] Pull request

[Maciej S. <mac...@ce...>]

Hi Steve,

This time I have just a minor update that brings support for using
function calls in concatenations and a few fixes [1,2].

I would be grateful if you could review at least the two commits related
to ivl. Nothing is broken according to the test suite (moreover, the
changes seem to fix some problems), but I am not always sure if I put
solutions in the right place. Thank you in advance.

Regards,
Orson

1. https://github.com/steveicarus/iverilog/pull/56
2. https://github.com/orsonmmz/ivtest/tree/expfunc_test

Re: [Iverilog-devel] iverilog - constant user function.

[Martin W. <mai...@ma...>]

dp...@sw... wrote:

 >> Most likely something inside the module is also assigning a value to R.
>
> My code structure bellow:
> core_rst is defined as output in module1, and R is input in a few ODDR2
> modules I instantiate in the main_module
> However R is defined with a ‘pulldown’ and I guess this explains the
> warning?
> ODDR2 Is from standard Xilinx
> /opt/Xilinx/14.7/ISE_DS/ISE/verilog/src/unisims/ODDR2.v
>
Yes, the pulldown will cause this.

Labelling a port as "input" in Verilog does not do what you would expect it 
to. You might find these of help:

 
http://www.sutherland-hdl.com/papers/2006-SNUG-Boston_standard_gotchas_paper.pdf

   http://www.sutherland-hdl.com/papers/2007-SNUG-SanJose_gotcha_again_paper.pdf

Martin

Re: [Iverilog-devel] Crash on invalid indexing of generate block

[Martin W. <mai...@ma...>]

ni...@ly... (Niels Möller) wrote:
> For the attached (broken) code, I get the following error, and a
> segmentation fault. I'm using iverilog compiled from the repo.
>
>    $ iverilog ctz-reduced.vl
>    ctz-reduced.vl:28: error: Scope index expression is not constant: ((n)-(k))-('sd1)
>    ctz-reduced.vl:28: XXXXX: Errors evaluating scope index
>    ctz-reduced.vl:28: error: Scope index expression is not constant: ((n)-(k))-('sd1)
>    ctz-reduced.vl:28: XXXXX: Errors evaluating scope index
>    ctz-reduced.vl:28: error: Unable to bind wire/reg/memory `REDUCE[((n)-(k))-('sd1)].r[('sd2)*(cnt[(n)-('sd1):((n)-(k))+('sd1)])]' in `ctz'
>    Segmentation fault
>
> (I have a working version too, using a second generate block. I wasn't
> sure if that was necessary, but it seems one can't use regular variables
> (i.e., not params or genvar) when indexing generate blocks).
>
Yes, the index must be a constant expression. From the standard:

   hierarchical_identifier ::=
     { identifier [ [ constant_expression ] ] . } identifier

The segfault is poor error recovery, so needs to be fixed.

Martin

Re: [Iverilog-devel] iverilog for syntesis

[Martin W. <mai...@ma...>]

dp...@sw... wrote:
> Hello,
>
> I am trying to use Icarus Verilog for implementation of my Verilog HDL in Xilinx xc6slx9-tqg144-2 target.
>
> I can successfully compile for a simulation target with the line
> iverilog -o DSLogic -I ./src/i2c/ -y ./ISE/unisims/  ./ISE/XilinxCoreLib/FIFO_GENERATOR_V8_2.v ./ISE/Verilog/src/glbl.v $(MY_VERILOG_FILES)
>
> What is the command I should use to get data suitable for the Xilinx ngdbuild tool?
>
iverilog is primarily a simulator. It has some very basic synthesis 
capabilities, but not enough for serious use as a synthesis tool. Your easiest 
option is to use the Xilinx synthesis tool (Xst) - you will have to use the 
Xilinx tools anyway for place&route and bitstream generation. If you do want 
to experiment with open-source alternatives, 
http://www.clifford.at/yosys/about.html is a possibility (although not one 
I've tried myself).

Martin

Re: [Iverilog-devel] iverilog - constant user function.

[<dp...@sw...>]

Hello

>> I am getting few warnings however.
>> Please ignore if this is not the best place to ask such a questions.

>This list is really for discussing things specific to Icarus Verilog - you
>might try comp.lang.verilog for more general questions. But a few quick 
>comments:

>> ./src/DSLogic_top.v:315: warning: input port R is coerced to inout.
>> I have confirmed that R s an input which is supplied by the output of 
>> other module.
>> Any typical reasons we could get this ‘coerced’ issue?

>Most likely something inside the module is also assigning a value to R.

My code structure bellow:
core_rst is defined as output in module1, and R is input in a few ODDR2 
modules I instantiate in the main_module
However R is defined with a ‘pulldown’ and I guess this explains the 
warning?
ODDR2 Is from standard Xilinx 
/opt/Xilinx/14.7/ISE_DS/ISE/verilog/src/unisims/ODDR2.v

module   main_module ()
...
wire core_rst;
...
module1 module1(..., .core_rst(core_rst), ...) //core_rst is defined as 
output in module1
module2 module2(..., .core_rst(core_rst), ...) //core_rst is defined as 
input in module2
module3 module3(..., .core_rst(core_rst), ...) //core_rst is defined as 
input in module3
...
ODDR2 #(
      .DDR_ALIGNMENT("C0"),
      .INIT(1'b0),
    .SRTYPE("ASYNC")
) trig_oe_oddr (
      .Q(ext_trig_oe_oddr),
      .C0(adc_clkb),
      .C1(~adc_clkb),
      .CE(1'b1),
      .D0(~ext_pin_oe),
      .D1(~ext_pin_oe),
      .R(core_rst),       // <= coerced  warning referring here, R is 
defined as input in
      .S(1'b0)
);

ODDR2 #(
      .DDR_ALIGNMENT("C0"),
      .INIT(1'b0),
    .SRTYPE("ASYNC")
) clk_oe_oddr (
      .Q(ext_trig_oe_oddr),
      .C0(adc_clkb),
      .C1(~adc_clkb),
      .CE(1'b1),
      .D0(~ext_pin_oe),
      .D1(~ext_pin_oe),
      .R(core_rst),         // <= coerced  warning referring here
      .S(1'b0)
);

...

end

Best Regards
Dimitar 

[Iverilog-devel] Crash on invalid indexing of generate block

[<ni...@ly...>]

For the attached (broken) code, I get the following error, and a
segmentation fault. I'm using iverilog compiled from the repo.

  $ iverilog ctz-reduced.vl
  ctz-reduced.vl:28: error: Scope index expression is not constant: ((n)-(k))-('sd1)
  ctz-reduced.vl:28: XXXXX: Errors evaluating scope index
  ctz-reduced.vl:28: error: Scope index expression is not constant: ((n)-(k))-('sd1)
  ctz-reduced.vl:28: XXXXX: Errors evaluating scope index
  ctz-reduced.vl:28: error: Unable to bind wire/reg/memory `REDUCE[((n)-(k))-('sd1)].r[('sd2)*(cnt[(n)-('sd1):((n)-(k))+('sd1)])]' in `ctz'
  Segmentation fault

(I have a working version too, using a second generate block. I wasn't
sure if that was necessary, but it seems one can't use regular variables
(i.e., not params or genvar) when indexing generate blocks).

Regards,
/Niels

Re: [Iverilog-devel] Assertion failure for system verilog structs

[<ni...@ly...>]

Martin Whitaker <mai...@ma...> writes:

> Yes, the problem was that the compilation of the parent net was delayed 
> (pending resolution of another symbol lookup), which meant that when the PV 
> expression was compiled, the VPI handle for the parent wasn't available.
>
> I've pushed a fix for this to the master branch on GitHub.

I've updated to the new version, and it no longer crashes on my test
case.

Thanks!
/Niels

-- 
Niels Möller. PGP-encrypted email is preferred. Keyid C0B98E26.
Internet email is subject to wholesale government surveillance.

[Iverilog-devel] iverilog for syntesis

[<dp...@sw...>]

Hello,

I am trying to use Icarus Verilog for implementation of my Verilog HDL in Xilinx xc6slx9-tqg144-2 target.

I can successfully compile for a simulation target with the line
iverilog -o DSLogic -I ./src/i2c/ -y ./ISE/unisims/  ./ISE/XilinxCoreLib/FIFO_GENERATOR_V8_2.v ./ISE/Verilog/src/glbl.v $(MY_VERILOG_FILES)

What is the command I should use to get data suitable for the Xilinx ngdbuild tool?

Thanks,
Dimitar

Re: [Iverilog-devel] iverilog - constant user function.

[Martin W. <mai...@ma...>]

dp...@sw... wrote:
> I am getting few warnings however.
> Please ignore if this is not the best place to ask such a questions.

This list is really for discussing things specific to Icarus Verilog - you 
might try comp.lang.verilog for more general questions. But a few quick comments:

> ./src/DSLogic_top.v:315: warning: input port R is coerced to inout.
> I have confirmed that R s an input which is supplied by the output of other module.
> Any typical reasons we could get this ‘coerced’ issue?

Most likely something inside the module is also assigning a value to R.

> ./ISE/XilinxCoreLib/FIFO_GENERATOR_V8_2.v:3202: warning: @* found no sensitivities so it will never trigger.
> This is on the line 3202
> ...
> always @* rst_full_gen_i <= 1'b0;
> ...
> I guess this is more an issue of ./ISE/XilinxCoreLib/FIFO_GENERATOR_V8_2.v as we assigned constant here, so no sensitivity?

Yes, this assignment will never get executed because there is nothing to 
trigger the always statement.

Martin

Re: [Iverilog-devel] Assertion failure for system verilog structs

[Martin W. <mai...@ma...>]

Cary R. wrote:
> Hi Martin, I'm guessing that the difference is $display can work with
> automatic variables and things like $strobe (which also fails) and $monitor
> cannot so we have to check to see if the variable is automatic. I think the
> problem is that between step 5 and 6 the reference to the net is being lost
> while trying to determine if the argument is to an automatic variable (or
> in this case part of an automatic variable) or not. It almost looks like we
> are loosing the pointer to the parent for the PV structure,
> vvp_lookup_handle() is failing? We would need to run this with a runtime
> compiled with -O0 and -g to get the true back trace.
>
Yes, the problem was that the compilation of the parent net was delayed 
(pending resolution of another symbol lookup), which meant that when the PV 
expression was compiled, the VPI handle for the parent wasn't available.

I've pushed a fix for this to the master branch on GitHub.

I'll see about adding a "sorry" message for non-packed structs later in the 
week unless you or Steve get to it first.

Martin

Re: [Iverilog-devel] iverilog - constant user function.

[<dp...@sw...>]

Hi Gents,

I have managed to build my code with the latest iverilog, thanks.

I am getting few warnings however. 
Please ignore if this is not the best place to ask such a questions. 
------------------------
./src/DSLogic_top.v:315: warning: input port R is coerced to inout.
I have confirmed that R s an input which is supplied by the output of other module.
Any typical reasons we could get this ‘coerced’ issue?
-----------------------
./ISE/XilinxCoreLib/FIFO_GENERATOR_V8_2.v:3202: warning: @* found no sensitivities so it will never trigger.
This is on the line 3202 
...
always @* rst_full_gen_i <= 1'b0;
...
I guess this is more an issue of ./ISE/XilinxCoreLib/FIFO_GENERATOR_V8_2.v as we assigned constant here, so no sensitivity?


Thanks.
Dimitar 





From: dp...@sw... 
Sent: Monday, March 16, 2015 23:15
To: Discussions concerning Icarus Verilog development 
Subject: Re: [Iverilog-devel] iverilog - constant user function.

Thank you Gents about your advices!
I will try to follow them

Best Regards
Dimitar 


From: Iztok Jeras 
Sent: Monday, March 16, 2015 22:51
To: Discussions concerning Icarus Verilog development 
Subject: Re: [Iverilog-devel] iverilog - constant user function.

Yosys seems to support Xilinx FPGA synthesis, but I would recommend Xilinx tools. 
http://www.clifford.at/yosys/cmd_synth_xilinx.html


And yes, Vivado is a pain, many things do not work as documented, but there is SystemVerilog support and I am not going back.

Regards,
Iztok Jeras

On Mon, Mar 16, 2015 at 9:44 PM, Larry Doolittle <ldo...@re...> wrote:

  Friends -

  On Mon, Mar 16, 2015 at 08:08:37PM +0000, Martin Whitaker wrote:
  > dp...@sw... wrote:
  > > Assuming I manage to fix this is there a comand line tools in Linux able to implement bitstream for Xilinx XC6SLX9 devices
  > Last time I used them (which was a few years ago), the Xilinx tools worked
  > well from the Linux command line. All my FPGA builds were done via Linux shell
  > scripts.

  That is still true today.  The XC6SLX9 is smaller than I have used,
  but I can personally vouch for the 16 and 45.  This is with ISE 12.x
  or 14.x.  Vivado is a pain, just because it's different, but a friend
  of mine has that running too.

  > The GUI could be used in Linux too, although I never bothered with it.

  Ditto.

  > I am not aware of any third-party tools that can generate bitstreams for
  > Xilinx devices.

  I have been told that every time a third-party synthesizer comes out,
  it's either terrible and gets dropped, or it's better than Xilinx and
  Xilinx buys the company so they can roll it in to their next release.
  The latter process has happened several times.

  Sometimes it seems that there are open-source synthesizers that are on
  the edge of being or becoming useful.  Icarus 0.8, for instance, or
  some talks by Sebastien Bourdeauducq, or Wolfgang Spraul's fpgatools.
  I've noticed recently that Xilinx has started using the ABC code base.

    - Larry


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Re: [Iverilog-devel] Assertion failure for system verilog structs

[Cary R. <cy...@ya...>]

Hi Martin,
I'm guessing that the difference is $display can work with automatic variables and things like $strobe (which also fails) and $monitor cannot so we have to check to see if the variable is automatic. I think the problem is that between step 5 and 6 the reference to the net is being lost while trying to determine if the argument is to an automatic variable (or in this case part of an automatic variable) or not. It almost looks like we are loosing the pointer to the parent for the PV structure, vvp_lookup_handle() is failing? We would need to run this with a runtime compiled with -O0 and -g to get the true back trace.

 Cary


     On Monday, March 16, 2015 3:16 PM, Martin Whitaker <mai...@ma...> wrote:
   

 ni...@ly... (Niels Möller) wrote:
> Martin Whitaker <mai...@ma...> writes:
>
>> I have reproduced the first failure, but not the second. Could you provide a
>> simple test case that demonstrates it?
>
> It seems a bit tricky to reproduce, I also don't see the problem with my
> current code. Maybe it's not really related to structs, I don't know.
>
Yes, it's a more general problem. Reducing your code, I ended up with this:

  wire [7:0] my_net;

  assign my_net[3:0] = 1;

  initial begin
    #1 $monitor("At time %0t, field1 = %h", $time, my_net[3:0]);
    #1 $finish;
  end

Passing a part select of a wire to $monitor seems to be the issue. $display 
doesn't have the problem.

This code works in v0.9, so it's a regression.

Martin

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Re: [Iverilog-devel] Assertion failure for system verilog structs

[Martin W. <mai...@ma...>]

ni...@ly... (Niels Möller) wrote:
> Martin Whitaker <mai...@ma...> writes:
>
>> I have reproduced the first failure, but not the second. Could you provide a
>> simple test case that demonstrates it?
>
> It seems a bit tricky to reproduce, I also don't see the problem with my
> current code. Maybe it's not really related to structs, I don't know.
>
Yes, it's a more general problem. Reducing your code, I ended up with this:

   wire [7:0] my_net;

   assign my_net[3:0] = 1;

   initial begin
     #1 $monitor("At time %0t, field1 = %h", $time, my_net[3:0]);
     #1 $finish;
   end

Passing a part select of a wire to $monitor seems to be the issue. $display 
doesn't have the problem.

This code works in v0.9, so it's a regression.

Martin

Re: [Iverilog-devel] vvp runtime error

[Cary R. <cy...@ya...>]

Hi Lonnie,
We have not done a snapshot since this was fixed. Steve normally announces snapshots when they are released and I believe he dates them so you would need to look for a snapshot that was newer than the one where you discovered the problem. There is also still one known issue related to zero-replications that I have not had time to research and verify what the correct fix is.

Cary
 


     On Thursday, March 5, 2015 8:53 AM, Lonnie L Gliem <lg...@sr...> wrote:
   

 #yiv7727319946 -- filtered {font-family:Helvetica;panose-1:2 11 6 4 2 2 2 2 2 4;}#yiv7727319946 filtered {font-family:Helvetica;panose-1:2 11 6 4 2 2 2 2 2 4;}#yiv7727319946 filtered {font-family:Calibri;panose-1:2 15 5 2 2 2 4 3 2 4;}#yiv7727319946 filtered {font-family:Tahoma;panose-1:2 11 6 4 3 5 4 4 2 4;}#yiv7727319946 p.yiv7727319946MsoNormal, #yiv7727319946 li.yiv7727319946MsoNormal, #yiv7727319946 div.yiv7727319946MsoNormal {margin:0in;margin-bottom:.0001pt;font-size:12.0pt;}#yiv7727319946 a:link, #yiv7727319946 span.yiv7727319946MsoHyperlink {color:blue;text-decoration:underline;}#yiv7727319946 a:visited, #yiv7727319946 span.yiv7727319946MsoHyperlinkFollowed {color:purple;text-decoration:underline;}#yiv7727319946 span.yiv7727319946EmailStyle17 {color:#1F497D;}#yiv7727319946 .yiv7727319946MsoChpDefault {font-size:10.0pt;}#yiv7727319946 filtered {margin:1.0in 1.0in 1.0in 1.0in;}#yiv7727319946 div.yiv7727319946WordSection1 {}#yiv7727319946 Hi Cary,Do you know if this is in a snapshot yet. How can I check?ThanksLonnie  From: Cary R. [mailto:cy...@ya...] 
Sent: Monday, February 02, 2015 6:27 PM
To: Discussions concerning Icarus Verilog development
Subject: Re: [Iverilog-devel] vvp runtime error  Okay, there are still a few other issues since nested replications do not correctly check for a zero replication at a lower level which was why I thought I may have to keep the zero width check. (e.g. {{2{{0{sign}}}}, 16'h0001} should report that a zero width (zero replication) cannot be replicated. A zero replication is only allowed in a concatenation/replication if it is also included with another non-zero width element. There are likely other degenerate cases (e.g. {{0{sign}}, {0{lsb}}}, etc.) that need to be checked and reported in the compiler.  And then all this needs to be check for constant and non-constant values being replicated. Constant-constant is done in the compiler, constant-variable is done in the run time.  Cary  On Monday, February 2, 2015 4:00 PM, Stephen Williams <st...@ic...> wrote:  -----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1


I kinda think this should be restricted to zero-replications,
and NOT zero-width expressions in general. I would rather catch
the latter is an error, or something.

On 02/02/2015 03:43 PM, Cary R. wrote:
> A patch for this has been pushed to git.
> 
> The issues was that zero replications inside of concatenations
> were generating incorrect vvp code for the new stack based vector
> operators. For the moment this code checks to see if the
> sub-expression width is zero. A more specific fix would check to
> see if the sub-expression was a concatenation that had a zero
> replication. I can easily change the code if needed, but the zero
> width may be better if other things can also generate a zero width
> result. I don't know of any, but there may be SystemVerilog
> constructs that can do this. Does anyone have an opinion on this or
> know of a construct that can do this?
> 
> Cary
> 
> 
> On Monday, February 2, 2015 10:20 AM, Cary R. <cy...@ya...>
> wrote:
> 
> 
> Hi Lonnie,
> 
> I was able to reduce this example down even further. It looks like
> the problem is that when Steve switched to the new stack code
> something broke concerning zero replications. At the moment an
> input width of 32 is getting a sign bit added which gives a width
> of 33 instead of 32. I will try to look at this later today.
> 
> Cary
> 
> 
> On Monday, February 2, 2015 9:03 AM, Lonnie Gliem 
> <lg...@sr...> wrote:
> 
> 
> Hi Cary, I found the code causing the error and have attahced a
> small verilog file that causes it.
> 
> iverilog iverilog_core.v
> 
> Then run it. [lgliem@ajax <mailto:lgliem@ajax> ulogic_sim]$
> ./a.out Fun: 0x7ba500 is for variable clk Fun: 0x7ba550 is for
> variable data_in_tmp Current vector
> is:32'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX New value
> is:33'bZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ vvp: vvp_net_sig.cc:185:
> virtual void vvp_fun_signal4_sa::recv_vec4(vvp_net_ptr_t, const
> vvp_vector4_t&, void**): Assertion `bit.size() == bits4_.size()'
> failed. Aborted (core dumped)
> 
> Lonnie
> 
> 
> 
> 
> 
> 
> 
> ------------------------------------------------------------------------------
>
> 
Dive into the World of Parallel Programming. The Go Parallel Website,
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> Media, is your hub for all things parallel software development,
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- -- 
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com          But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."
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Version: GnuPG v2

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F+8AoOuTKqoQMRyYVpPDtm7JD8yYYVrF
=qK5u
-----END PGP SIGNATURE-----

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Re: [Iverilog-devel] Assertion failure for system verilog structs

[Cary R. <cy...@ya...>]

I don't have time to look at this right now, but it looks like the problem could be related to the instr_op net  being driven from a function in an assignment statement. I'm guessing that Icarus is treating that function as an automatic function since it is in an assignment statement and is then having a problem finding the actual driver for the individual pieces of the net from the VPI interface. Given the current implementation I'm guessing the $monitor will also fire for any change in instr_op not just when the specified parts change value. I'm not certain if that is correct behavior or not.

The compiler code looks okay given how Steve implemented this (the two references to instr_op in the $monitor are part selects of the base instr_op vector at the correct offset and width).
Cary 


     On Monday, March 16, 2015 2:11 PM, Niels Möller <ni...@ly...> wrote:
   

 Martin Whitaker <mai...@ma...> writes:

> I have reproduced the first failure, but not the second. Could you provide a 
> simple test case that demonstrates it?

It seems a bit tricky to reproduce, I also don't see the problem with my
current code. Maybe it's not really related to structs, I don't know.

I've digged up the version of the code I used when experiencing the
problem. I'm attaching the preprocessed source code (close to 300 lines,
so not too huge, I hope. I don't have the time to reduce it further
tonight).

To reproduce,

  $ iverilog -g2005-sv main-preprocessed.vl
  $ ./a.out
  vpi error: bad global property: 50
  vvp: vpi_priv.cc:281: int vpip_get_global(int): Assertion `0' failed.
  Aborted

iverilog -v says

  Icarus Verilog version 0.10.0 (devel) (s20141205-283-g437dc10)

Best regards,
/Niels



-- 
Niels Möller. PGP-encrypted email is preferred. Keyid C0B98E26.
Internet email is subject to wholesale government surveillance.
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Re: [Iverilog-devel] iverilog - constant user function.

[<dp...@sw...>]

Thank you Gents about your advices!
I will try to follow them

Best Regards
Dimitar 


From: Iztok Jeras 
Sent: Monday, March 16, 2015 22:51
To: Discussions concerning Icarus Verilog development 
Subject: Re: [Iverilog-devel] iverilog - constant user function.

Yosys seems to support Xilinx FPGA synthesis, but I would recommend Xilinx tools. 
http://www.clifford.at/yosys/cmd_synth_xilinx.html


And yes, Vivado is a pain, many things do not work as documented, but there is SystemVerilog support and I am not going back.

Regards,
Iztok Jeras

On Mon, Mar 16, 2015 at 9:44 PM, Larry Doolittle <ldo...@re...> wrote:

  Friends -

  On Mon, Mar 16, 2015 at 08:08:37PM +0000, Martin Whitaker wrote:
  > dp...@sw... wrote:
  > > Assuming I manage to fix this is there a comand line tools in Linux able to implement bitstream for Xilinx XC6SLX9 devices
  > Last time I used them (which was a few years ago), the Xilinx tools worked
  > well from the Linux command line. All my FPGA builds were done via Linux shell
  > scripts.

  That is still true today.  The XC6SLX9 is smaller than I have used,
  but I can personally vouch for the 16 and 45.  This is with ISE 12.x
  or 14.x.  Vivado is a pain, just because it's different, but a friend
  of mine has that running too.

  > The GUI could be used in Linux too, although I never bothered with it.

  Ditto.

  > I am not aware of any third-party tools that can generate bitstreams for
  > Xilinx devices.

  I have been told that every time a third-party synthesizer comes out,
  it's either terrible and gets dropped, or it's better than Xilinx and
  Xilinx buys the company so they can roll it in to their next release.
  The latter process has happened several times.

  Sometimes it seems that there are open-source synthesizers that are on
  the edge of being or becoming useful.  Icarus 0.8, for instance, or
  some talks by Sebastien Bourdeauducq, or Wolfgang Spraul's fpgatools.
  I've noticed recently that Xilinx has started using the ABC code base.

    - Larry


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Re: [Iverilog-devel] Assertion failure for system verilog structs

[<ni...@ly...>]

Martin Whitaker <mai...@ma...> writes:

> I have reproduced the first failure, but not the second. Could you provide a 
> simple test case that demonstrates it?

It seems a bit tricky to reproduce, I also don't see the problem with my
current code. Maybe it's not really related to structs, I don't know.

I've digged up the version of the code I used when experiencing the
problem. I'm attaching the preprocessed source code (close to 300 lines,
so not too huge, I hope. I don't have the time to reduce it further
tonight).

To reproduce,

  $ iverilog -g2005-sv main-preprocessed.vl
  $ ./a.out
  vpi error: bad global property: 50
  vvp: vpi_priv.cc:281: int vpip_get_global(int): Assertion `0' failed.
  Aborted

iverilog -v says

  Icarus Verilog version 0.10.0 (devel) (s20141205-283-g437dc10)

Best regards,
/Niels

Re: [Iverilog-devel] iverilog - constant user function.

[Iztok J. <izt...@gm...>]

Yosys seems to support Xilinx FPGA synthesis, but I would recommend Xilinx
tools.
http://www.clifford.at/yosys/cmd_synth_xilinx.html

And yes, Vivado is a pain, many things do not work as documented, but there
is SystemVerilog support and I am not going back.

Regards,
Iztok Jeras

On Mon, Mar 16, 2015 at 9:44 PM, Larry Doolittle <ldo...@re...>
wrote:

> Friends -
>
> On Mon, Mar 16, 2015 at 08:08:37PM +0000, Martin Whitaker wrote:
> > dp...@sw... wrote:
> > > Assuming I manage to fix this is there a comand line tools in Linux
> able to implement bitstream for Xilinx XC6SLX9 devices
> > Last time I used them (which was a few years ago), the Xilinx tools
> worked
> > well from the Linux command line. All my FPGA builds were done via Linux
> shell
> > scripts.
>
> That is still true today.  The XC6SLX9 is smaller than I have used,
> but I can personally vouch for the 16 and 45.  This is with ISE 12.x
> or 14.x.  Vivado is a pain, just because it's different, but a friend
> of mine has that running too.
>
> > The GUI could be used in Linux too, although I never bothered with it.
>
> Ditto.
>
> > I am not aware of any third-party tools that can generate bitstreams for
> > Xilinx devices.
>
> I have been told that every time a third-party synthesizer comes out,
> it's either terrible and gets dropped, or it's better than Xilinx and
> Xilinx buys the company so they can roll it in to their next release.
> The latter process has happened several times.
>
> Sometimes it seems that there are open-source synthesizers that are on
> the edge of being or becoming useful.  Icarus 0.8, for instance, or
> some talks by Sebastien Bourdeauducq, or Wolfgang Spraul's fpgatools.
> I've noticed recently that Xilinx has started using the ABC code base.
>
>   - Larry
>
>
> ------------------------------------------------------------------------------
> Dive into the World of Parallel Programming The Go Parallel Website,
> sponsored
> by Intel and developed in partnership with Slashdot Media, is your hub for
> all
> things parallel software development, from weekly thought leadership blogs
> to
> news, videos, case studies, tutorials and more. Take a look and join the
> conversation now. http://goparallel.sourceforge.net/
> _______________________________________________
> Iverilog-devel mailing list
> Ive...@li...
> https://lists.sourceforge.net/lists/listinfo/iverilog-devel
>

Re: [Iverilog-devel] iverilog - constant user function.

[Larry D. <ldo...@re...>]

Friends -

On Mon, Mar 16, 2015 at 08:08:37PM +0000, Martin Whitaker wrote:
> dp...@sw... wrote:
> > Assuming I manage to fix this is there a comand line tools in Linux able to implement bitstream for Xilinx XC6SLX9 devices
> Last time I used them (which was a few years ago), the Xilinx tools worked 
> well from the Linux command line. All my FPGA builds were done via Linux shell 
> scripts.

That is still true today.  The XC6SLX9 is smaller than I have used,
but I can personally vouch for the 16 and 45.  This is with ISE 12.x
or 14.x.  Vivado is a pain, just because it's different, but a friend
of mine has that running too.

> The GUI could be used in Linux too, although I never bothered with it.

Ditto.

> I am not aware of any third-party tools that can generate bitstreams for 
> Xilinx devices.

I have been told that every time a third-party synthesizer comes out,
it's either terrible and gets dropped, or it's better than Xilinx and
Xilinx buys the company so they can roll it in to their next release.
The latter process has happened several times.

Sometimes it seems that there are open-source synthesizers that are on
the edge of being or becoming useful.  Icarus 0.8, for instance, or 
some talks by Sebastien Bourdeauducq, or Wolfgang Spraul's fpgatools.
I've noticed recently that Xilinx has started using the ABC code base.

  - Larry

Re: [Iverilog-devel] Assertion failure for system verilog structs

[Martin W. <mai...@ma...>]

I have reproduced the first failure, but not the second. Could you provide a 
simple test case that demonstrates it? It would be good if you could do this 
via the bug tracker (http://sourceforge.net/p/iverilog/bugs/) - that makes 
sure we can't forget about it!

Thanks,

Martin

ni...@ly... (Niels Möller) wrote:
> Hi,
>
> I'm still trying to learn verilog and system verilog. This time playing
> with struct (the idea is to define a combinatorial function which takes
> an opcode and some other cpu state as input and returns a larger struct
> more suitable for executing the instruction).
>
> I'm using iverilog compiled from commit
>
>    commit 437dc103416dd2bca99cccdaca4aacfec3411f36
>    Merge: 102d2d5 d1dc98b
>    Author: Stephen Williams <st...@ic...>
>    Date:   Thu Mar 12 10:30:56 2015 -0700
>
>        Merge pull request #55 from orsonmmz/const_record
>
>        Const record
>
> running on a debian gnu/linux box, x86_64. First I got compilation
> failures with
>
>    ex.vl:1: assert: pform_struct_type.cc:83: failed assertion 0
>    Aborted
>
> Looking up that line, it seems non-packed structs are not yet supported
> (an error message saying so would be nicer than an assert...). So I
> added the packed keyword, without understanding what it really means in
> system verilog, and that made the compiler happy.
>
> But now I get an assertion failure from vvp instead,
>
>    vpi error: bad global property: 50
>    vvp: vpi_priv.cc:281: int vpip_get_global(int): Assertion `0' failed.
>    Aborted (core dumped)
>
> The number 50 seems to be vpiAutomatic (from a call in sys_check_args).
> But I'm a bit lost here. Backtrace is as follows:
>
>    (gdb) bt
>    #0  0x00007f6057bf8107 in __GI_raise (sig=sig@entry=6)
>        at ../nptl/sysdeps/unix/sysv/linux/raise.c:56
>    #1  0x00007f6057bf94e8 in __GI_abort () at abort.c:89
>    #2  0x00007f6057bf1226 in __assert_fail_base (
>        fmt=0x7f6057d27ce8 "%s%s%s:%u: %s%sAssertion `%s' failed.\n%n",
>        assertion=assertion@entry=0x4e188e "0",
>        file=file@entry=0x4e2c21 "vpi_priv.cc", line=line@entry=281,
>        function=function@entry=0x4e3690 <vpip_get_global(int)::__PRETTY_FUNCTION__> "int vpip_get_global(int)") at assert.c:92
>    #3  0x00007f6057bf12d2 in __GI___assert_fail (assertion=0x4e188e "0",
>        file=0x4e2c21 "vpi_priv.cc", line=281,
>        function=0x4e3690 <vpip_get_global(int)::__PRETTY_FUNCTION__> "int vpip_get_global(int)") at assert.c:101
>    #4  0x00000000004ac29f in vpip_get_global (property=50)
>        at vpi_priv.cc:281
>    #5  vpi_get (property=50, ref=0x0) at vpi_priv.cc:392
>    #6  0x00000000004ac1b1 in vpi_get (property=50, ref=0x10eccd0)
>        at vpi_priv.cc:406
>    #7  0x00007f6057591bd2 in sys_check_args (callh=callh@entry=0x10ecf30,
>        argv=0x10c2f00, name=name@entry=0x7f60575b1106 "$monitor",
>        no_auto=no_auto@entry=1, is_monitor=is_monitor@entry=1)
>        at sys_display.c:1076
>    #8  0x00007f605759464e in sys_monitor_compiletf (
>        name=0x7f60575b1106 "$monitor") at sys_display.c:1461
>    #9  0x000000000045b616 in compile_cleanup () at compile.cc:784
>    #10 0x0000000000442761 in main (argc=3, argv=0x7fff9180e368)
>        at main.cc:457
>
> My test and debugging code includes the command
>
>       $monitor ("At time %t: pc: %x, instr: %x, instr_valid: %d\n  imm_value: %x, src_value: %x\n  imm_op: %d, prefix_active: %d, prefix: %x",
> 	       $time, main_cpu.pc, main_cpu.instr, main_cpu.instr_valid,
> 	       main_cpu.instr_op.imm_value, main_cpu.src_value,
> 	       main_cpu.instr_op.imm_op, main_cpu.prefix_active, main_cpu.prefix);
>
> where main_cpu.instr_op is a struct type defined by
>
>    typedef struct packed {
>       bit [63:0] imm_value;
>       bit        imm_op;
>       bit        imm_sign;
>       bit [3:0]  dreg;
>       bit [3:0]  sreg;
>       bit        write_dst;
>       bit [3:0]  op_type;
>       bit [3:0]  op;
>    } DECODED_INSTR;
>
> Dropping these references from the $monitor command makes the problem go
> away, but then it is more difficult to track down the bugs in my own
> code...
>
> Best regards,
> /Niels
>

Re: [Iverilog-devel] iverilog - constant user function.

[Martin W. <mai...@ma...>]

dp...@sw... wrote:
> I am at the point now getting
>
> FIFO_GENERATOR_V8_2.v:3336: sorry: constant user functions are not currently supported: log2_val().
> This is the original file from the Xilinx ISE
> Xilinx\14.7\ISE_DS\ISE\verilog\src\XilinxCoreLib\FIFO_GENERATOR_V8_2.v
>
> Can you please give me some hint solving this ?
>
Constant user functions are supported in the development branch of iverilog, 
so you will need to build and install a development snapshot to solve this. 
Instructions on how to do this can be found here:

   http://iverilog.wikia.com/wiki/Installation_Guide

> Assuming I manage to fix this is there a comand line tools in Linux able to implement bitstream for Xilinx XC6SLX9 devices
>
Last time I used them (which was a few years ago), the Xilinx tools worked 
well from the Linux command line. All my FPGA builds were done via Linux shell 
scripts. The GUI could be used in Linux too, although I never bothered with it.

I am not aware of any third-party tools that can generate bitstreams for 
Xilinx devices.

Martin