#42 support for SystemVerilog "end labels"

[Iztok Jeras]

Hi,

SystemVerilog ads the ability to provide labels/identifiers at the end of the module (also other hierarchical constructs). NCsim creates a warning, but this could also be a lint error, since it is very easy to fix. Ignoring the label (instead of a syntax error) would also be an acceptable partial solution.
The next constructs should support end identifiers (not sure which are or will be implemented in Icarus Verilog):
module/endmodule
package/endpackage
interface/endinterface
covergroup/endgroup
config/endconfig
program/endprogram
class/endclass
function/endfunction
task/endtask
property/endproperty
sequence/endsequence
begin/end (inside generate, always, fork/join, ... blocks)
primitive/endprimitive
fork/join|join_any|join_none
clocking/endclocking

Two examples are provided, one should pass, the other should fail compilation or at least report a warning.

Use the example code from: https://github.com/jeras/ivtest/tree/test_sv
iverilog -g2009 ivltests/sv_end_labels.v && vvp a.out
iverilog -g2009 ivltests/sv_end_labels_bad.v && vvp a.out
or the attached file.

Regards,
Iztok Jeras

[Iztok Jeras]

example Verilog code (2 files)

[Cary R.]

I have pushed a patch that should add end label support for all constructs that Icarus currently supports. If you find something that is supported by Icarus and it does not support an end label like it should please file a bug report.

[Stephen Williams]

At least some of these end labels are already supported due to
SV work I've been doing. In particular, classes, tasks, functions,
and packages should all use the endname_opt rule to support these.

On 05/14/2013 03:27 PM, Cary R. wrote:

I have pushed a patch that should add end label support for all
constructs that Icarus currently supports. If you find something that is
supported by Icarus and it does not support an end label like it should
please file a bug report.

---

[feature-requests:#42] support for SystemVerilog "end labels"

Status: closed
Created: Mon Apr 09, 2012 12:12 PM UTC by Iztok Jeras
Last Updated: Mon Dec 10, 2012 11:03 PM UTC
Owner: Cary R.

Hi,

SystemVerilog ads the ability to provide labels/identifiers at the end
of the module (also other hierarchical constructs). NCsim creates a
warning, but this could also be a lint error, since it is very easy to
fix. Ignoring the label (instead of a syntax error) would also be an
acceptable partial solution.
The next constructs should support end identifiers (not sure which are
or will be implemented in Icarus Verilog):
module/endmodule
package/endpackage
interface/endinterface
covergroup/endgroup
config/endconfig
program/endprogram
class/endclass
function/endfunction
task/endtask
property/endproperty
sequence/endsequence
begin/end (inside generate, always, fork/join, ... blocks)
primitive/endprimitive
fork/join|join_any|join_none
clocking/endclocking

Two examples are provided, one should pass, the other should fail
compilation or at least report a warning.

Use the example code from: https://github.com/jeras/ivtest/tree/test_sv
iverilog -g2009 ivltests/sv_end_labels.v && vvp a.out
iverilog -g2009 ivltests/sv_end_labels_bad.v && vvp a.out
or the attached file.

Regards,
Iztok Jeras

---

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