SystemVerilog ads the ability to provide labels/identifiers at the end of the module (also other hierarchical constructs). NCsim creates a warning, but this could also be a lint error, since it is very easy to fix. Ignoring the label (instead of a syntax error) would also be an acceptable partial solution.
The next constructs should support end identifiers (not sure which are or will be implemented in Icarus Verilog):
begin/end (inside generate, always, fork/join, ... blocks)
Two examples are provided, one should pass, the other should fail compilation or at least report a warning.
Use the example code from: https://github.com/jeras/ivtest/tree/test_sv
iverilog -g2009 ivltests/sv_end_labels.v && vvp a.out
iverilog -g2009 ivltests/sv_end_labels_bad.v && vvp a.out
or the attached file.
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