According to Chris:
> http://www.chris.spear.net/pli/default.htm
> If you are using the latest version of VCS, NC-Verilog, and ModelSim, this is already built into your simulator.
would be nice if this would be built into iverilog too ...
verilog-20070408/bin/iverilog test.v
a.out
$fopenr: This task not defined by any modules. I cannot compile it.
a.out: Program not runnable, 1 errors.
module test;
parameter filename = "loadmem.tcl";
integer mem_file;
initial begin
mem_file = $fopenr(filename);
end
endmodule
Logged In: YES
user_id=1606747
Originator: YES
grrr, submitted to early, closed because of nondesciptive summary, replaced by 1697264