#974 SystemVerilog extensions to non-ANSI port declarations are not supported

[Neil Turton]

The following example fails to compile:
typedef logic data_t;

module iv_error2(d);
input data_t d;
endmodule // iv_error2

The errors are:
rtl/iv_error2.sv:4: syntax error
rtl/iv_error2.sv:4: error: Invalid variable list in port declaration.

According to IEEE Std 1800-2012:

Section A.2.1.2:
input_declaration ::=
[...]
| input variable_port_type list_of_variable_identifiers

Section A.2.2.1:
variable_port_type ::= var_data_type
var_data_type ::= data_type | [...]
data_type ::=
[...]
| [...] type_identifier [...]

[Martin Whitaker]

Sorry, this is a SystemVerilog feature that Icarus does not support yet. You can work round this by using ANSI style port declarations.

I've looked at getting the parser to recognise the new syntax and output a suitable "sorry" message, but the limitations of a yacc-based parser make this too hard.

[Neil Turton]

Hi Martin. Thanks for the work-around. That will let me make progress.

[x127]

This also affects array ports, e.g. input wire [7:0] foo[0:5]; will not work. Even ANSI style array ports will not work, will open a feature request regarding that.

[Martin Whitaker]

I've pushed a fix for this to the master branch on GitHub.

Array syntax is recognised, but fails later in compilation in the same way as when using ansi-style port declarations.